From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:40550) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QcPeK-0001Cp-SD for qemu-devel@nongnu.org; Thu, 30 Jun 2011 18:23:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QcPeJ-0000lQ-BX for qemu-devel@nongnu.org; Thu, 30 Jun 2011 18:23:52 -0400 Received: from tx2ehsobe001.messaging.microsoft.com ([65.55.88.11]:18876 helo=TX2EHSOBE002.bigfish.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QcPeI-0000lI-SI for qemu-devel@nongnu.org; Thu, 30 Jun 2011 18:23:51 -0400 Date: Thu, 30 Jun 2011 17:23:45 -0500 From: Scott Wood Message-ID: <20110630172345.36994f31@schlenkerla.am.freescale.net> In-Reply-To: <9B335790-A8DA-4545-8746-F66B1B258FBF@suse.de> References: <1309180555-3942-1-git-send-email-chouteau@adacore.com> <20110627112807.22346e82@schlenkerla.am.freescale.net> <4E098E23.3040605@adacore.com> <20110628112008.31cf6237@schlenkerla.am.freescale.net> <4E0C32FB.40302@adacore.com> <20110630111745.7c544a06@schlenkerla.am.freescale.net> <86AF921C-3FD1-409A-ACFD-EEEA23BBE130@suse.de> <20110630164630.2bd57166@schlenkerla.am.freescale.net> <10F3D94F-5B79-4041-BFE7-58681B7E89CB@suse.de> <20110630171147.76eef3fc@schlenkerla.am.freescale.net> <9B335790-A8DA-4545-8746-F66B1B258FBF@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] Add e500 instructions dcblc, dcbtls and dcbtstl as no-op List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: qemu-devel@nongnu.org, Fabien Chouteau On Fri, 1 Jul 2011 00:18:22 +0200 Alexander Graf wrote: > > On 01.07.2011, at 00:11, Scott Wood wrote: > > > Almost, but what if we have write permission but not read? > > How would you write back data from a cache line when you haven't read it earlier? The CPU can read it. The program can't. > > but what about a race with DMA from the I/O thread? > > That'd simply be broken, but I don't quite see how it wouldn't with real hardware either :). Real hardware doesn't generate a load/store sequence that the program didn't ask for -- where's the breakage? -Scott