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Date: Fri, 22 Jul 2011 11:37:29 -0500
From: Scott Wood <scottwood@freescale.com>
Message-ID: <20110722113729.14036c41@schlenkerla.am.freescale.net>
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Subject: Re: [Qemu-devel] [PATCH 06/23] PPC: Fix IPI support in MPIC
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To: Alexander Graf <agraf@suse.de>
Cc: Elie Richa <richa@adacore.com>, QEMU-devel Developers <qemu-devel@nongnu.org>

On Fri, 22 Jul 2011 17:01:11 +0200
Alexander Graf <agraf@suse.de> wrote:

> On 22.07.2011, at 16:08, Elie Richa wrote:
> 
> > > #if MAX_IPI > 0
> > >     case 0x40: /* IDE */
> > >     case 0x50:
> > >         idx = (addr - 0x40) >> 4;
> > >         retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IDE);
> > >         break;
> > > #endif
> > 
> > These are the IPI dispatch registers which are write only, so I suppose this shouldn't be here right?
> 
> The code was there long before me :). No idea why it is there though - it tries to read out the IDE register for 2 IPIs. Maybe it was read-write in early versions of MPIC? Scott, any idea?

I don't know about early MPICs, but I don't know how you'd even define that
register for read -- it's a command, not state.

I suspect it's just a bug -- especially given the initialization to 1,
which suggests the author saw it as just another destination register.

-Scott