[Qemu-devel] [PATCH] mips: Support the MT TCStatus IXMT irq disable flag

[Qemu-devel] [PATCH] mips: Support the MT TCStatus IXMT irq disable flag

[Edgar E. Iglesias]

This one goes on top of the recently posted MIPS SMP patches.

It allows a linux MIPS SMTC kernel too boot with one VPE and
one thread.

Multiple threads per core still dont work.

Cheers

commit 063f70f8faf4b856bd0e3a4d9edac47c7d9aa2d4
Author: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Date:   Tue Aug 30 00:44:28 2011 +0200

    mips: Support the MT TCStatus IXMT irq disable flag
    
    Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index f6f16a3..79e2558 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -537,6 +537,10 @@ static inline int cpu_mips_hw_interrupts_pending(CPUState *env)
     if (!(env->CP0_Status & (1 << CP0St_IE)) ||
         (env->CP0_Status & (1 << CP0St_EXL)) ||
         (env->CP0_Status & (1 << CP0St_ERL)) ||
+        /* Note that the TCStatus IXMT field is initialized to zero,
+           and only MT capable cores can set it to one. So we don't
+           need to check for MT capabilities here.  */
+        (env->active_tc.CP0_TCStatus & (1 << CP0TCSt_IXMT)) ||
         (env->hflags & MIPS_HFLAG_DM)) {
         /* Interrupts are disabled */
         return 0;