From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:54902) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QzVze-0006M4-OS for qemu-devel@nongnu.org; Fri, 02 Sep 2011 11:49:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QzVzd-0003e7-JB for qemu-devel@nongnu.org; Fri, 02 Sep 2011 11:49:22 -0400 Received: from mx1.redhat.com ([209.132.183.28]:18912) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QzVzd-0003dx-CB for qemu-devel@nongnu.org; Fri, 02 Sep 2011 11:49:21 -0400 Date: Fri, 2 Sep 2011 18:45:50 +0300 From: "Michael S. Tsirkin" Message-ID: <20110902154549.GA18368@redhat.com> References: <20110901163359.GB11620@redhat.com> <786649703.1049386.1314909069542.JavaMail.root@zmail07.collab.prod.int.phx2.redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <786649703.1049386.1314909069542.JavaMail.root@zmail07.collab.prod.int.phx2.redhat.com> Subject: Re: [Qemu-devel] [PATCH] virtio: Make memory barriers be memory barriers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: aliguori@us.ibm.com, aik@ozlabs.ru, rusty@rustcorp.com.au, agraf@suse.de, qemu-devel@nongnu.org, David Gibson On Thu, Sep 01, 2011 at 04:31:09PM -0400, Paolo Bonzini wrote: > > > > Why not limit the change to ppc then? > > > > > > Because the bug is masked by the x86 memory model, but it is still > > > there even there conceptually. It is not really true that x86 does > > > not need memory barriers, though it doesn't in this case: > > > > > > http://bartoszmilewski.wordpress.com/2008/11/05/who-ordered-memory-fences-on-an-x86/ > > > > > > Paolo > > > > Right. > > To summarize, on x86 we probably want wmb and rmb to be compiler > > barrier only. Only mb might in theory need to be an mfence. > > No, wmb needs to be sfence and rmb needs to be lfence. GCC does > not provide those, so they should become __sync_synchronize() too, > or you should use inline assembly. > > > But there might be reasons why that is not an issue either > > if we look closely enough. > > Since the ring buffers are not using locked instructions (no xchg > or cmpxchg) the barriers simply must be there, even on x86. Whether > it works in practice is not interesting, only the formal model is > interesting. > > Paolo Well, can you describe an issue in virtio that lfence/sfence help solve in terms of a memory model please? Pls note that guest uses smp_ variants for barriers. -- MST