* [Qemu-devel] [PATCH 00/25] VMState port of all cpus
@ 2011-10-25 14:00 Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 01/25] vmstate: Fix VMSTATE_VARRAY_UINT32 Juan Quintela
` (24 more replies)
0 siblings, 25 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel
Cc: Huacai Chen, aliguori, Peter Maydell, Alexander Graf, Blue Swirl,
Max Filippov, Michael Walle, Paul Brook, Edgar E. Iglesias,
Aurelien Jarno, Richard Henderson
Hi
This series port all cpus to use vmstate.
- 1st patch is a fix of vmstate.
- I discussed the arm changes over irc with Peter, he agreed that some
simplification could be good, but he didn't saw the patches O:-)
- mips: no pci chipset has been ported, so migration don't work there.
I have embedded a couple of structs to improve vmstate checking. Notice
that they were always allocated, so there shouldn't be any problem.
- sparc: I changed the format a little bit to be able to use normal arrays.
- sparc: If we always send the whole register windows, we don't need
VMSTATE_VARRAY_MULTIPLY. As that array is quite big (520 elements), I am not
sure what is best.
- cpsr_vmstate on arm: I am not sure if I could "abuse" uncached_cpsr for that
purpose?
I have only tested on x86, for the rest, I double checked, but it is
possible that I missed something. I expect all patches to be
integrated by Anthony in one go. Architecture maintainers are CC'd
for an ACK/NACK/comments.
Please, review.
PD. Is there an easy way of creating this "CC" list of mail addresses,
or the only way is to edit comments and write it by hand as I did?
CC: Alexander Graf <agraf@suse.de>
CC: Aurelien Jarno <aurelien@aurel32.net>
CC: Blue Swirl <blauwirbel@gmail.com>
CC: Edgar E. Iglesias <edgar.iglesias@gmail.com>
CC: Huacai Chen <zltjiangshi@gmail.com>
CC: Max Filippov <jcmvbkbc@gmail.com>
CC: Michael Walle <michael@walle.cc>
CC: Michael Walle <michael@walle.cc>
CC: Paul Brook <paul@codesourcery.com>
CC: Peter Maydell <peter.maydell@linaro.org>
CC: Richard Henderson <rth@twiddle.net>
Juan Quintela (25):
vmstate: Fix VMSTATE_VARRAY_UINT32
vmstate: Simplify test for CPU_SAVE_VERSION
vmstate: make all architectures export a way to migrate cpu's
vmstate: unicore32 don't support cpu migration
vmstate: use new cpu style for x86
vmstate: use new style for lm32 cpus
vmstate: make microblaze cpus not migrateable
vmstate: port cris cpu to vmstate
vmstate: machine.c is only compiled for !CONFIG_USER_ONLY
vmstate: introduce float32 arrays
vmstate: introduce float64 arrays
vmstate: Introduce VMSTATE_STRUCT_VARRAY_INT32_TEST
vmstate: port ppc cpu
vmstate: introduce VMSTATE_VARRAY_MULTIPLY
vmstate: define vmstate_info_uinttls
vmstate: port sparc cpu
vmstate: make incompatible change for sparc
mips_fulong2e: cpu vmstate already registered in cpu_exec_init
mips: make mvp an embedded struct instead of pointer
mips: make tlb an embedded struct instead of a pointer
mips: bump migration version to 4
vmstate: port mips cpu
arm: save always 32 fpu registers
vmstate: port arm cpu
vmstate: all cpus converted
exec.c | 7 +-
hw/hw.h | 34 +++
hw/mips_fulong2e.c | 1 -
hw/mips_malta.c | 4 +-
hw/mips_timer.c | 2 +-
hw/sun4u.c | 20 --
qemu-common.h | 4 -
savevm.c | 68 ++++++
target-alpha/machine.c | 12 +-
target-arm/cpu.h | 4 +-
target-arm/machine.c | 350 +++++++++++++------------------
target-cris/cpu.h | 13 +-
target-cris/machine.c | 138 +++++--------
target-i386/cpu.h | 2 -
target-i386/machine.c | 14 +-
target-lm32/cpu.h | 2 -
target-lm32/machine.c | 14 +-
target-m68k/machine.c | 10 +
target-microblaze/cpu.h | 2 -
target-microblaze/machine.c | 15 +-
target-mips/cpu.h | 10 +-
target-mips/helper.c | 30 ++-
target-mips/machine.c | 468 ++++++++++++++++-------------------------
target-mips/op_helper.c | 70 ++++---
target-mips/translate.c | 22 ++-
target-mips/translate_init.c | 36 ++--
target-ppc/cpu.h | 4 +-
target-ppc/machine.c | 253 ++++++++---------------
target-s390x/machine.c | 14 +-
target-sh4/machine.c | 10 +
target-sparc/cpu.h | 8 +-
target-sparc/machine.c | 328 +++++++++++------------------
target-unicore32/cpu.h | 2 -
target-xtensa/machine.c | 14 +-
34 files changed, 852 insertions(+), 1133 deletions(-)
--
1.7.6.4
^ permalink raw reply [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 01/25] vmstate: Fix VMSTATE_VARRAY_UINT32
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 02/25] vmstate: Simplify test for CPU_SAVE_VERSION Juan Quintela
` (23 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
We didn't saved elemnts with that size (brown paper bag for me).
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
savevm.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/savevm.c b/savevm.c
index f01838f..557eba4 100644
--- a/savevm.c
+++ b/savevm.c
@@ -1457,6 +1457,8 @@ void vmstate_save_state(QEMUFile *f, const VMStateDescription *vmsd,
n_elems = field->num;
} else if (field->flags & VMS_VARRAY_INT32) {
n_elems = *(int32_t *)(opaque+field->num_offset);
+ } else if (field->flags & VMS_VARRAY_UINT32) {
+ n_elems = *(uint32_t *)(opaque+field->num_offset);
} else if (field->flags & VMS_VARRAY_UINT16) {
n_elems = *(uint16_t *)(opaque+field->num_offset);
} else if (field->flags & VMS_VARRAY_UINT8) {
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 02/25] vmstate: Simplify test for CPU_SAVE_VERSION
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 01/25] vmstate: Fix VMSTATE_VARRAY_UINT32 Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 03/25] vmstate: make all architectures export a way to migrate cpu's Juan Quintela
` (22 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Some cpu's definitions define CPU_SAVE_VERSION, others not, but they have
defined cpu_save/load.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
exec.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/exec.c b/exec.c
index 9dc4edb..165cfe8 100644
--- a/exec.c
+++ b/exec.c
@@ -591,7 +591,7 @@ void cpu_exec_init_all(void)
#endif
}
-#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
static int cpu_common_post_load(void *opaque, int version_id)
{
@@ -658,11 +658,13 @@ void cpu_exec_init(CPUState *env)
#if defined(CONFIG_USER_ONLY)
cpu_list_unlock();
#endif
-#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env);
+#if defined(CPU_SAVE_VERSION)
register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
cpu_save, cpu_load, env);
#endif
+#endif
}
/* Allocate a new translation block. Flush the translation buffer if
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 03/25] vmstate: make all architectures export a way to migrate cpu's
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 01/25] vmstate: Fix VMSTATE_VARRAY_UINT32 Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 02/25] vmstate: Simplify test for CPU_SAVE_VERSION Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 15:33 ` Andreas Färber
` (3 more replies)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 04/25] vmstate: unicore32 don't support cpu migration Juan Quintela
` (21 subsequent siblings)
24 siblings, 4 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, Alexander Graf, Max Filippov, Michael Walle, Paul Brook,
Aurelien Jarno, Richard Henderson
This makes several changes:
- exports VMStateDescription vmstate_cpu non-static.
- makes sure that every cpu has a vmstate_cpu or cpu_save/load defined
- for the architecture that had nothing, it just register the cpu as unmigratable.
- Depending on CPU_SAVE_VERSION we register old/new migration style
Signed-off-by: Juan Quintela <quintela@redhat.com>
CC: Richard Henderson <rth@twiddle.net>
CC: Michael Walle <michael@walle.cc>
CC: Paul Brook <paul@codesourcery.com>
CC: Alexander Graf <agraf@suse.de>
CC: Aurelien Jarno <aurelien@aurel32.net>
CC: Max Filippov <jcmvbkbc@gmail.com>
---
exec.c | 2 ++
hw/hw.h | 2 ++
target-alpha/machine.c | 12 +-----------
target-i386/machine.c | 2 +-
target-lm32/machine.c | 2 +-
target-m68k/machine.c | 10 ++++++++++
target-s390x/machine.c | 14 ++++++--------
target-sh4/machine.c | 10 ++++++++++
target-xtensa/machine.c | 14 ++++++--------
9 files changed, 39 insertions(+), 29 deletions(-)
diff --git a/exec.c b/exec.c
index 165cfe8..09f3f01 100644
--- a/exec.c
+++ b/exec.c
@@ -663,6 +663,8 @@ void cpu_exec_init(CPUState *env)
#if defined(CPU_SAVE_VERSION)
register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
cpu_save, cpu_load, env);
+#else
+ vmstate_register(NULL, cpu_index, &vmstate_cpu, env);
#endif
#endif
}
diff --git a/hw/hw.h b/hw/hw.h
index ed20f5a..0f0200a 100644
--- a/hw/hw.h
+++ b/hw/hw.h
@@ -359,6 +359,8 @@ extern const VMStateInfo vmstate_info_ptimer;
extern const VMStateInfo vmstate_info_buffer;
extern const VMStateInfo vmstate_info_unused_buffer;
+extern const VMStateDescription vmstate_cpu;
+
#define type_check_array(t1,t2,n) ((t1(*)[n])0 - (t2*)0)
#define type_check_pointer(t1,t2) ((t1**)0 - (t2*)0)
diff --git a/target-alpha/machine.c b/target-alpha/machine.c
index 76d70d9..8d32d7c 100644
--- a/target-alpha/machine.c
+++ b/target-alpha/machine.c
@@ -68,20 +68,10 @@ static VMStateField vmstate_cpu_fields[] = {
VMSTATE_END_OF_LIST()
};
-static const VMStateDescription vmstate_cpu = {
+const VMStateDescription vmstate_cpu = {
.name = "cpu",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = vmstate_cpu_fields,
};
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
- vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}
diff --git a/target-i386/machine.c b/target-i386/machine.c
index 25fa97d..54f5643 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -310,7 +310,7 @@ static const VMStateDescription vmstate_fpop_ip_dp = {
}
};
-static const VMStateDescription vmstate_cpu = {
+const VMStateDescription vmstate_cpu = {
.name = "cpu",
.version_id = CPU_SAVE_VERSION,
.minimum_version_id = 3,
diff --git a/target-lm32/machine.c b/target-lm32/machine.c
index 70ca52a..9014a9f 100644
--- a/target-lm32/machine.c
+++ b/target-lm32/machine.c
@@ -1,7 +1,7 @@
#include "hw/hw.h"
#include "hw/boards.h"
-static const VMStateDescription vmstate_cpu = {
+const VMStateDescription vmstate_cpu = {
.name = "cpu",
.version_id = CPU_SAVE_VERSION,
.minimum_version_id = 1,
diff --git a/target-m68k/machine.c b/target-m68k/machine.c
index e69de29..86b6fe9 100644
--- a/target-m68k/machine.c
+++ b/target-m68k/machine.c
@@ -0,0 +1,10 @@
+
+#include "hw/hw.h"
+
+/* To make this architecture migratable, we need to define cpu state
+ here. Other things need to be done elsewhere */
+
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
diff --git a/target-s390x/machine.c b/target-s390x/machine.c
index 3e79be6..5a7b219 100644
--- a/target-s390x/machine.c
+++ b/target-s390x/machine.c
@@ -18,13 +18,11 @@
*/
#include "hw/hw.h"
-#include "hw/boards.h"
-void cpu_save(QEMUFile *f, void *opaque)
-{
-}
+/* To make this architecture migratable, we need to define cpu state
+ here. Other things need to be done elsewhere */
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return 0;
-}
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
diff --git a/target-sh4/machine.c b/target-sh4/machine.c
index e69de29..86b6fe9 100644
--- a/target-sh4/machine.c
+++ b/target-sh4/machine.c
@@ -0,0 +1,10 @@
+
+#include "hw/hw.h"
+
+/* To make this architecture migratable, we need to define cpu state
+ here. Other things need to be done elsewhere */
+
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
diff --git a/target-xtensa/machine.c b/target-xtensa/machine.c
index ddeffb2..3f98330 100644
--- a/target-xtensa/machine.c
+++ b/target-xtensa/machine.c
@@ -26,13 +26,11 @@
*/
#include "hw/hw.h"
-#include "hw/boards.h"
-void cpu_save(QEMUFile *f, void *opaque)
-{
-}
+/* To make this architecture migratable, we need to define cpu state
+ here. Other things need to be done elsewhere */
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return 0;
-}
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 04/25] vmstate: unicore32 don't support cpu migration
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (2 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 03/25] vmstate: make all architectures export a way to migrate cpu's Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 05/25] vmstate: use new cpu style for x86 Juan Quintela
` (20 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-unicore32/cpu.h | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index b4e72cf..5632272 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -132,8 +132,6 @@ int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
int uc32_cpu_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int mmu_idx);
-#define CPU_SAVE_VERSION 2
-
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 05/25] vmstate: use new cpu style for x86
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (3 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 04/25] vmstate: unicore32 don't support cpu migration Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 06/25] vmstate: use new style for lm32 cpus Juan Quintela
` (19 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-i386/cpu.h | 2 --
target-i386/machine.c | 12 +-----------
2 files changed, 1 insertions(+), 13 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index a973f2e..ef6f9f4 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -949,8 +949,6 @@ uint64_t cpu_get_tsc(CPUX86State *env);
#define cpu_list_id x86_cpu_list
#define cpudef_setup x86_cpudef_setup
-#define CPU_SAVE_VERSION 13
-
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
diff --git a/target-i386/machine.c b/target-i386/machine.c
index 54f5643..0ecbfe9 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -312,7 +312,7 @@ static const VMStateDescription vmstate_fpop_ip_dp = {
const VMStateDescription vmstate_cpu = {
.name = "cpu",
- .version_id = CPU_SAVE_VERSION,
+ .version_id = 13,
.minimum_version_id = 3,
.minimum_version_id_old = 3,
.pre_save = cpu_pre_save,
@@ -426,13 +426,3 @@ const VMStateDescription vmstate_cpu = {
}
}
};
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
- vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 06/25] vmstate: use new style for lm32 cpus
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (4 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 05/25] vmstate: use new cpu style for x86 Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 19:02 ` Michael Walle
2011-10-25 14:00 ` [Qemu-devel] [PATCH 07/25] vmstate: make microblaze cpus not migrateable Juan Quintela
` (18 subsequent siblings)
24 siblings, 1 reply; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori, Michael Walle
Signed-off-by: Juan Quintela <quintela@redhat.com>
CC: Michael Walle <michael@walle.cc>
---
target-lm32/cpu.h | 2 --
target-lm32/machine.c | 12 +-----------
2 files changed, 1 insertions(+), 13 deletions(-)
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index 037ef52..bd37af8 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -202,8 +202,6 @@ void cpu_lm32_set_phys_msb_ignore(CPUState *env, int value);
#define cpu_gen_code cpu_lm32_gen_code
#define cpu_signal_handler cpu_lm32_signal_handler
-#define CPU_SAVE_VERSION 1
-
int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault
diff --git a/target-lm32/machine.c b/target-lm32/machine.c
index 9014a9f..e9ed250 100644
--- a/target-lm32/machine.c
+++ b/target-lm32/machine.c
@@ -3,7 +3,7 @@
const VMStateDescription vmstate_cpu = {
.name = "cpu",
- .version_id = CPU_SAVE_VERSION,
+ .version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
@@ -21,13 +21,3 @@ const VMStateDescription vmstate_cpu = {
VMSTATE_END_OF_LIST()
}
};
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
- vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 07/25] vmstate: make microblaze cpus not migrateable
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (5 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 06/25] vmstate: use new style for lm32 cpus Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 08/25] vmstate: port cris cpu to vmstate Juan Quintela
` (17 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Edgar E. Iglesias, aliguori
Signed-off-by: Juan Quintela <quintela@redhat.com>
CC: Edgar E. Iglesias <edgar.iglesias@gmail.com>
---
target-microblaze/cpu.h | 2 --
target-microblaze/machine.c | 15 +++++++--------
2 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 3530286..fc5c098 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -287,8 +287,6 @@ enum {
#define cpu_gen_code cpu_mb_gen_code
#define cpu_signal_handler cpu_mb_signal_handler
-#define CPU_SAVE_VERSION 1
-
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _nommu
#define MMU_MODE1_SUFFIX _kernel
diff --git a/target-microblaze/machine.c b/target-microblaze/machine.c
index 1be1c35..86b6fe9 100644
--- a/target-microblaze/machine.c
+++ b/target-microblaze/machine.c
@@ -1,11 +1,10 @@
+
#include "hw/hw.h"
-#include "hw/boards.h"
-void cpu_save(QEMUFile *f, void *opaque)
-{
-}
+/* To make this architecture migratable, we need to define cpu state
+ here. Other things need to be done elsewhere */
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return 0;
-}
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 08/25] vmstate: port cris cpu to vmstate
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (6 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 07/25] vmstate: make microblaze cpus not migrateable Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 09/25] vmstate: machine.c is only compiled for !CONFIG_USER_ONLY Juan Quintela
` (16 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Edgar E. Iglesias, aliguori
Have to define TLBSet struct.
Multidimensional arrays in C are a mess, just unroll them.
Signed-off-by: Juan Quintela <quintela@redhat.com>
CC: Edgar E. Iglesias <edgar.iglesias@gmail.com>
---
target-cris/cpu.h | 13 ++---
target-cris/machine.c | 138 +++++++++++++++++++------------------------------
2 files changed, 60 insertions(+), 91 deletions(-)
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 8ae0ce3..2cec75c 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -99,6 +99,11 @@
#define NB_MMU_MODES 2
+typedef struct {
+ uint32_t hi;
+ uint32_t lo;
+} TLBSet;
+
typedef struct CPUCRISState {
uint32_t regs[16];
/* P0 - P15 are referred to as special registers in the docs. */
@@ -152,11 +157,7 @@ typedef struct CPUCRISState {
*
* One for I and another for D.
*/
- struct
- {
- uint32_t hi;
- uint32_t lo;
- } tlbsets[2][4][16];
+ TLBSet tlbsets[2][4][16];
CPU_COMMON
@@ -214,8 +215,6 @@ enum {
#define cpu_gen_code cpu_cris_gen_code
#define cpu_signal_handler cpu_cris_signal_handler
-#define CPU_SAVE_VERSION 1
-
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
diff --git a/target-cris/machine.c b/target-cris/machine.c
index 8f9c0dd..79494a8 100644
--- a/target-cris/machine.c
+++ b/target-cris/machine.c
@@ -1,90 +1,60 @@
#include "hw/hw.h"
#include "hw/boards.h"
-void cpu_save(QEMUFile *f, void *opaque)
-{
- CPUCRISState *env = opaque;
- int i;
- int s;
- int mmu;
-
- for (i = 0; i < 16; i++)
- qemu_put_be32(f, env->regs[i]);
- for (i = 0; i < 16; i++)
- qemu_put_be32(f, env->pregs[i]);
-
- qemu_put_be32(f, env->pc);
- qemu_put_be32(f, env->ksp);
-
- qemu_put_be32(f, env->dslot);
- qemu_put_be32(f, env->btaken);
- qemu_put_be32(f, env->btarget);
-
- qemu_put_be32(f, env->cc_op);
- qemu_put_be32(f, env->cc_mask);
- qemu_put_be32(f, env->cc_dest);
- qemu_put_be32(f, env->cc_src);
- qemu_put_be32(f, env->cc_result);
- qemu_put_be32(f, env->cc_size);
- qemu_put_be32(f, env->cc_x);
-
- for (s = 0; s < 4; s++) {
- for (i = 0; i < 16; i++)
- qemu_put_be32(f, env->sregs[s][i]);
- }
-
- qemu_put_be32(f, env->mmu_rand_lfsr);
- for (mmu = 0; mmu < 2; mmu++) {
- for (s = 0; s < 4; s++) {
- for (i = 0; i < 16; i++) {
- qemu_put_be32(f, env->tlbsets[mmu][s][i].lo);
- qemu_put_be32(f, env->tlbsets[mmu][s][i].hi);
- }
- }
+static const VMStateDescription vmstate_tlbset = {
+ .name = "cpu/tlbset",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(lo, TLBSet),
+ VMSTATE_UINT32(hi, TLBSet),
+ VMSTATE_END_OF_LIST()
}
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- CPUCRISState *env = opaque;
- int i;
- int s;
- int mmu;
-
- for (i = 0; i < 16; i++)
- env->regs[i] = qemu_get_be32(f);
- for (i = 0; i < 16; i++)
- env->pregs[i] = qemu_get_be32(f);
-
- env->pc = qemu_get_be32(f);
- env->ksp = qemu_get_be32(f);
-
- env->dslot = qemu_get_be32(f);
- env->btaken = qemu_get_be32(f);
- env->btarget = qemu_get_be32(f);
-
- env->cc_op = qemu_get_be32(f);
- env->cc_mask = qemu_get_be32(f);
- env->cc_dest = qemu_get_be32(f);
- env->cc_src = qemu_get_be32(f);
- env->cc_result = qemu_get_be32(f);
- env->cc_size = qemu_get_be32(f);
- env->cc_x = qemu_get_be32(f);
-
- for (s = 0; s < 4; s++) {
- for (i = 0; i < 16; i++)
- env->sregs[s][i] = qemu_get_be32(f);
- }
-
- env->mmu_rand_lfsr = qemu_get_be32(f);
- for (mmu = 0; mmu < 2; mmu++) {
- for (s = 0; s < 4; s++) {
- for (i = 0; i < 16; i++) {
- env->tlbsets[mmu][s][i].lo = qemu_get_be32(f);
- env->tlbsets[mmu][s][i].hi = qemu_get_be32(f);
- }
- }
+};
+
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, CPUState, 16),
+ VMSTATE_UINT32_ARRAY(pregs, CPUState, 16),
+ VMSTATE_UINT32(pc, CPUState),
+ VMSTATE_UINT32(ksp, CPUState),
+ VMSTATE_INT32(dslot, CPUState),
+ VMSTATE_INT32(btaken, CPUState),
+ VMSTATE_UINT32(btarget, CPUState),
+ VMSTATE_UINT32(cc_op, CPUState),
+ VMSTATE_UINT32(cc_mask, CPUState),
+ VMSTATE_UINT32(cc_dest, CPUState),
+ VMSTATE_UINT32(cc_src, CPUState),
+ VMSTATE_UINT32(cc_result, CPUState),
+ VMSTATE_INT32(cc_size, CPUState),
+ VMSTATE_INT32(cc_x, CPUState),
+ VMSTATE_UINT32_ARRAY(sregs[0], CPUState, 16),
+ VMSTATE_UINT32_ARRAY(sregs[1], CPUState, 16),
+ VMSTATE_UINT32_ARRAY(sregs[2], CPUState, 16),
+ VMSTATE_UINT32_ARRAY(sregs[3], CPUState, 16),
+ VMSTATE_UINT32(mmu_rand_lfsr, CPUState),
+ VMSTATE_STRUCT_ARRAY(tlbsets[0][0], CPUState, 16, 0,
+ vmstate_tlbset, TLBSet),
+ VMSTATE_STRUCT_ARRAY(tlbsets[0][1], CPUState, 16, 0,
+ vmstate_tlbset, TLBSet),
+ VMSTATE_STRUCT_ARRAY(tlbsets[0][2], CPUState, 16, 0,
+ vmstate_tlbset, TLBSet),
+ VMSTATE_STRUCT_ARRAY(tlbsets[0][3], CPUState, 16, 0,
+ vmstate_tlbset, TLBSet),
+ VMSTATE_STRUCT_ARRAY(tlbsets[1][0], CPUState, 16, 0,
+ vmstate_tlbset, TLBSet),
+ VMSTATE_STRUCT_ARRAY(tlbsets[1][1], CPUState, 16, 0,
+ vmstate_tlbset, TLBSet),
+ VMSTATE_STRUCT_ARRAY(tlbsets[1][2], CPUState, 16, 0,
+ vmstate_tlbset, TLBSet),
+ VMSTATE_STRUCT_ARRAY(tlbsets[1][3], CPUState, 16, 0,
+ vmstate_tlbset, TLBSet),
+ VMSTATE_END_OF_LIST()
}
+};
- return 0;
-}
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 09/25] vmstate: machine.c is only compiled for !CONFIG_USER_ONLY
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (7 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 08/25] vmstate: port cris cpu to vmstate Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 10/25] vmstate: introduce float32 arrays Juan Quintela
` (15 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori, Alexander Graf
Signed-off-by: Juan Quintela <quintela@redhat.com>
CC: Alexander Graf <agraf@suse.de>
---
target-ppc/machine.c | 8 --------
1 files changed, 0 insertions(+), 8 deletions(-)
diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index 1c40d43..226b4a5 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -32,7 +32,6 @@ void cpu_save(QEMUFile *f, void *opaque)
}
qemu_put_be32s(f, &env->fpscr);
qemu_put_sbe32s(f, &env->access_type);
-#if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
qemu_put_betls(f, &env->asr);
qemu_put_sbe32s(f, &env->slb_nr);
@@ -62,7 +61,6 @@ void cpu_save(QEMUFile *f, void *opaque)
}
for (i = 0; i < 4; i++)
qemu_put_betls(f, &env->pb[i]);
-#endif
for (i = 0; i < 1024; i++)
qemu_put_betls(f, &env->spr[i]);
qemu_put_be32s(f, &env->vscr);
@@ -72,7 +70,6 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_be32s(f, &env->flags);
qemu_put_sbe32s(f, &env->error_code);
qemu_put_be32s(f, &env->pending_interrupts);
-#if !defined(CONFIG_USER_ONLY)
qemu_put_be32s(f, &env->irq_input_state);
for (i = 0; i < POWERPC_EXCP_NB; i++)
qemu_put_betls(f, &env->excp_vectors[i]);
@@ -81,7 +78,6 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_betls(f, &env->ivor_mask);
qemu_put_betls(f, &env->ivpr_mask);
qemu_put_betls(f, &env->hreset_vector);
-#endif
qemu_put_betls(f, &env->nip);
qemu_put_betls(f, &env->hflags);
qemu_put_betls(f, &env->hflags_nmsr);
@@ -120,7 +116,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
}
qemu_get_be32s(f, &env->fpscr);
qemu_get_sbe32s(f, &env->access_type);
-#if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
qemu_get_betls(f, &env->asr);
qemu_get_sbe32s(f, &env->slb_nr);
@@ -150,7 +145,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
}
for (i = 0; i < 4; i++)
qemu_get_betls(f, &env->pb[i]);
-#endif
for (i = 0; i < 1024; i++)
qemu_get_betls(f, &env->spr[i]);
ppc_store_sdr1(env, sdr1);
@@ -161,7 +155,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_be32s(f, &env->flags);
qemu_get_sbe32s(f, &env->error_code);
qemu_get_be32s(f, &env->pending_interrupts);
-#if !defined(CONFIG_USER_ONLY)
qemu_get_be32s(f, &env->irq_input_state);
for (i = 0; i < POWERPC_EXCP_NB; i++)
qemu_get_betls(f, &env->excp_vectors[i]);
@@ -170,7 +163,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_betls(f, &env->ivor_mask);
qemu_get_betls(f, &env->ivpr_mask);
qemu_get_betls(f, &env->hreset_vector);
-#endif
qemu_get_betls(f, &env->nip);
qemu_get_betls(f, &env->hflags);
qemu_get_betls(f, &env->hflags_nmsr);
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 10/25] vmstate: introduce float32 arrays
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (8 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 09/25] vmstate: machine.c is only compiled for !CONFIG_USER_ONLY Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 11/25] vmstate: introduce float64 arrays Juan Quintela
` (14 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/hw.h | 5 +++++
savevm.c | 30 ++++++++++++++++++++++++++++++
2 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/hw/hw.h b/hw/hw.h
index 0f0200a..014cdc1 100644
--- a/hw/hw.h
+++ b/hw/hw.h
@@ -354,6 +354,8 @@ extern const VMStateInfo vmstate_info_uint16;
extern const VMStateInfo vmstate_info_uint32;
extern const VMStateInfo vmstate_info_uint64;
+extern const VMStateInfo vmstate_info_float32;
+
extern const VMStateInfo vmstate_info_timer;
extern const VMStateInfo vmstate_info_ptimer;
extern const VMStateInfo vmstate_info_buffer;
@@ -875,6 +877,9 @@ extern const VMStateDescription vmstate_hid_ptr_device;
#define VMSTATE_INT64_ARRAY(_f, _s, _n) \
VMSTATE_INT64_ARRAY_V(_f, _s, _n, 0)
+#define VMSTATE_FLOAT32_ARRAY(_f, _s, _n) \
+ VMSTATE_ARRAY(_f, _s, _n, 0, vmstate_info_float32, float32)
+
#define VMSTATE_BUFFER_V(_f, _s, _v) \
VMSTATE_STATIC_BUFFER(_f, _s, _v, NULL, 0, sizeof(typeof_field(_s, _f)))
diff --git a/savevm.c b/savevm.c
index 557eba4..cd0178c 100644
--- a/savevm.c
+++ b/savevm.c
@@ -1027,6 +1027,36 @@ const VMStateInfo vmstate_info_uint16_equal = {
.put = put_uint16,
};
+/* 32 bit float */
+
+typedef union {
+ float32 f;
+ uint32_t i;
+} VMStateFloat32;
+
+static int get_float32(QEMUFile *f, void *pv, size_t size)
+{
+ float32 *v = pv;
+ VMStateFloat32 u;
+ qemu_get_be32s(f, &u.i);
+ *v = u.f;
+ return 0;
+}
+
+static void put_float32(QEMUFile *f, void *pv, size_t size)
+{
+ float32 *v = pv;
+ VMStateFloat32 u;
+ u.f = *v;
+ qemu_put_be32s(f, &u.i);
+}
+
+const VMStateInfo vmstate_info_float32 = {
+ .name = "float32",
+ .get = get_float32,
+ .put = put_float32,
+};
+
/* timers */
static int get_timer(QEMUFile *f, void *pv, size_t size)
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 11/25] vmstate: introduce float64 arrays
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (9 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 10/25] vmstate: introduce float32 arrays Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 12/25] vmstate: Introduce VMSTATE_STRUCT_VARRAY_INT32_TEST Juan Quintela
` (13 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/hw.h | 4 ++++
savevm.c | 30 ++++++++++++++++++++++++++++++
2 files changed, 34 insertions(+), 0 deletions(-)
diff --git a/hw/hw.h b/hw/hw.h
index 014cdc1..3044cec 100644
--- a/hw/hw.h
+++ b/hw/hw.h
@@ -355,6 +355,7 @@ extern const VMStateInfo vmstate_info_uint32;
extern const VMStateInfo vmstate_info_uint64;
extern const VMStateInfo vmstate_info_float32;
+extern const VMStateInfo vmstate_info_float64;
extern const VMStateInfo vmstate_info_timer;
extern const VMStateInfo vmstate_info_ptimer;
@@ -880,6 +881,9 @@ extern const VMStateDescription vmstate_hid_ptr_device;
#define VMSTATE_FLOAT32_ARRAY(_f, _s, _n) \
VMSTATE_ARRAY(_f, _s, _n, 0, vmstate_info_float32, float32)
+#define VMSTATE_FLOAT64_ARRAY(_f, _s, _n) \
+ VMSTATE_ARRAY(_f, _s, _n, 0, vmstate_info_float64, float64)
+
#define VMSTATE_BUFFER_V(_f, _s, _v) \
VMSTATE_STATIC_BUFFER(_f, _s, _v, NULL, 0, sizeof(typeof_field(_s, _f)))
diff --git a/savevm.c b/savevm.c
index cd0178c..2e191ad 100644
--- a/savevm.c
+++ b/savevm.c
@@ -1057,6 +1057,36 @@ const VMStateInfo vmstate_info_float32 = {
.put = put_float32,
};
+/* 64 bit float */
+
+typedef union {
+ float64 d;
+ uint64_t l;
+} VMStateFloat64;
+
+static int get_float64(QEMUFile *f, void *pv, size_t size)
+{
+ float64 *v = pv;
+ VMStateFloat64 u;
+ qemu_get_be64s(f, &u.l);
+ *v = u.d;
+ return 0;
+}
+
+static void put_float64(QEMUFile *f, void *pv, size_t size)
+{
+ float64 *v = pv;
+ VMStateFloat64 u;
+ u.d = *v;
+ qemu_put_be64s(f, &u.l);
+}
+
+const VMStateInfo vmstate_info_float64 = {
+ .name = "float64",
+ .get = get_float64,
+ .put = put_float64,
+};
+
/* timers */
static int get_timer(QEMUFile *f, void *pv, size_t size)
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 12/25] vmstate: Introduce VMSTATE_STRUCT_VARRAY_INT32_TEST
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (10 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 11/25] vmstate: introduce float64 arrays Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 13/25] vmstate: port ppc cpu Juan Quintela
` (12 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
We have an array of structs whose size is an int32 in the same struct that
depends on a test value to know if it is there or not.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/hw.h | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/hw/hw.h b/hw/hw.h
index 3044cec..798732f 100644
--- a/hw/hw.h
+++ b/hw/hw.h
@@ -533,6 +533,16 @@ extern const VMStateDescription vmstate_cpu;
.offset = offsetof(_state, _field), \
}
+#define VMSTATE_STRUCT_VARRAY_INT32_TEST(_field, _state, _field_num, _test, _vmsd, _type) { \
+ .name = (stringify(_field)), \
+ .num_offset = vmstate_offset_value(_state, _field_num, int32_t), \
+ .vmsd = &(_vmsd), \
+ .field_exists = (_test), \
+ .size = sizeof(_type), \
+ .flags = VMS_STRUCT|VMS_VARRAY_INT32, \
+ .offset = offsetof(_state, _field), \
+}
+
#define VMSTATE_STRUCT_VARRAY_POINTER_INT32(_field, _state, _field_num, _vmsd, _type) { \
.name = (stringify(_field)), \
.version_id = 0, \
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 13/25] vmstate: port ppc cpu
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (11 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 12/25] vmstate: Introduce VMSTATE_STRUCT_VARRAY_INT32_TEST Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-30 16:36 ` Alexander Graf
2011-10-25 14:00 ` [Qemu-devel] [PATCH 14/25] vmstate: introduce VMSTATE_VARRAY_MULTIPLY Juan Quintela
` (11 subsequent siblings)
24 siblings, 1 reply; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori, Alexander Graf
Added sdr1_vmstate because storing the value requires calling ppc_store_sdr1().
The position when the function is called also changes (I think it is save).
Signed-off-by: Juan Quintela <quintela@redhat.com>
CC: Alexander Graf <agraf@suse.de>
---
target-ppc/cpu.h | 4 +-
target-ppc/machine.c | 245 ++++++++++++++++++--------------------------------
2 files changed, 89 insertions(+), 160 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 3f77e30..e7f6625 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1029,6 +1029,8 @@ struct CPUPPCState {
*/
uint8_t fit_period[4];
uint8_t wdt_period[4];
+
+ target_ulong sdr1_vmstate;
};
#define SET_FIT_PERIOD(a_, b_, c_, d_) \
@@ -1183,8 +1185,6 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
#define cpu_signal_handler cpu_ppc_signal_handler
#define cpu_list ppc_cpu_list
-#define CPU_SAVE_VERSION 4
-
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _user
#define MMU_MODE1_SUFFIX _kernel
diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index 226b4a5..8d3cd86 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -2,172 +2,101 @@
#include "hw/boards.h"
#include "kvm.h"
-void cpu_save(QEMUFile *f, void *opaque)
+static const VMStateDescription vmstate_tlb = {
+ .name = "tlb",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
+ VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
+ VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static bool is_tlb6(void *opaque, int version_id)
{
- CPUState *env = (CPUState *)opaque;
- unsigned int i, j;
+ CPUState *env = opaque;
- for (i = 0; i < 32; i++)
- qemu_put_betls(f, &env->gpr[i]);
-#if !defined(TARGET_PPC64)
- for (i = 0; i < 32; i++)
- qemu_put_betls(f, &env->gprh[i]);
-#endif
- qemu_put_betls(f, &env->lr);
- qemu_put_betls(f, &env->ctr);
- for (i = 0; i < 8; i++)
- qemu_put_be32s(f, &env->crf[i]);
- qemu_put_betls(f, &env->xer);
- qemu_put_betls(f, &env->reserve_addr);
- qemu_put_betls(f, &env->msr);
- for (i = 0; i < 4; i++)
- qemu_put_betls(f, &env->tgpr[i]);
- for (i = 0; i < 32; i++) {
- union {
- float64 d;
- uint64_t l;
- } u;
- u.d = env->fpr[i];
- qemu_put_be64(f, u.l);
- }
- qemu_put_be32s(f, &env->fpscr);
- qemu_put_sbe32s(f, &env->access_type);
-#if defined(TARGET_PPC64)
- qemu_put_betls(f, &env->asr);
- qemu_put_sbe32s(f, &env->slb_nr);
-#endif
- qemu_put_betls(f, &env->spr[SPR_SDR1]);
- for (i = 0; i < 32; i++)
- qemu_put_betls(f, &env->sr[i]);
- for (i = 0; i < 2; i++)
- for (j = 0; j < 8; j++)
- qemu_put_betls(f, &env->DBAT[i][j]);
- for (i = 0; i < 2; i++)
- for (j = 0; j < 8; j++)
- qemu_put_betls(f, &env->IBAT[i][j]);
- qemu_put_sbe32s(f, &env->nb_tlb);
- qemu_put_sbe32s(f, &env->tlb_per_way);
- qemu_put_sbe32s(f, &env->nb_ways);
- qemu_put_sbe32s(f, &env->last_way);
- qemu_put_sbe32s(f, &env->id_tlbs);
- qemu_put_sbe32s(f, &env->nb_pids);
- if (env->tlb.tlb6) {
- // XXX assumes 6xx
- for (i = 0; i < env->nb_tlb; i++) {
- qemu_put_betls(f, &env->tlb.tlb6[i].pte0);
- qemu_put_betls(f, &env->tlb.tlb6[i].pte1);
- qemu_put_betls(f, &env->tlb.tlb6[i].EPN);
- }
- }
- for (i = 0; i < 4; i++)
- qemu_put_betls(f, &env->pb[i]);
- for (i = 0; i < 1024; i++)
- qemu_put_betls(f, &env->spr[i]);
- qemu_put_be32s(f, &env->vscr);
- qemu_put_be64s(f, &env->spe_acc);
- qemu_put_be32s(f, &env->spe_fscr);
- qemu_put_betls(f, &env->msr_mask);
- qemu_put_be32s(f, &env->flags);
- qemu_put_sbe32s(f, &env->error_code);
- qemu_put_be32s(f, &env->pending_interrupts);
- qemu_put_be32s(f, &env->irq_input_state);
- for (i = 0; i < POWERPC_EXCP_NB; i++)
- qemu_put_betls(f, &env->excp_vectors[i]);
- qemu_put_betls(f, &env->excp_prefix);
- qemu_put_betls(f, &env->hreset_excp_prefix);
- qemu_put_betls(f, &env->ivor_mask);
- qemu_put_betls(f, &env->ivpr_mask);
- qemu_put_betls(f, &env->hreset_vector);
- qemu_put_betls(f, &env->nip);
- qemu_put_betls(f, &env->hflags);
- qemu_put_betls(f, &env->hflags_nmsr);
- qemu_put_sbe32s(f, &env->mmu_idx);
- qemu_put_sbe32s(f, &env->power_mode);
+ return (env->tlb.tlb6 != NULL);
}
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
+static void cpu_pre_save(void *opaque)
{
- CPUState *env = (CPUState *)opaque;
- unsigned int i, j;
- target_ulong sdr1;
+ CPUState *env = opaque;
+ env->sdr1_vmstate = env->spr[SPR_SDR1];
+}
- for (i = 0; i < 32; i++)
- qemu_get_betls(f, &env->gpr[i]);
+static int cpu_post_load(void *opaque, int version_id)
+{
+ CPUState *env = opaque;
+ ppc_store_sdr1(env, env->sdr1_vmstate);
+ return 0;
+}
+
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .version_id = 4,
+ .minimum_version_id = 4,
+ .minimum_version_id_old = 4,
+ .pre_save = cpu_pre_save,
+ .post_load = cpu_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL_ARRAY(gpr, CPUState, 32),
#if !defined(TARGET_PPC64)
- for (i = 0; i < 32; i++)
- qemu_get_betls(f, &env->gprh[i]);
+ VMSTATE_UINTTL_ARRAY(gprh, CPUState, 32),
#endif
- qemu_get_betls(f, &env->lr);
- qemu_get_betls(f, &env->ctr);
- for (i = 0; i < 8; i++)
- qemu_get_be32s(f, &env->crf[i]);
- qemu_get_betls(f, &env->xer);
- qemu_get_betls(f, &env->reserve_addr);
- qemu_get_betls(f, &env->msr);
- for (i = 0; i < 4; i++)
- qemu_get_betls(f, &env->tgpr[i]);
- for (i = 0; i < 32; i++) {
- union {
- float64 d;
- uint64_t l;
- } u;
- u.l = qemu_get_be64(f);
- env->fpr[i] = u.d;
- }
- qemu_get_be32s(f, &env->fpscr);
- qemu_get_sbe32s(f, &env->access_type);
+ VMSTATE_UINTTL(lr, CPUState),
+ VMSTATE_UINTTL(ctr, CPUState),
+ VMSTATE_UINT32_ARRAY(crf, CPUState, 8),
+ VMSTATE_UINTTL(xer, CPUState),
+ VMSTATE_UINTTL(reserve_addr, CPUState),
+ VMSTATE_UINTTL(msr, CPUState),
+ VMSTATE_UINTTL_ARRAY(tgpr, CPUState, 4),
+ VMSTATE_FLOAT64_ARRAY(fpr, CPUState, 32),
+ VMSTATE_UINT32(fpscr, CPUState),
+ VMSTATE_INT32(access_type, CPUState),
#if defined(TARGET_PPC64)
- qemu_get_betls(f, &env->asr);
- qemu_get_sbe32s(f, &env->slb_nr);
+ VMSTATE_UINTTL(asr, CPUState),
+ VMSTATE_INT32(slb_nr, CPUState),
#endif
- qemu_get_betls(f, &sdr1);
- for (i = 0; i < 32; i++)
- qemu_get_betls(f, &env->sr[i]);
- for (i = 0; i < 2; i++)
- for (j = 0; j < 8; j++)
- qemu_get_betls(f, &env->DBAT[i][j]);
- for (i = 0; i < 2; i++)
- for (j = 0; j < 8; j++)
- qemu_get_betls(f, &env->IBAT[i][j]);
- qemu_get_sbe32s(f, &env->nb_tlb);
- qemu_get_sbe32s(f, &env->tlb_per_way);
- qemu_get_sbe32s(f, &env->nb_ways);
- qemu_get_sbe32s(f, &env->last_way);
- qemu_get_sbe32s(f, &env->id_tlbs);
- qemu_get_sbe32s(f, &env->nb_pids);
- if (env->tlb.tlb6) {
- // XXX assumes 6xx
- for (i = 0; i < env->nb_tlb; i++) {
- qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
- qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
- qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
- }
- }
- for (i = 0; i < 4; i++)
- qemu_get_betls(f, &env->pb[i]);
- for (i = 0; i < 1024; i++)
- qemu_get_betls(f, &env->spr[i]);
- ppc_store_sdr1(env, sdr1);
- qemu_get_be32s(f, &env->vscr);
- qemu_get_be64s(f, &env->spe_acc);
- qemu_get_be32s(f, &env->spe_fscr);
- qemu_get_betls(f, &env->msr_mask);
- qemu_get_be32s(f, &env->flags);
- qemu_get_sbe32s(f, &env->error_code);
- qemu_get_be32s(f, &env->pending_interrupts);
- qemu_get_be32s(f, &env->irq_input_state);
- for (i = 0; i < POWERPC_EXCP_NB; i++)
- qemu_get_betls(f, &env->excp_vectors[i]);
- qemu_get_betls(f, &env->excp_prefix);
- qemu_get_betls(f, &env->hreset_excp_prefix);
- qemu_get_betls(f, &env->ivor_mask);
- qemu_get_betls(f, &env->ivpr_mask);
- qemu_get_betls(f, &env->hreset_vector);
- qemu_get_betls(f, &env->nip);
- qemu_get_betls(f, &env->hflags);
- qemu_get_betls(f, &env->hflags_nmsr);
- qemu_get_sbe32s(f, &env->mmu_idx);
- qemu_get_sbe32s(f, &env->power_mode);
+ VMSTATE_UINTTL(spr[SPR_SDR1], CPUState),
+ VMSTATE_UINTTL_ARRAY(sr, CPUState, 32),
+ VMSTATE_UINTTL_ARRAY(DBAT[0], CPUState, 8),
+ VMSTATE_UINTTL_ARRAY(DBAT[1], CPUState, 8),
+ VMSTATE_UINTTL_ARRAY(IBAT[0], CPUState, 8),
+ VMSTATE_UINTTL_ARRAY(IBAT[1], CPUState, 8),
+ VMSTATE_INT32(nb_tlb, CPUState),
+ VMSTATE_INT32(tlb_per_way, CPUState),
+ VMSTATE_INT32(nb_ways, CPUState),
+ VMSTATE_INT32(last_way, CPUState),
+ VMSTATE_INT32(id_tlbs, CPUState),
+ VMSTATE_INT32(nb_pids, CPUState),
+ VMSTATE_STRUCT_VARRAY_INT32_TEST(tlb.tlb6, CPUState, nb_tlb,
+ is_tlb6, vmstate_tlb, ppc6xx_tlb_t),
+ VMSTATE_UINTTL_ARRAY(pb, CPUState, 4),
+ VMSTATE_UINTTL_ARRAY(spr, CPUState, 1024),
+ VMSTATE_UINT32(vscr, CPUState),
+ VMSTATE_UINT64(spe_acc, CPUState),
+ VMSTATE_UINT32(spe_fscr, CPUState),
+ VMSTATE_UINTTL(msr_mask, CPUState),
+ VMSTATE_UINT32(flags, CPUState),
+ VMSTATE_INT32(error_code, CPUState),
+ VMSTATE_UINT32(pending_interrupts, CPUState),
+ VMSTATE_UINT32(irq_input_state, CPUState),
+ VMSTATE_UINTTL_ARRAY(excp_vectors, CPUState, POWERPC_EXCP_NB),
+ VMSTATE_UINTTL(excp_prefix, CPUState),
+ VMSTATE_UINTTL(hreset_excp_prefix, CPUState),
+ VMSTATE_UINTTL(ivor_mask, CPUState),
+ VMSTATE_UINTTL(ivpr_mask, CPUState),
+ VMSTATE_UINTTL(hreset_vector, CPUState),
+ VMSTATE_UINTTL(nip, CPUState),
+ VMSTATE_UINTTL(hflags, CPUState),
+ VMSTATE_UINTTL(hflags_nmsr, CPUState),
+ VMSTATE_INT32(mmu_idx, CPUState),
+ VMSTATE_INT32(power_mode, CPUState),
+ VMSTATE_END_OF_LIST()
+ },
+};
- return 0;
-}
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 14/25] vmstate: introduce VMSTATE_VARRAY_MULTIPLY
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (12 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 13/25] vmstate: port ppc cpu Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 15/25] vmstate: define vmstate_info_uinttls Juan Quintela
` (10 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
Thiss allows to sent a partial array where the size is another
structure field multiplied by a constant.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/hw.h | 11 +++++++++++
savevm.c | 6 ++++++
2 files changed, 17 insertions(+), 0 deletions(-)
diff --git a/hw/hw.h b/hw/hw.h
index 798732f..727d563 100644
--- a/hw/hw.h
+++ b/hw/hw.h
@@ -300,6 +300,7 @@ enum VMStateFlags {
VMS_MULTIPLY = 0x200, /* multiply "size" field by field_size */
VMS_VARRAY_UINT8 = 0x400, /* Array with size in uint8_t field*/
VMS_VARRAY_UINT32 = 0x800, /* Array with size in uint32_t field*/
+ VMS_MULTIPLY_ELEMENTS= 0x1000, /* multiply "size" field by field_size */
};
typedef struct {
@@ -424,6 +425,16 @@ extern const VMStateDescription vmstate_cpu;
.offset = vmstate_offset_array(_state, _field, _type, _num), \
}
+#define VMSTATE_VARRAY_MULTIPLY(_field, _state, _field_num, _multiply, _info, _type) { \
+ .name = (stringify(_field)), \
+ .num_offset = vmstate_offset_value(_state, _field_num, uint32_t),\
+ .num = (_multiply), \
+ .info = &(_info), \
+ .size = sizeof(_type), \
+ .flags = VMS_VARRAY_UINT32|VMS_MULTIPLY_ELEMENTS, \
+ .offset = offsetof(_state, _field), \
+}
+
#define VMSTATE_ARRAY_TEST(_field, _state, _num, _test, _info, _type) {\
.name = (stringify(_field)), \
.field_exists = (_test), \
diff --git a/savevm.c b/savevm.c
index 2e191ad..8ef46a1 100644
--- a/savevm.c
+++ b/savevm.c
@@ -1460,6 +1460,9 @@ int vmstate_load_state(QEMUFile *f, const VMStateDescription *vmsd,
} else if (field->flags & VMS_VARRAY_UINT8) {
n_elems = *(uint8_t *)(opaque+field->num_offset);
}
+ if (field->flags & VMS_MULTIPLY_ELEMENTS) {
+ n_elems *= field->num;
+ }
if (field->flags & VMS_POINTER) {
base_addr = *(void **)base_addr + field->start;
}
@@ -1524,6 +1527,9 @@ void vmstate_save_state(QEMUFile *f, const VMStateDescription *vmsd,
} else if (field->flags & VMS_VARRAY_UINT8) {
n_elems = *(uint8_t *)(opaque+field->num_offset);
}
+ if (field->flags & VMS_MULTIPLY_ELEMENTS) {
+ n_elems *= field->num;
+ }
if (field->flags & VMS_POINTER) {
base_addr = *(void **)base_addr + field->start;
}
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 15/25] vmstate: define vmstate_info_uinttls
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (13 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 14/25] vmstate: introduce VMSTATE_VARRAY_MULTIPLY Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 16/25] vmstate: port sparc cpu Juan Quintela
` (9 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
We are going to define arrays of this type, so we need the integer type.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/hw.h | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/hw.h b/hw/hw.h
index 727d563..306127a 100644
--- a/hw/hw.h
+++ b/hw/hw.h
@@ -947,11 +947,13 @@ extern const VMStateDescription vmstate_hid_ptr_device;
VMSTATE_UINT64_V(_f, _s, _v)
#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v)
+#define vmstate_info_uinttls vmstate_info_uint64
#else
#define VMSTATE_UINTTL_V(_f, _s, _v) \
VMSTATE_UINT32_V(_f, _s, _v)
#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v)
+#define vmstate_info_uinttls vmstate_info_uint32
#endif
#define VMSTATE_UINTTL(_f, _s) \
VMSTATE_UINTTL_V(_f, _s, 0)
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 16/25] vmstate: port sparc cpu
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (14 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 15/25] vmstate: define vmstate_info_uinttls Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 17/25] vmstate: make incompatible change for sparc Juan Quintela
` (8 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl, aliguori
Signed-off-by: Juan Quintela <quintela@redhat.com>
CC: Blue Swirl <blauwirbel@gmail.com>
---
hw/sun4u.c | 20 --
target-sparc/cpu.h | 8 +-
target-sparc/machine.c | 482 ++++++++++++++++++++++++++++--------------------
3 files changed, 282 insertions(+), 228 deletions(-)
diff --git a/hw/sun4u.c b/hw/sun4u.c
index eaaefe3..b0f671d 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -324,26 +324,6 @@ typedef struct ResetData {
uint64_t prom_addr;
} ResetData;
-void cpu_put_timer(QEMUFile *f, CPUTimer *s)
-{
- qemu_put_be32s(f, &s->frequency);
- qemu_put_be32s(f, &s->disabled);
- qemu_put_be64s(f, &s->disabled_mask);
- qemu_put_sbe64s(f, &s->clock_offset);
-
- qemu_put_timer(f, s->qtimer);
-}
-
-void cpu_get_timer(QEMUFile *f, CPUTimer *s)
-{
- qemu_get_be32s(f, &s->frequency);
- qemu_get_be32s(f, &s->disabled);
- qemu_get_be64s(f, &s->disabled_mask);
- qemu_get_sbe64s(f, &s->clock_offset);
-
- qemu_get_timer(f, s->qtimer);
-}
-
static CPUTimer* cpu_timer_create(const char* name, CPUState *env,
QEMUBHFunc *cb, uint32_t frequency,
uint64_t disabled_mask)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 6bf9275..ae554c9 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -352,10 +352,6 @@ struct CPUTimer
typedef struct CPUTimer CPUTimer;
-struct QEMUFile;
-void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
-void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
-
typedef struct CPUSPARCState {
target_ulong gregs[8]; /* general registers */
target_ulong *regwptr; /* pointer to current register window */
@@ -482,6 +478,8 @@ typedef struct CPUSPARCState {
/* Leon3 cache control */
uint32_t cache_control;
+
+ uint32_t psr_vmstate;
} CPUSPARCState;
#ifndef NO_CPU_IO_DEFS
@@ -569,8 +567,6 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
#define cpu_signal_handler cpu_sparc_signal_handler
#define cpu_list sparc_cpu_list
-#define CPU_SAVE_VERSION 7
-
/* MMU modes definitions */
#if defined (TARGET_SPARC64)
#define MMU_USER_IDX 0
diff --git a/target-sparc/machine.c b/target-sparc/machine.c
index 56ae041..2186756 100644
--- a/target-sparc/machine.c
+++ b/target-sparc/machine.c
@@ -4,222 +4,300 @@
#include "cpu.h"
-void cpu_save(QEMUFile *f, void *opaque)
-{
- CPUState *env = opaque;
- int i;
- uint32_t tmp;
-
- // if env->cwp == env->nwindows - 1, this will set the ins of the last
- // window as the outs of the first window
- cpu_set_cwp(env, env->cwp);
+static const VMStateDescription vmstate_cpu_timer = {
+ .name = "cpu_timer",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(frequency, CPUTimer),
+ VMSTATE_UINT32(disabled, CPUTimer),
+ VMSTATE_UINT64(disabled_mask, CPUTimer),
+ VMSTATE_INT64(clock_offset, CPUTimer),
+ VMSTATE_TIMER(qtimer, CPUTimer),
+ VMSTATE_END_OF_LIST()
+ }
+};
- for(i = 0; i < 8; i++)
- qemu_put_betls(f, &env->gregs[i]);
- qemu_put_be32s(f, &env->nwindows);
- for(i = 0; i < env->nwindows * 16; i++)
- qemu_put_betls(f, &env->regbase[i]);
+#define VMSTATE_CPU_TIMER(_f, _s) \
+ VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_timer, CPUTimer *)
- /* FPU */
- for(i = 0; i < TARGET_FPREGS; i++) {
- union {
- float32 f;
- uint32_t i;
- } u;
- u.f = env->fpr[i];
- qemu_put_be32(f, u.i);
+#if defined(TARGET_SPARC64)
+static const VMStateDescription vmstate_trap_state = {
+ .name = "trap_state",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(tpc, trap_state),
+ VMSTATE_UINT64(tnpc, trap_state),
+ VMSTATE_UINT64(tstate, trap_state),
+ VMSTATE_UINT32(tt, trap_state),
+ VMSTATE_END_OF_LIST()
}
+};
- qemu_put_betls(f, &env->pc);
- qemu_put_betls(f, &env->npc);
- qemu_put_betls(f, &env->y);
- tmp = cpu_get_psr(env);
- qemu_put_be32(f, tmp);
- qemu_put_betls(f, &env->fsr);
- qemu_put_betls(f, &env->tbr);
- tmp = env->interrupt_index;
- qemu_put_be32(f, tmp);
- qemu_put_be32s(f, &env->pil_in);
-#ifndef TARGET_SPARC64
- qemu_put_be32s(f, &env->wim);
- /* MMU */
- for (i = 0; i < 32; i++)
- qemu_put_be32s(f, &env->mmuregs[i]);
- for (i = 0; i < 4; i++) {
- qemu_put_be64s(f, &env->mxccdata[i]);
- }
- for (i = 0; i < 8; i++) {
- qemu_put_be64s(f, &env->mxccregs[i]);
- }
- qemu_put_be32s(f, &env->mmubpctrv);
- qemu_put_be32s(f, &env->mmubpctrc);
- qemu_put_be32s(f, &env->mmubpctrs);
- qemu_put_be64s(f, &env->mmubpaction);
- for (i = 0; i < 4; i++) {
- qemu_put_be64s(f, &env->mmubpregs[i]);
+static const VMStateDescription vmstate_tlb_entry = {
+ .name = "tlb_entry",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(tag, SparcTLBEntry),
+ VMSTATE_UINT64(tte, SparcTLBEntry),
+ VMSTATE_END_OF_LIST()
}
-#else
- qemu_put_be64s(f, &env->lsu);
- for (i = 0; i < 16; i++) {
- qemu_put_be64s(f, &env->immuregs[i]);
- qemu_put_be64s(f, &env->dmmuregs[i]);
- }
- for (i = 0; i < 64; i++) {
- qemu_put_be64s(f, &env->itlb[i].tag);
- qemu_put_be64s(f, &env->itlb[i].tte);
- qemu_put_be64s(f, &env->dtlb[i].tag);
- qemu_put_be64s(f, &env->dtlb[i].tte);
- }
- qemu_put_be32s(f, &env->mmu_version);
- for (i = 0; i < MAXTL_MAX; i++) {
- qemu_put_be64s(f, &env->ts[i].tpc);
- qemu_put_be64s(f, &env->ts[i].tnpc);
- qemu_put_be64s(f, &env->ts[i].tstate);
- qemu_put_be32s(f, &env->ts[i].tt);
- }
- qemu_put_be32s(f, &env->xcc);
- qemu_put_be32s(f, &env->asi);
- qemu_put_be32s(f, &env->pstate);
- qemu_put_be32s(f, &env->tl);
- qemu_put_be32s(f, &env->cansave);
- qemu_put_be32s(f, &env->canrestore);
- qemu_put_be32s(f, &env->otherwin);
- qemu_put_be32s(f, &env->wstate);
- qemu_put_be32s(f, &env->cleanwin);
- for (i = 0; i < 8; i++)
- qemu_put_be64s(f, &env->agregs[i]);
- for (i = 0; i < 8; i++)
- qemu_put_be64s(f, &env->bgregs[i]);
- for (i = 0; i < 8; i++)
- qemu_put_be64s(f, &env->igregs[i]);
- for (i = 0; i < 8; i++)
- qemu_put_be64s(f, &env->mgregs[i]);
- qemu_put_be64s(f, &env->fprs);
- qemu_put_be64s(f, &env->tick_cmpr);
- qemu_put_be64s(f, &env->stick_cmpr);
- cpu_put_timer(f, env->tick);
- cpu_put_timer(f, env->stick);
- qemu_put_be64s(f, &env->gsr);
- qemu_put_be32s(f, &env->gl);
- qemu_put_be64s(f, &env->hpstate);
- for (i = 0; i < MAXTL_MAX; i++)
- qemu_put_be64s(f, &env->htstate[i]);
- qemu_put_be64s(f, &env->hintp);
- qemu_put_be64s(f, &env->htba);
- qemu_put_be64s(f, &env->hver);
- qemu_put_be64s(f, &env->hstick_cmpr);
- qemu_put_be64s(f, &env->ssr);
- cpu_put_timer(f, env->hstick);
+};
#endif
-}
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
+static void cpu_pre_save(void *opaque)
{
CPUState *env = opaque;
- int i;
- uint32_t tmp;
- if (version_id < 6)
- return -EINVAL;
- for(i = 0; i < 8; i++)
- qemu_get_betls(f, &env->gregs[i]);
- qemu_get_be32s(f, &env->nwindows);
- for(i = 0; i < env->nwindows * 16; i++)
- qemu_get_betls(f, &env->regbase[i]);
+ /* if env->cwp == env->nwindows - 1, this will set the ins of the last
+ * window as the outs of the first window
+ */
+ cpu_set_cwp(env, env->cwp);
+ env->psr_vmstate = cpu_get_psr(env);
+}
- /* FPU */
- for(i = 0; i < TARGET_FPREGS; i++) {
- union {
- float32 f;
- uint32_t i;
- } u;
- u.i = qemu_get_be32(f);
- env->fpr[i] = u.f;
- }
+static int cpu_post_load(void *opaque, int version_id)
+{
+ CPUState *env = opaque;
- qemu_get_betls(f, &env->pc);
- qemu_get_betls(f, &env->npc);
- qemu_get_betls(f, &env->y);
- tmp = qemu_get_be32(f);
env->cwp = 0; /* needed to ensure that the wrapping registers are
correctly updated */
- cpu_put_psr(env, tmp);
- qemu_get_betls(f, &env->fsr);
- qemu_get_betls(f, &env->tbr);
- tmp = qemu_get_be32(f);
- env->interrupt_index = tmp;
- qemu_get_be32s(f, &env->pil_in);
-#ifndef TARGET_SPARC64
- qemu_get_be32s(f, &env->wim);
- /* MMU */
- for (i = 0; i < 32; i++)
- qemu_get_be32s(f, &env->mmuregs[i]);
- for (i = 0; i < 4; i++) {
- qemu_get_be64s(f, &env->mxccdata[i]);
- }
- for (i = 0; i < 8; i++) {
- qemu_get_be64s(f, &env->mxccregs[i]);
- }
- qemu_get_be32s(f, &env->mmubpctrv);
- qemu_get_be32s(f, &env->mmubpctrc);
- qemu_get_be32s(f, &env->mmubpctrs);
- qemu_get_be64s(f, &env->mmubpaction);
- for (i = 0; i < 4; i++) {
- qemu_get_be64s(f, &env->mmubpregs[i]);
- }
-#else
- qemu_get_be64s(f, &env->lsu);
- for (i = 0; i < 16; i++) {
- qemu_get_be64s(f, &env->immuregs[i]);
- qemu_get_be64s(f, &env->dmmuregs[i]);
- }
- for (i = 0; i < 64; i++) {
- qemu_get_be64s(f, &env->itlb[i].tag);
- qemu_get_be64s(f, &env->itlb[i].tte);
- qemu_get_be64s(f, &env->dtlb[i].tag);
- qemu_get_be64s(f, &env->dtlb[i].tte);
- }
- qemu_get_be32s(f, &env->mmu_version);
- for (i = 0; i < MAXTL_MAX; i++) {
- qemu_get_be64s(f, &env->ts[i].tpc);
- qemu_get_be64s(f, &env->ts[i].tnpc);
- qemu_get_be64s(f, &env->ts[i].tstate);
- qemu_get_be32s(f, &env->ts[i].tt);
- }
- qemu_get_be32s(f, &env->xcc);
- qemu_get_be32s(f, &env->asi);
- qemu_get_be32s(f, &env->pstate);
- qemu_get_be32s(f, &env->tl);
- qemu_get_be32s(f, &env->cansave);
- qemu_get_be32s(f, &env->canrestore);
- qemu_get_be32s(f, &env->otherwin);
- qemu_get_be32s(f, &env->wstate);
- qemu_get_be32s(f, &env->cleanwin);
- for (i = 0; i < 8; i++)
- qemu_get_be64s(f, &env->agregs[i]);
- for (i = 0; i < 8; i++)
- qemu_get_be64s(f, &env->bgregs[i]);
- for (i = 0; i < 8; i++)
- qemu_get_be64s(f, &env->igregs[i]);
- for (i = 0; i < 8; i++)
- qemu_get_be64s(f, &env->mgregs[i]);
- qemu_get_be64s(f, &env->fprs);
- qemu_get_be64s(f, &env->tick_cmpr);
- qemu_get_be64s(f, &env->stick_cmpr);
- cpu_get_timer(f, env->tick);
- cpu_get_timer(f, env->stick);
- qemu_get_be64s(f, &env->gsr);
- qemu_get_be32s(f, &env->gl);
- qemu_get_be64s(f, &env->hpstate);
- for (i = 0; i < MAXTL_MAX; i++)
- qemu_get_be64s(f, &env->htstate[i]);
- qemu_get_be64s(f, &env->hintp);
- qemu_get_be64s(f, &env->htba);
- qemu_get_be64s(f, &env->hver);
- qemu_get_be64s(f, &env->hstick_cmpr);
- qemu_get_be64s(f, &env->ssr);
- cpu_get_timer(f, env->hstick);
-#endif
+ cpu_put_psr(env, env->psr_vmstate);
tlb_flush(env, 1);
return 0;
}
+
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .version_id = 7,
+ .minimum_version_id = 7,
+ .minimum_version_id_old = 7,
+ .pre_save = cpu_pre_save,
+ .post_load = cpu_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL_ARRAY(gregs, CPUState, 8),
+ VMSTATE_UINT32(nwindows, CPUState),
+ VMSTATE_VARRAY_MULTIPLY(regbase, CPUState, nwindows, 16,
+ vmstate_info_uinttls, target_ulong),
+ VMSTATE_FLOAT32_ARRAY(fpr, CPUState, TARGET_FPREGS),
+ VMSTATE_UINTTL(pc, CPUState),
+ VMSTATE_UINTTL(npc, CPUState),
+ VMSTATE_UINTTL(y, CPUState),
+ VMSTATE_UINT32(psr_vmstate, CPUState),
+ VMSTATE_UINTTL(fsr, CPUState),
+ VMSTATE_UINTTL(tbr, CPUState),
+ VMSTATE_INT32(interrupt_index, CPUState),
+ VMSTATE_UINT32(pil_in, CPUState),
+#ifndef TARGET_SPARC64
+ /* MMU */
+ VMSTATE_UINT32(wim, CPUState),
+ VMSTATE_UINT32_ARRAY(mmuregs, CPUState, 32),
+ VMSTATE_UINT64_ARRAY(mxccdata, CPUState, 4),
+ VMSTATE_UINT64_ARRAY(mxccregs, CPUState, 8),
+ VMSTATE_UINT32(mmubpctrv, CPUState),
+ VMSTATE_UINT32(mmubpctrc, CPUState),
+ VMSTATE_UINT32(mmubpctrs, CPUState),
+ VMSTATE_UINT64(mmubpaction, CPUState),
+ VMSTATE_UINT64_ARRAY(mmubpregs, CPUState, 4),
+#else
+ VMSTATE_UINT64(lsu, CPUState),
+ VMSTATE_UINT64(immuregs[0], CPUState),
+ VMSTATE_UINT64(dmmuregs[0], CPUState),
+ VMSTATE_UINT64(immuregs[1], CPUState),
+ VMSTATE_UINT64(dmmuregs[1], CPUState),
+ VMSTATE_UINT64(immuregs[2], CPUState),
+ VMSTATE_UINT64(dmmuregs[2], CPUState),
+ VMSTATE_UINT64(immuregs[3], CPUState),
+ VMSTATE_UINT64(dmmuregs[3], CPUState),
+ VMSTATE_UINT64(immuregs[4], CPUState),
+ VMSTATE_UINT64(dmmuregs[4], CPUState),
+ VMSTATE_UINT64(immuregs[5], CPUState),
+ VMSTATE_UINT64(dmmuregs[5], CPUState),
+ VMSTATE_UINT64(immuregs[6], CPUState),
+ VMSTATE_UINT64(dmmuregs[6], CPUState),
+ VMSTATE_UINT64(immuregs[7], CPUState),
+ VMSTATE_UINT64(dmmuregs[7], CPUState),
+ VMSTATE_UINT64(immuregs[8], CPUState),
+ VMSTATE_UINT64(dmmuregs[8], CPUState),
+ VMSTATE_UINT64(immuregs[9], CPUState),
+ VMSTATE_UINT64(dmmuregs[9], CPUState),
+ VMSTATE_UINT64(immuregs[10], CPUState),
+ VMSTATE_UINT64(dmmuregs[10], CPUState),
+ VMSTATE_UINT64(immuregs[11], CPUState),
+ VMSTATE_UINT64(dmmuregs[11], CPUState),
+ VMSTATE_UINT64(immuregs[12], CPUState),
+ VMSTATE_UINT64(dmmuregs[12], CPUState),
+ VMSTATE_UINT64(immuregs[13], CPUState),
+ VMSTATE_UINT64(dmmuregs[13], CPUState),
+ VMSTATE_UINT64(immuregs[14], CPUState),
+ VMSTATE_UINT64(dmmuregs[14], CPUState),
+ VMSTATE_UINT64(immuregs[15], CPUState),
+ VMSTATE_UINT64(dmmuregs[15], CPUState),
+ VMSTATE_STRUCT(itlb[0], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[0], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[1], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[1], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[2], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[2], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[3], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[3], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[4], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[4], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[5], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[5], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[6], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[6], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[7], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[7], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[8], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[8], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[9], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[9], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[10], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[10], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[11], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[11], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[12], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[12], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[13], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[13], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[14], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[14], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[15], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[15], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[16], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[16], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[17], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[17], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[18], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[18], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[19], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[19], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[20], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[20], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[21], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[21], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[22], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[22], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[23], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[23], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[24], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[24], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[25], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[25], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[26], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[26], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[27], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[27], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[28], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[28], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[29], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[29], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[30], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[30], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[31], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[31], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[32], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[32], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[33], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[33], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[34], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[34], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[35], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[35], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[36], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[36], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[37], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[37], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[38], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[38], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[39], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[39], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[40], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[40], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[41], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[41], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[42], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[42], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[43], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[43], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[44], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[44], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[45], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[45], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[46], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[46], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[47], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[47], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[48], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[48], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[49], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[49], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[50], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[50], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[51], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[51], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[52], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[52], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[53], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[53], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[54], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[54], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[55], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[55], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[56], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[56], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[57], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[57], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[58], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[58], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[59], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[59], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[60], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[60], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[61], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[61], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[62], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[62], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[63], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[63], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_UINT32(mmu_version, CPUState),
+ VMSTATE_STRUCT_ARRAY(ts, CPUState, MAXTL_MAX, 0,
+ vmstate_trap_state, trap_state),
+ VMSTATE_UINT32(xcc, CPUState),
+ VMSTATE_UINT32(asi, CPUState),
+ VMSTATE_UINT32(pstate, CPUState),
+ VMSTATE_UINT32(tl, CPUState),
+ VMSTATE_UINT32(cansave, CPUState),
+ VMSTATE_UINT32(canrestore, CPUState),
+ VMSTATE_UINT32(otherwin, CPUState),
+ VMSTATE_UINT32(wstate, CPUState),
+ VMSTATE_UINT32(cleanwin, CPUState),
+ VMSTATE_UINT64_ARRAY(agregs, CPUState, 8),
+ VMSTATE_UINT64_ARRAY(bgregs, CPUState, 8),
+ VMSTATE_UINT64_ARRAY(igregs, CPUState, 8),
+ VMSTATE_UINT64_ARRAY(mgregs, CPUState, 8),
+ VMSTATE_UINT64(fprs, CPUState),
+ VMSTATE_UINT64(tick_cmpr, CPUState),
+ VMSTATE_UINT64(stick_cmpr, CPUState),
+ VMSTATE_CPU_TIMER(tick, CPUState),
+ VMSTATE_CPU_TIMER(stick, CPUState),
+ VMSTATE_UINT64(gsr, CPUState),
+ VMSTATE_UINT32(gl, CPUState),
+ VMSTATE_UINT64(hpstate, CPUState),
+ VMSTATE_UINT64_ARRAY(htstate, CPUState, MAXTL_MAX),
+ VMSTATE_UINT64(hintp, CPUState),
+ VMSTATE_UINT64(htba, CPUState),
+ VMSTATE_UINT64(hver, CPUState),
+ VMSTATE_UINT64(hstick_cmpr, CPUState),
+ VMSTATE_UINT64(ssr, CPUState),
+ VMSTATE_CPU_TIMER(hstick, CPUState),
+#endif
+ VMSTATE_END_OF_LIST()
+ },
+};
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 17/25] vmstate: make incompatible change for sparc
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (15 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 16/25] vmstate: port sparc cpu Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 20:30 ` Blue Swirl
2011-10-25 14:00 ` [Qemu-devel] [PATCH 18/25] mips_fulong2e: cpu vmstate already registered in cpu_exec_init Juan Quintela
` (7 subsequent siblings)
24 siblings, 1 reply; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Blue Swirl, aliguori
With this change, we sent arrays as arrays, making state description
much simpler. The change is incompatible, but as far as I know, sparc
don't care about migration compatibility beteween versions.
Signed-off-by: Juan Quintela <quintela@redhat.com>
CC: Blue Swirl <blauwirbel@gmail.com>
---
target-sparc/machine.c | 172 +++---------------------------------------------
1 files changed, 9 insertions(+), 163 deletions(-)
diff --git a/target-sparc/machine.c b/target-sparc/machine.c
index 2186756..ccca36f 100644
--- a/target-sparc/machine.c
+++ b/target-sparc/machine.c
@@ -74,9 +74,9 @@ static int cpu_post_load(void *opaque, int version_id)
const VMStateDescription vmstate_cpu = {
.name = "cpu",
- .version_id = 7,
- .minimum_version_id = 7,
- .minimum_version_id_old = 7,
+ .version_id = 8,
+ .minimum_version_id = 8,
+ .minimum_version_id_old = 8,
.pre_save = cpu_pre_save,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
@@ -106,166 +106,12 @@ const VMStateDescription vmstate_cpu = {
VMSTATE_UINT64_ARRAY(mmubpregs, CPUState, 4),
#else
VMSTATE_UINT64(lsu, CPUState),
- VMSTATE_UINT64(immuregs[0], CPUState),
- VMSTATE_UINT64(dmmuregs[0], CPUState),
- VMSTATE_UINT64(immuregs[1], CPUState),
- VMSTATE_UINT64(dmmuregs[1], CPUState),
- VMSTATE_UINT64(immuregs[2], CPUState),
- VMSTATE_UINT64(dmmuregs[2], CPUState),
- VMSTATE_UINT64(immuregs[3], CPUState),
- VMSTATE_UINT64(dmmuregs[3], CPUState),
- VMSTATE_UINT64(immuregs[4], CPUState),
- VMSTATE_UINT64(dmmuregs[4], CPUState),
- VMSTATE_UINT64(immuregs[5], CPUState),
- VMSTATE_UINT64(dmmuregs[5], CPUState),
- VMSTATE_UINT64(immuregs[6], CPUState),
- VMSTATE_UINT64(dmmuregs[6], CPUState),
- VMSTATE_UINT64(immuregs[7], CPUState),
- VMSTATE_UINT64(dmmuregs[7], CPUState),
- VMSTATE_UINT64(immuregs[8], CPUState),
- VMSTATE_UINT64(dmmuregs[8], CPUState),
- VMSTATE_UINT64(immuregs[9], CPUState),
- VMSTATE_UINT64(dmmuregs[9], CPUState),
- VMSTATE_UINT64(immuregs[10], CPUState),
- VMSTATE_UINT64(dmmuregs[10], CPUState),
- VMSTATE_UINT64(immuregs[11], CPUState),
- VMSTATE_UINT64(dmmuregs[11], CPUState),
- VMSTATE_UINT64(immuregs[12], CPUState),
- VMSTATE_UINT64(dmmuregs[12], CPUState),
- VMSTATE_UINT64(immuregs[13], CPUState),
- VMSTATE_UINT64(dmmuregs[13], CPUState),
- VMSTATE_UINT64(immuregs[14], CPUState),
- VMSTATE_UINT64(dmmuregs[14], CPUState),
- VMSTATE_UINT64(immuregs[15], CPUState),
- VMSTATE_UINT64(dmmuregs[15], CPUState),
- VMSTATE_STRUCT(itlb[0], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[0], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[1], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[1], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[2], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[2], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[3], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[3], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[4], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[4], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[5], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[5], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[6], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[6], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[7], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[7], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[8], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[8], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[9], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[9], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[10], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[10], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[11], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[11], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[12], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[12], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[13], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[13], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[14], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[14], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[15], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[15], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[16], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[16], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[17], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[17], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[18], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[18], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[19], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[19], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[20], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[20], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[21], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[21], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[22], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[22], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[23], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[23], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[24], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[24], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[25], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[25], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[26], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[26], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[27], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[27], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[28], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[28], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[29], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[29], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[30], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[30], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[31], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[31], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[32], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[32], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[33], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[33], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[34], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[34], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[35], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[35], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[36], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[36], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[37], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[37], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[38], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[38], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[39], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[39], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[40], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[40], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[41], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[41], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[42], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[42], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[43], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[43], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[44], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[44], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[45], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[45], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[46], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[46], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[47], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[47], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[48], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[48], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[49], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[49], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[50], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[50], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[51], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[51], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[52], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[52], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[53], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[53], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[54], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[54], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[55], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[55], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[56], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[56], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[57], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[57], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[58], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[58], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[59], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[59], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[60], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[60], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[61], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[61], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[62], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[62], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[63], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[63], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_UINT64_ARRAY(immuregs, CPUState, 16),
+ VMSTATE_UINT64_ARRAY(dmmuregs, CPUState, 16),
+ VMSTATE_STRUCT_ARRAY(itlb, CPUState, 64, 0,
+ vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT_ARRAY(dtlb, CPUState, 64, 0,
+ vmstate_tlb_entry, SparcTLBEntry),
VMSTATE_UINT32(mmu_version, CPUState),
VMSTATE_STRUCT_ARRAY(ts, CPUState, MAXTL_MAX, 0,
vmstate_trap_state, trap_state),
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 18/25] mips_fulong2e: cpu vmstate already registered in cpu_exec_init
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (16 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 17/25] vmstate: make incompatible change for sparc Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 19/25] mips: make mvp an embedded struct instead of pointer Juan Quintela
` (6 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Huacai Chen, aliguori
This is the second place that register cpu migration code, it is done
in general in cpu_exec_init(), just remove this call.
Signed-off-by: Juan Quintela <quintela@redhat.com>
CC: Huacai Chen <zltjiangshi@gmail.com>
---
hw/mips_fulong2e.c | 1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/hw/mips_fulong2e.c b/hw/mips_fulong2e.c
index 04921c1..d96b7dc 100644
--- a/hw/mips_fulong2e.c
+++ b/hw/mips_fulong2e.c
@@ -281,7 +281,6 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
exit(1);
}
- register_savevm(NULL, "cpu", 0, 3, cpu_save, cpu_load, env);
qemu_register_reset(main_cpu_reset, env);
/* fulong 2e has 256M ram. */
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 19/25] mips: make mvp an embedded struct instead of pointer
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (17 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 18/25] mips_fulong2e: cpu vmstate already registered in cpu_exec_init Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 20/25] mips: make tlb an embedded struct instead of a pointer Juan Quintela
` (5 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori, Aurelien Jarno
Adjust all callers.
Signed-off-by: Juan Quintela <quintela@redhat.com>
CC: Aurelien Jarno <aurelien@aurel32.net>
---
hw/mips_malta.c | 4 ++--
target-mips/cpu.h | 4 ++--
target-mips/machine.c | 12 ++++++------
target-mips/op_helper.c | 30 +++++++++++++++++-------------
target-mips/translate.c | 6 +++---
target-mips/translate_init.c | 14 ++++++--------
6 files changed, 36 insertions(+), 34 deletions(-)
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index bb49749..cd40e7b 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -732,8 +732,8 @@ static int64_t load_kernel (void)
static void malta_mips_config(CPUState *env)
{
- env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
- ((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC);
+ env->mvp.CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
+ ((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC);
}
static void main_cpu_reset(void *opaque)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 79e2558..e11865b 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -473,7 +473,7 @@ struct CPUMIPSState {
CPU_COMMON
- CPUMIPSMVPContext *mvp;
+ CPUMIPSMVPContext mvp;
#if !defined(CONFIG_USER_ONLY)
CPUMIPSTLBContext *tlb;
#endif
@@ -675,7 +675,7 @@ static inline int mips_vpe_active(CPUState *env)
int active = 1;
/* Check that the VPE is enabled. */
- if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
+ if (!(env->mvp.CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
active = 0;
}
/* Check that the VPE is actived. */
diff --git a/target-mips/machine.c b/target-mips/machine.c
index be72b36..8137488 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -52,9 +52,9 @@ void cpu_save(QEMUFile *f, void *opaque)
save_fpu(f, &env->active_fpu);
/* Save MVP */
- qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl);
- qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0);
- qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1);
+ qemu_put_sbe32s(f, &env->mvp.CP0_MVPControl);
+ qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf0);
+ qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf1);
/* Save TLB */
qemu_put_be32s(f, &env->tlb->nb_tlb);
@@ -203,9 +203,9 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
load_fpu(f, &env->active_fpu);
/* Load MVP */
- qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl);
- qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0);
- qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1);
+ qemu_get_sbe32s(f, &env->mvp.CP0_MVPControl);
+ qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf0);
+ qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf1);
/* Load TLB */
qemu_get_be32s(f, &env->tlb->nb_tlb);
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index c51b9cb..a5d095c 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -909,17 +909,17 @@ static void sync_c0_entryhi(CPUState *cpu, int tc)
/* CP0 helpers */
target_ulong helper_mfc0_mvpcontrol (void)
{
- return env->mvp->CP0_MVPControl;
+ return env->mvp.CP0_MVPControl;
}
target_ulong helper_mfc0_mvpconf0 (void)
{
- return env->mvp->CP0_MVPConf0;
+ return env->mvp.CP0_MVPConf0;
}
target_ulong helper_mfc0_mvpconf1 (void)
{
- return env->mvp->CP0_MVPConf1;
+ return env->mvp.CP0_MVPConf1;
}
target_ulong helper_mfc0_random (void)
@@ -1172,13 +1172,14 @@ void helper_mtc0_mvpcontrol (target_ulong arg1)
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
(1 << CP0MVPCo_EVP);
- if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (1 << CP0MVPCo_STLB);
- newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
+ }
+ newval = (env->mvp.CP0_MVPControl & ~mask) | (arg1 & mask);
// TODO: Enable/disable shared TLB, enable/disable VPEs.
- env->mvp->CP0_MVPControl = newval;
+ env->mvp.CP0_MVPControl = newval;
}
void helper_mtc0_vpecontrol (target_ulong arg1)
@@ -1266,9 +1267,10 @@ void helper_mtc0_vpeconf1 (target_ulong arg1)
uint32_t mask = 0;
uint32_t newval;
- if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
(0xff << CP0VPEC1_NCP1);
+ }
newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
/* UDI not implemented. */
@@ -1325,8 +1327,9 @@ void helper_mtc0_tcbind (target_ulong arg1)
uint32_t mask = (1 << CP0TCBd_TBE);
uint32_t newval;
- if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (1 << CP0TCBd_CurVPE);
+ }
newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
env->active_tc.CP0_TCBind = newval;
}
@@ -1338,8 +1341,9 @@ void helper_mttc0_tcbind (target_ulong arg1)
uint32_t newval;
CPUState *other = mips_cpu_map_tc(&other_tc);
- if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ if (other->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (1 << CP0TCBd_CurVPE);
+ }
if (other_tc == other->current_tc) {
newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
other->active_tc.CP0_TCBind = newval;
@@ -1910,12 +1914,12 @@ target_ulong helper_emt(void)
target_ulong helper_dvpe(void)
{
CPUState *other_cpu = first_cpu;
- target_ulong prev = env->mvp->CP0_MVPControl;
+ target_ulong prev = env->mvp.CP0_MVPControl;
do {
/* Turn off all VPEs except the one executing the dvpe. */
if (other_cpu != env) {
- other_cpu->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
+ other_cpu->mvp.CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
mips_vpe_sleep(other_cpu);
}
other_cpu = other_cpu->next_cpu;
@@ -1926,14 +1930,14 @@ target_ulong helper_dvpe(void)
target_ulong helper_evpe(void)
{
CPUState *other_cpu = first_cpu;
- target_ulong prev = env->mvp->CP0_MVPControl;
+ target_ulong prev = env->mvp.CP0_MVPControl;
do {
if (other_cpu != env
/* If the VPE is WFI, dont distrub it's sleep. */
&& !mips_vpe_is_wfi(other_cpu)) {
/* Enable the VPE. */
- other_cpu->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+ other_cpu->mvp.CP0_MVPControl |= (1 << CP0MVPCo_EVP);
mips_vpe_wake(other_cpu); /* And wake it up. */
}
other_cpu = other_cpu->next_cpu;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index d5b1c76..c655a34 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -5533,7 +5533,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, int rd,
(env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
tcg_gen_movi_tl(t0, -1);
else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
- (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
+ (env->mvp.CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
tcg_gen_movi_tl(t0, -1);
else if (u == 0) {
switch (rt) {
@@ -5751,7 +5751,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, int rt,
(env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
/* NOP */ ;
else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
- (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
+ (env->mvp.CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
/* NOP */ ;
else if (u == 0) {
switch (rd) {
@@ -12827,7 +12827,7 @@ void cpu_reset (CPUMIPSState *env)
if (!env->cpu_index) {
/* VPE0 starts up enabled. */
- env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+ env->mvp.CP0_MVPControl |= (1 << CP0MVPCo_EVP);
env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
/* TC0 starts up unhalted. */
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c39138f..54fd1eb 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -568,27 +568,25 @@ static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
{
- env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
-
/* MVPConf1 implemented, TLB sharable, no gating storage support,
programmable cache partitioning implemented, number of allocatable
and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
implemented, 5 TCs implemented. */
- env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
- (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
+ env->mvp.CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
+ (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
// TODO: actually do 2 VPEs.
// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
// (0x04 << CP0MVPC0_PTC);
- (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
- (0x00 << CP0MVPC0_PTC);
+ (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
+ (0x00 << CP0MVPC0_PTC);
#if !defined(CONFIG_USER_ONLY)
/* Usermode has no TLB support */
- env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
+ env->mvp.CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
#endif
/* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
- env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
+ env->mvp.CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
(0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
(0x1 << CP0MVPC1_PCP1);
}
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 20/25] mips: make tlb an embedded struct instead of a pointer
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (18 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 19/25] mips: make mvp an embedded struct instead of pointer Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 21/25] mips: bump migration version to 4 Juan Quintela
` (4 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori, Aurelien Jarno
Adjust all callers.
Signed-off-by: Juan Quintela <quintela@redhat.com>
CC: Aurelien Jarno <aurelien@aurel32.net>
---
hw/mips_timer.c | 2 +-
target-mips/cpu.h | 2 +-
target-mips/helper.c | 30 +++++++++++++---------
target-mips/machine.c | 56 +++++++++++++++++++++---------------------
target-mips/op_helper.c | 40 +++++++++++++++---------------
target-mips/translate.c | 16 +++++++----
target-mips/translate_init.c | 24 ++++++++---------
7 files changed, 89 insertions(+), 81 deletions(-)
diff --git a/hw/mips_timer.c b/hw/mips_timer.c
index cf6ac69..cb72d0d 100644
--- a/hw/mips_timer.c
+++ b/hw/mips_timer.c
@@ -35,7 +35,7 @@ uint32_t cpu_mips_get_random (CPUState *env)
/* Don't return same value twice, so get another value */
do {
lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u);
- idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
+ idx = lfsr % (env->tlb.nb_tlb - env->CP0_Wired) + env->CP0_Wired;
} while (idx == prev_idx);
prev_idx = idx;
return idx;
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index e11865b..7ca751b 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -475,7 +475,7 @@ struct CPUMIPSState {
CPUMIPSMVPContext mvp;
#if !defined(CONFIG_USER_ONLY)
- CPUMIPSTLBContext *tlb;
+ CPUMIPSTLBContext tlb;
#endif
const mips_def_t *cpu_model;
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 1c58e0c..32209e3 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -69,8 +69,8 @@ int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
uint8_t ASID = env->CP0_EntryHi & 0xFF;
int i;
- for (i = 0; i < env->tlb->tlb_in_use; i++) {
- r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
+ for (i = 0; i < env->tlb.tlb_in_use; i++) {
+ r4k_tlb_t *tlb = &env->tlb.mmu.r4k.tlb[i];
/* 1k pages are not supported. */
target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
target_ulong tag = address & ~mask;
@@ -124,13 +124,15 @@ static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
*physical = address & 0xFFFFFFFF;
*prot = PAGE_READ | PAGE_WRITE;
} else {
- ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ ret = env->tlb.map_address(env, physical, prot, address, rw,
+ access_type);
}
#if defined(TARGET_MIPS64)
} else if (address < 0x4000000000000000ULL) {
/* xuseg */
if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
- ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ ret = env->tlb.map_address(env, physical, prot, address, rw,
+ access_type);
} else {
ret = TLBRET_BADADDR;
}
@@ -138,7 +140,8 @@ static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
/* xsseg */
if ((supervisor_mode || kernel_mode) &&
SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
- ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ ret = env->tlb.map_address(env, physical, prot, address, rw,
+ access_type);
} else {
ret = TLBRET_BADADDR;
}
@@ -155,7 +158,8 @@ static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
/* xkseg */
if (kernel_mode && KX &&
address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
- ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ ret = env->tlb.map_address(env, physical, prot, address, rw,
+ access_type);
} else {
ret = TLBRET_BADADDR;
}
@@ -179,7 +183,8 @@ static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
} else if (address < (int32_t)0xE0000000UL) {
/* sseg (kseg2) */
if (supervisor_mode || kernel_mode) {
- ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ ret = env->tlb.map_address(env, physical, prot, address, rw,
+ access_type);
} else {
ret = TLBRET_BADADDR;
}
@@ -187,7 +192,8 @@ static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
/* kseg3 */
/* XXX: debug segment is not emulated */
if (kernel_mode) {
- ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ ret = env->tlb.map_address(env, physical, prot, address, rw,
+ access_type);
} else {
ret = TLBRET_BADADDR;
}
@@ -645,19 +651,19 @@ void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
uint8_t ASID = env->CP0_EntryHi & 0xFF;
target_ulong mask;
- tlb = &env->tlb->mmu.r4k.tlb[idx];
+ tlb = &env->tlb.mmu.r4k.tlb[idx];
/* The qemu TLB is flushed when the ASID changes, so no need to
flush these entries again. */
if (tlb->G == 0 && tlb->ASID != ASID) {
return;
}
- if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
+ if (use_extra && env->tlb.tlb_in_use < MIPS_TLB_MAX) {
/* For tlbwr, we can shadow the discarded entry into
a new (fake) TLB entry, as long as the guest can not
tell that it's there. */
- env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
- env->tlb->tlb_in_use++;
+ env->tlb.mmu.r4k.tlb[env->tlb.tlb_in_use] = *tlb;
+ env->tlb.tlb_in_use++;
return;
}
diff --git a/target-mips/machine.c b/target-mips/machine.c
index 8137488..a55fbb6 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -57,25 +57,25 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf1);
/* Save TLB */
- qemu_put_be32s(f, &env->tlb->nb_tlb);
- qemu_put_be32s(f, &env->tlb->tlb_in_use);
+ qemu_put_be32s(f, &env->tlb.nb_tlb);
+ qemu_put_be32s(f, &env->tlb.tlb_in_use);
for(i = 0; i < MIPS_TLB_MAX; i++) {
- uint16_t flags = ((env->tlb->mmu.r4k.tlb[i].G << 10) |
- (env->tlb->mmu.r4k.tlb[i].C0 << 7) |
- (env->tlb->mmu.r4k.tlb[i].C1 << 4) |
- (env->tlb->mmu.r4k.tlb[i].V0 << 3) |
- (env->tlb->mmu.r4k.tlb[i].V1 << 2) |
- (env->tlb->mmu.r4k.tlb[i].D0 << 1) |
- (env->tlb->mmu.r4k.tlb[i].D1 << 0));
+ uint16_t flags = ((env->tlb.mmu.r4k.tlb[i].G << 10) |
+ (env->tlb.mmu.r4k.tlb[i].C0 << 7) |
+ (env->tlb.mmu.r4k.tlb[i].C1 << 4) |
+ (env->tlb.mmu.r4k.tlb[i].V0 << 3) |
+ (env->tlb.mmu.r4k.tlb[i].V1 << 2) |
+ (env->tlb.mmu.r4k.tlb[i].D0 << 1) |
+ (env->tlb.mmu.r4k.tlb[i].D1 << 0));
uint8_t asid;
- qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
- qemu_put_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
- asid = env->tlb->mmu.r4k.tlb[i].ASID;
+ qemu_put_betls(f, &env->tlb.mmu.r4k.tlb[i].VPN);
+ qemu_put_be32s(f, &env->tlb.mmu.r4k.tlb[i].PageMask);
+ asid = env->tlb.mmu.r4k.tlb[i].ASID;
qemu_put_8s(f, &asid);
qemu_put_be16s(f, &flags);
- qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
- qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
+ qemu_put_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[0]);
+ qemu_put_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[1]);
}
/* Save CPU metastate */
@@ -208,26 +208,26 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf1);
/* Load TLB */
- qemu_get_be32s(f, &env->tlb->nb_tlb);
- qemu_get_be32s(f, &env->tlb->tlb_in_use);
+ qemu_get_be32s(f, &env->tlb.nb_tlb);
+ qemu_get_be32s(f, &env->tlb.tlb_in_use);
for(i = 0; i < MIPS_TLB_MAX; i++) {
uint16_t flags;
uint8_t asid;
- qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
- qemu_get_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
+ qemu_get_betls(f, &env->tlb.mmu.r4k.tlb[i].VPN);
+ qemu_get_be32s(f, &env->tlb.mmu.r4k.tlb[i].PageMask);
qemu_get_8s(f, &asid);
- env->tlb->mmu.r4k.tlb[i].ASID = asid;
+ env->tlb.mmu.r4k.tlb[i].ASID = asid;
qemu_get_be16s(f, &flags);
- env->tlb->mmu.r4k.tlb[i].G = (flags >> 10) & 1;
- env->tlb->mmu.r4k.tlb[i].C0 = (flags >> 7) & 3;
- env->tlb->mmu.r4k.tlb[i].C1 = (flags >> 4) & 3;
- env->tlb->mmu.r4k.tlb[i].V0 = (flags >> 3) & 1;
- env->tlb->mmu.r4k.tlb[i].V1 = (flags >> 2) & 1;
- env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1;
- env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1;
- qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
- qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
+ env->tlb.mmu.r4k.tlb[i].G = (flags >> 10) & 1;
+ env->tlb.mmu.r4k.tlb[i].C0 = (flags >> 7) & 3;
+ env->tlb.mmu.r4k.tlb[i].C1 = (flags >> 4) & 3;
+ env->tlb.mmu.r4k.tlb[i].V0 = (flags >> 3) & 1;
+ env->tlb.mmu.r4k.tlb[i].V1 = (flags >> 2) & 1;
+ env->tlb.mmu.r4k.tlb[i].D0 = (flags >> 1) & 1;
+ env->tlb.mmu.r4k.tlb[i].D1 = (flags >> 0) & 1;
+ qemu_get_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[0]);
+ qemu_get_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[1]);
}
/* Load CPU metastate */
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index a5d095c..85efac1 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1155,7 +1155,7 @@ target_ulong helper_dmfc0_watchlo (uint32_t sel)
void helper_mtc0_index (target_ulong arg1)
{
int num = 1;
- unsigned int tmp = env->tlb->nb_tlb;
+ unsigned int tmp = env->tlb.nb_tlb;
do {
tmp >>= 1;
@@ -1486,7 +1486,7 @@ void helper_mtc0_pagegrain (target_ulong arg1)
void helper_mtc0_wired (target_ulong arg1)
{
- env->CP0_Wired = arg1 % env->tlb->nb_tlb;
+ env->CP0_Wired = arg1 % env->tlb.nb_tlb;
}
void helper_mtc0_srsconf0 (target_ulong arg1)
@@ -1989,14 +1989,14 @@ static void cpu_mips_tlb_flush (CPUState *env, int flush_global)
{
/* Flush qemu's TLB and discard all shadowed entries. */
tlb_flush (env, flush_global);
- env->tlb->tlb_in_use = env->tlb->nb_tlb;
+ env->tlb.tlb_in_use = env->tlb.nb_tlb;
}
static void r4k_mips_tlb_flush_extra (CPUState *env, int first)
{
/* Discard entries from env->tlb[first] onwards. */
- while (env->tlb->tlb_in_use > first) {
- r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
+ while (env->tlb.tlb_in_use > first) {
+ r4k_invalidate_tlb(env, --env->tlb.tlb_in_use, 0);
}
}
@@ -2005,7 +2005,7 @@ static void r4k_fill_tlb (int idx)
r4k_tlb_t *tlb;
/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
- tlb = &env->tlb->mmu.r4k.tlb[idx];
+ tlb = &env->tlb.mmu.r4k.tlb[idx];
tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
#if defined(TARGET_MIPS64)
tlb->VPN &= env->SEGMask;
@@ -2027,12 +2027,12 @@ void r4k_helper_tlbwi (void)
{
int idx;
- idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
+ idx = (env->CP0_Index & ~0x80000000) % env->tlb.nb_tlb;
/* Discard cached TLB entries. We could avoid doing this if the
tlbwi is just upgrading access permissions on the current entry;
that might be a further win. */
- r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
+ r4k_mips_tlb_flush_extra(env, env->tlb.nb_tlb);
r4k_invalidate_tlb(env, idx, 0);
r4k_fill_tlb(idx);
@@ -2056,8 +2056,8 @@ void r4k_helper_tlbp (void)
int i;
ASID = env->CP0_EntryHi & 0xFF;
- for (i = 0; i < env->tlb->nb_tlb; i++) {
- tlb = &env->tlb->mmu.r4k.tlb[i];
+ for (i = 0; i < env->tlb.nb_tlb; i++) {
+ tlb = &env->tlb.mmu.r4k.tlb[i];
/* 1k pages are not supported. */
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
tag = env->CP0_EntryHi & ~mask;
@@ -2069,10 +2069,10 @@ void r4k_helper_tlbp (void)
break;
}
}
- if (i == env->tlb->nb_tlb) {
+ if (i == env->tlb.nb_tlb) {
/* No match. Discard any shadow entries, if any of them match. */
- for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
- tlb = &env->tlb->mmu.r4k.tlb[i];
+ for (i = env->tlb.nb_tlb; i < env->tlb.tlb_in_use; i++) {
+ tlb = &env->tlb.mmu.r4k.tlb[i];
/* 1k pages are not supported. */
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
tag = env->CP0_EntryHi & ~mask;
@@ -2095,14 +2095,14 @@ void r4k_helper_tlbr (void)
int idx;
ASID = env->CP0_EntryHi & 0xFF;
- idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
- tlb = &env->tlb->mmu.r4k.tlb[idx];
+ idx = (env->CP0_Index & ~0x80000000) % env->tlb.nb_tlb;
+ tlb = &env->tlb.mmu.r4k.tlb[idx];
/* If this will change the current ASID, flush qemu's TLB. */
if (ASID != tlb->ASID)
cpu_mips_tlb_flush (env, 1);
- r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
+ r4k_mips_tlb_flush_extra(env, env->tlb.nb_tlb);
env->CP0_EntryHi = tlb->VPN | tlb->ASID;
env->CP0_PageMask = tlb->PageMask;
@@ -2114,22 +2114,22 @@ void r4k_helper_tlbr (void)
void helper_tlbwi(void)
{
- env->tlb->helper_tlbwi();
+ env->tlb.helper_tlbwi();
}
void helper_tlbwr(void)
{
- env->tlb->helper_tlbwr();
+ env->tlb.helper_tlbwr();
}
void helper_tlbp(void)
{
- env->tlb->helper_tlbp();
+ env->tlb.helper_tlbp();
}
void helper_tlbr(void)
{
- env->tlb->helper_tlbr();
+ env->tlb.helper_tlbr();
}
/* Specials */
diff --git a/target-mips/translate.c b/target-mips/translate.c
index c655a34..48a0108 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -5999,26 +5999,30 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
break;
case OPC_TLBWI:
opn = "tlbwi";
- if (!env->tlb->helper_tlbwi)
+ if (!env->tlb.helper_tlbwi) {
goto die;
+ }
gen_helper_tlbwi();
break;
case OPC_TLBWR:
opn = "tlbwr";
- if (!env->tlb->helper_tlbwr)
+ if (!env->tlb.helper_tlbwr) {
goto die;
+ }
gen_helper_tlbwr();
break;
case OPC_TLBP:
opn = "tlbp";
- if (!env->tlb->helper_tlbp)
+ if (!env->tlb.helper_tlbp) {
goto die;
+ }
gen_helper_tlbp();
break;
case OPC_TLBR:
opn = "tlbr";
- if (!env->tlb->helper_tlbr)
+ if (!env->tlb.helper_tlbr) {
goto die;
+ }
gen_helper_tlbr();
break;
case OPC_ERET:
@@ -12792,8 +12796,8 @@ void cpu_reset (CPUMIPSState *env)
env->CP0_ErrorEPC = env->active_tc.PC;
}
env->active_tc.PC = (int32_t)0xBFC00000;
- env->CP0_Random = env->tlb->nb_tlb - 1;
- env->tlb->tlb_in_use = env->tlb->nb_tlb;
+ env->CP0_Random = env->tlb.nb_tlb - 1;
+ env->tlb.tlb_in_use = env->tlb.nb_tlb;
env->CP0_Wired = 0;
env->CP0_EBase = 0x80000000 | (env->cpu_index & 0x3FF);
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 54fd1eb..0adb304 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -513,30 +513,28 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
#ifndef CONFIG_USER_ONLY
static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
{
- env->tlb->nb_tlb = 1;
- env->tlb->map_address = &no_mmu_map_address;
+ env->tlb.nb_tlb = 1;
+ env->tlb.map_address = &no_mmu_map_address;
}
static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
{
- env->tlb->nb_tlb = 1;
- env->tlb->map_address = &fixed_mmu_map_address;
+ env->tlb.nb_tlb = 1;
+ env->tlb.map_address = &fixed_mmu_map_address;
}
static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
{
- env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
- env->tlb->map_address = &r4k_map_address;
- env->tlb->helper_tlbwi = r4k_helper_tlbwi;
- env->tlb->helper_tlbwr = r4k_helper_tlbwr;
- env->tlb->helper_tlbp = r4k_helper_tlbp;
- env->tlb->helper_tlbr = r4k_helper_tlbr;
+ env->tlb.nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
+ env->tlb.map_address = &r4k_map_address;
+ env->tlb.helper_tlbwi = r4k_helper_tlbwi;
+ env->tlb.helper_tlbwr = r4k_helper_tlbwr;
+ env->tlb.helper_tlbp = r4k_helper_tlbp;
+ env->tlb.helper_tlbr = r4k_helper_tlbr;
}
static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
{
- env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
-
switch (def->mmu_type) {
case MMU_TYPE_NONE:
no_mmu_init(env, def);
@@ -581,7 +579,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
(0x00 << CP0MVPC0_PTC);
#if !defined(CONFIG_USER_ONLY)
/* Usermode has no TLB support */
- env->mvp.CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
+ env->mvp.CP0_MVPConf0 |= (env->tlb.nb_tlb << CP0MVPC0_PTLBE);
#endif
/* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 21/25] mips: bump migration version to 4
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (19 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 20/25] mips: make tlb an embedded struct instead of a pointer Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 22/25] vmstate: port mips cpu Juan Quintela
` (3 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori, Aurelien Jarno
bcond state was stored as int32, but it is target_ulong. Change migration state
to reflect that.
Signed-off-by: Juan Quintela <quintela@redhat.com>
CC: Aurelien Jarno <aurelien@aurel32.net>
---
target-mips/cpu.h | 2 +-
target-mips/machine.c | 10 ++++------
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 7ca751b..7810924 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -507,7 +507,7 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
#define cpu_signal_handler cpu_mips_signal_handler
#define cpu_list mips_cpu_list
-#define CPU_SAVE_VERSION 3
+#define CPU_SAVE_VERSION 4
/* MMU modes definitions. We carefully match the indices with our
hflags layout. */
diff --git a/target-mips/machine.c b/target-mips/machine.c
index a55fbb6..134dbd5 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -84,8 +84,7 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_sbe32s(f, &env->error_code);
qemu_put_be32s(f, &env->hflags);
qemu_put_betls(f, &env->btarget);
- i = env->bcond;
- qemu_put_sbe32s(f, &i);
+ qemu_put_betls(f, &env->bcond);
/* Save remaining CP1 registers */
qemu_put_sbe32s(f, &env->CP0_Index);
@@ -193,9 +192,9 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
CPUState *env = opaque;
int i;
- if (version_id != 3)
+ if (version_id != 4) {
return -EINVAL;
-
+ }
/* Load active TC */
load_tc(f, &env->active_tc);
@@ -236,8 +235,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_sbe32s(f, &env->error_code);
qemu_get_be32s(f, &env->hflags);
qemu_get_betls(f, &env->btarget);
- qemu_get_sbe32s(f, &i);
- env->bcond = i;
+ qemu_get_betls(f, &env->bcond);
/* Load remaining CP1 registers */
qemu_get_sbe32s(f, &env->CP0_Index);
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 22/25] vmstate: port mips cpu
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (20 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 21/25] mips: bump migration version to 4 Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 23/25] arm: save always 32 fpu registers Juan Quintela
` (2 subsequent siblings)
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori, Aurelien Jarno
Signed-off-by: Juan Quintela <quintela@redhat.com>
CC: Aurelien Jarno <aurelien@aurel32.net>
---
target-mips/cpu.h | 4 +-
target-mips/machine.c | 466 +++++++++++++++++++------------------------------
2 files changed, 185 insertions(+), 285 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 7810924..9bb7379 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -37,6 +37,8 @@ struct r4k_tlb_t {
uint_fast16_t D0:1;
uint_fast16_t D1:1;
target_ulong PFN[2];
+ uint8_t asid_vmstate;
+ uint16_t flags_vmstate;
};
#if !defined(CONFIG_USER_ONLY)
@@ -507,8 +509,6 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
#define cpu_signal_handler cpu_mips_signal_handler
#define cpu_list mips_cpu_list
-#define CPU_SAVE_VERSION 4
-
/* MMU modes definitions. We carefully match the indices with our
hflags layout. */
#define MMU_MODE0_SUFFIX _kernel
diff --git a/target-mips/machine.c b/target-mips/machine.c
index 134dbd5..1753f9a 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -3,304 +3,204 @@
#include "cpu.h"
-static void save_tc(QEMUFile *f, TCState *tc)
-{
- int i;
-
- /* Save active TC */
- for(i = 0; i < 32; i++)
- qemu_put_betls(f, &tc->gpr[i]);
- qemu_put_betls(f, &tc->PC);
- for(i = 0; i < MIPS_DSP_ACC; i++)
- qemu_put_betls(f, &tc->HI[i]);
- for(i = 0; i < MIPS_DSP_ACC; i++)
- qemu_put_betls(f, &tc->LO[i]);
- for(i = 0; i < MIPS_DSP_ACC; i++)
- qemu_put_betls(f, &tc->ACX[i]);
- qemu_put_betls(f, &tc->DSPControl);
- qemu_put_sbe32s(f, &tc->CP0_TCStatus);
- qemu_put_sbe32s(f, &tc->CP0_TCBind);
- qemu_put_betls(f, &tc->CP0_TCHalt);
- qemu_put_betls(f, &tc->CP0_TCContext);
- qemu_put_betls(f, &tc->CP0_TCSchedule);
- qemu_put_betls(f, &tc->CP0_TCScheFBack);
- qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus);
-}
+static const VMStateDescription vmstate_tc = {
+ .name = "tc",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
+ VMSTATE_UINTTL(PC, TCState),
+ VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
+ VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
+ VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
+ VMSTATE_UINTTL(DSPControl, TCState),
+ VMSTATE_INT32(CP0_TCStatus, TCState),
+ VMSTATE_INT32(CP0_TCBind, TCState),
+ VMSTATE_UINTTL(CP0_TCHalt, TCState),
+ VMSTATE_UINTTL(CP0_TCContext, TCState),
+ VMSTATE_UINTTL(CP0_TCSchedule, TCState),
+ VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
+ VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_fpu_reg = {
+ .name = "fpu_reg",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(d, fpr_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_fpu_context = {
+ .name = "fpu_context",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT_ARRAY(fpr, CPUMIPSFPUContext, 32, 0,
+ vmstate_fpu_reg, fpr_t),
+ VMSTATE_INT8(fp_status.float_detect_tininess, CPUMIPSFPUContext),
+ VMSTATE_INT8(fp_status.float_rounding_mode, CPUMIPSFPUContext),
+ VMSTATE_INT8(fp_status.float_exception_flags, CPUMIPSFPUContext),
+ VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
+ VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
+ VMSTATE_END_OF_LIST()
+ }
+};
-static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
+static void tlb_pre_save(void *opaque)
{
- int i;
-
- for(i = 0; i < 32; i++)
- qemu_put_be64s(f, &fpu->fpr[i].d);
- qemu_put_s8s(f, &fpu->fp_status.float_detect_tininess);
- qemu_put_s8s(f, &fpu->fp_status.float_rounding_mode);
- qemu_put_s8s(f, &fpu->fp_status.float_exception_flags);
- qemu_put_be32s(f, &fpu->fcr0);
- qemu_put_be32s(f, &fpu->fcr31);
+ r4k_tlb_t *tlb = opaque;
+
+ tlb->asid_vmstate = tlb->ASID;
+ tlb->flags_vmstate = ((tlb->G << 10) |
+ (tlb->C0 << 7) |
+ (tlb->C1 << 4) |
+ (tlb->V0 << 3) |
+ (tlb->V1 << 2) |
+ (tlb->D0 << 1) |
+ (tlb->D1 << 0));
}
-void cpu_save(QEMUFile *f, void *opaque)
+static int tlb_post_load(void *opaque, int version_id)
{
- CPUState *env = opaque;
- int i;
-
- /* Save active TC */
- save_tc(f, &env->active_tc);
-
- /* Save active FPU */
- save_fpu(f, &env->active_fpu);
-
- /* Save MVP */
- qemu_put_sbe32s(f, &env->mvp.CP0_MVPControl);
- qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf0);
- qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf1);
-
- /* Save TLB */
- qemu_put_be32s(f, &env->tlb.nb_tlb);
- qemu_put_be32s(f, &env->tlb.tlb_in_use);
- for(i = 0; i < MIPS_TLB_MAX; i++) {
- uint16_t flags = ((env->tlb.mmu.r4k.tlb[i].G << 10) |
- (env->tlb.mmu.r4k.tlb[i].C0 << 7) |
- (env->tlb.mmu.r4k.tlb[i].C1 << 4) |
- (env->tlb.mmu.r4k.tlb[i].V0 << 3) |
- (env->tlb.mmu.r4k.tlb[i].V1 << 2) |
- (env->tlb.mmu.r4k.tlb[i].D0 << 1) |
- (env->tlb.mmu.r4k.tlb[i].D1 << 0));
- uint8_t asid;
-
- qemu_put_betls(f, &env->tlb.mmu.r4k.tlb[i].VPN);
- qemu_put_be32s(f, &env->tlb.mmu.r4k.tlb[i].PageMask);
- asid = env->tlb.mmu.r4k.tlb[i].ASID;
- qemu_put_8s(f, &asid);
- qemu_put_be16s(f, &flags);
- qemu_put_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[0]);
- qemu_put_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[1]);
- }
-
- /* Save CPU metastate */
- qemu_put_be32s(f, &env->current_tc);
- qemu_put_be32s(f, &env->current_fpu);
- qemu_put_sbe32s(f, &env->error_code);
- qemu_put_be32s(f, &env->hflags);
- qemu_put_betls(f, &env->btarget);
- qemu_put_betls(f, &env->bcond);
-
- /* Save remaining CP1 registers */
- qemu_put_sbe32s(f, &env->CP0_Index);
- qemu_put_sbe32s(f, &env->CP0_Random);
- qemu_put_sbe32s(f, &env->CP0_VPEControl);
- qemu_put_sbe32s(f, &env->CP0_VPEConf0);
- qemu_put_sbe32s(f, &env->CP0_VPEConf1);
- qemu_put_betls(f, &env->CP0_YQMask);
- qemu_put_betls(f, &env->CP0_VPESchedule);
- qemu_put_betls(f, &env->CP0_VPEScheFBack);
- qemu_put_sbe32s(f, &env->CP0_VPEOpt);
- qemu_put_betls(f, &env->CP0_EntryLo0);
- qemu_put_betls(f, &env->CP0_EntryLo1);
- qemu_put_betls(f, &env->CP0_Context);
- qemu_put_sbe32s(f, &env->CP0_PageMask);
- qemu_put_sbe32s(f, &env->CP0_PageGrain);
- qemu_put_sbe32s(f, &env->CP0_Wired);
- qemu_put_sbe32s(f, &env->CP0_SRSConf0);
- qemu_put_sbe32s(f, &env->CP0_SRSConf1);
- qemu_put_sbe32s(f, &env->CP0_SRSConf2);
- qemu_put_sbe32s(f, &env->CP0_SRSConf3);
- qemu_put_sbe32s(f, &env->CP0_SRSConf4);
- qemu_put_sbe32s(f, &env->CP0_HWREna);
- qemu_put_betls(f, &env->CP0_BadVAddr);
- qemu_put_sbe32s(f, &env->CP0_Count);
- qemu_put_betls(f, &env->CP0_EntryHi);
- qemu_put_sbe32s(f, &env->CP0_Compare);
- qemu_put_sbe32s(f, &env->CP0_Status);
- qemu_put_sbe32s(f, &env->CP0_IntCtl);
- qemu_put_sbe32s(f, &env->CP0_SRSCtl);
- qemu_put_sbe32s(f, &env->CP0_SRSMap);
- qemu_put_sbe32s(f, &env->CP0_Cause);
- qemu_put_betls(f, &env->CP0_EPC);
- qemu_put_sbe32s(f, &env->CP0_PRid);
- qemu_put_sbe32s(f, &env->CP0_EBase);
- qemu_put_sbe32s(f, &env->CP0_Config0);
- qemu_put_sbe32s(f, &env->CP0_Config1);
- qemu_put_sbe32s(f, &env->CP0_Config2);
- qemu_put_sbe32s(f, &env->CP0_Config3);
- qemu_put_sbe32s(f, &env->CP0_Config6);
- qemu_put_sbe32s(f, &env->CP0_Config7);
- qemu_put_betls(f, &env->lladdr);
- for(i = 0; i < 8; i++)
- qemu_put_betls(f, &env->CP0_WatchLo[i]);
- for(i = 0; i < 8; i++)
- qemu_put_sbe32s(f, &env->CP0_WatchHi[i]);
- qemu_put_betls(f, &env->CP0_XContext);
- qemu_put_sbe32s(f, &env->CP0_Framemask);
- qemu_put_sbe32s(f, &env->CP0_Debug);
- qemu_put_betls(f, &env->CP0_DEPC);
- qemu_put_sbe32s(f, &env->CP0_Performance0);
- qemu_put_sbe32s(f, &env->CP0_TagLo);
- qemu_put_sbe32s(f, &env->CP0_DataLo);
- qemu_put_sbe32s(f, &env->CP0_TagHi);
- qemu_put_sbe32s(f, &env->CP0_DataHi);
- qemu_put_betls(f, &env->CP0_ErrorEPC);
- qemu_put_sbe32s(f, &env->CP0_DESAVE);
-
- /* Save inactive TC state */
- for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)
- save_tc(f, &env->tcs[i]);
- for (i = 0; i < MIPS_FPU_MAX; i++)
- save_fpu(f, &env->fpus[i]);
+ r4k_tlb_t *tlb = opaque;
+
+ tlb->ASID = tlb->asid_vmstate;
+ tlb->G = (tlb->flags_vmstate >> 10) & 1;
+ tlb->C0 = (tlb->flags_vmstate >> 7) & 3;
+ tlb->C1 = (tlb->flags_vmstate >> 4) & 3;
+ tlb->V0 = (tlb->flags_vmstate >> 3) & 1;
+ tlb->V1 = (tlb->flags_vmstate >> 2) & 1;
+ tlb->D0 = (tlb->flags_vmstate >> 1) & 1;
+ tlb->D1 = (tlb->flags_vmstate >> 0) & 1;
+ return 0;
}
-static void load_tc(QEMUFile *f, TCState *tc)
-{
- int i;
-
- /* Save active TC */
- for(i = 0; i < 32; i++)
- qemu_get_betls(f, &tc->gpr[i]);
- qemu_get_betls(f, &tc->PC);
- for(i = 0; i < MIPS_DSP_ACC; i++)
- qemu_get_betls(f, &tc->HI[i]);
- for(i = 0; i < MIPS_DSP_ACC; i++)
- qemu_get_betls(f, &tc->LO[i]);
- for(i = 0; i < MIPS_DSP_ACC; i++)
- qemu_get_betls(f, &tc->ACX[i]);
- qemu_get_betls(f, &tc->DSPControl);
- qemu_get_sbe32s(f, &tc->CP0_TCStatus);
- qemu_get_sbe32s(f, &tc->CP0_TCBind);
- qemu_get_betls(f, &tc->CP0_TCHalt);
- qemu_get_betls(f, &tc->CP0_TCContext);
- qemu_get_betls(f, &tc->CP0_TCSchedule);
- qemu_get_betls(f, &tc->CP0_TCScheFBack);
- qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus);
-}
+static const VMStateDescription vmstate_tlb = {
+ .name = "tlb",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .pre_save = tlb_pre_save,
+ .post_load = tlb_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(VPN, r4k_tlb_t),
+ VMSTATE_UINT32(PageMask, r4k_tlb_t),
+ VMSTATE_UINT8(asid_vmstate, r4k_tlb_t),
+ VMSTATE_UINT16(flags_vmstate, r4k_tlb_t),
+ VMSTATE_UINTTL_ARRAY(PFN, r4k_tlb_t, 2),
+ VMSTATE_END_OF_LIST()
+ }
+};
-static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
+static void cpu_pre_save(void *opaque)
{
- int i;
-
- for(i = 0; i < 32; i++)
- qemu_get_be64s(f, &fpu->fpr[i].d);
- qemu_get_s8s(f, &fpu->fp_status.float_detect_tininess);
- qemu_get_s8s(f, &fpu->fp_status.float_rounding_mode);
- qemu_get_s8s(f, &fpu->fp_status.float_exception_flags);
- qemu_get_be32s(f, &fpu->fcr0);
- qemu_get_be32s(f, &fpu->fcr31);
+ CPUState *env = opaque;
+ env = env;
}
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
+static int cpu_post_load(void *opaque, int version_id)
{
CPUState *env = opaque;
- int i;
-
- if (version_id != 4) {
- return -EINVAL;
- }
- /* Load active TC */
- load_tc(f, &env->active_tc);
-
- /* Load active FPU */
- load_fpu(f, &env->active_fpu);
-
- /* Load MVP */
- qemu_get_sbe32s(f, &env->mvp.CP0_MVPControl);
- qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf0);
- qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf1);
-
- /* Load TLB */
- qemu_get_be32s(f, &env->tlb.nb_tlb);
- qemu_get_be32s(f, &env->tlb.tlb_in_use);
- for(i = 0; i < MIPS_TLB_MAX; i++) {
- uint16_t flags;
- uint8_t asid;
-
- qemu_get_betls(f, &env->tlb.mmu.r4k.tlb[i].VPN);
- qemu_get_be32s(f, &env->tlb.mmu.r4k.tlb[i].PageMask);
- qemu_get_8s(f, &asid);
- env->tlb.mmu.r4k.tlb[i].ASID = asid;
- qemu_get_be16s(f, &flags);
- env->tlb.mmu.r4k.tlb[i].G = (flags >> 10) & 1;
- env->tlb.mmu.r4k.tlb[i].C0 = (flags >> 7) & 3;
- env->tlb.mmu.r4k.tlb[i].C1 = (flags >> 4) & 3;
- env->tlb.mmu.r4k.tlb[i].V0 = (flags >> 3) & 1;
- env->tlb.mmu.r4k.tlb[i].V1 = (flags >> 2) & 1;
- env->tlb.mmu.r4k.tlb[i].D0 = (flags >> 1) & 1;
- env->tlb.mmu.r4k.tlb[i].D1 = (flags >> 0) & 1;
- qemu_get_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[0]);
- qemu_get_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[1]);
- }
-
- /* Load CPU metastate */
- qemu_get_be32s(f, &env->current_tc);
- qemu_get_be32s(f, &env->current_fpu);
- qemu_get_sbe32s(f, &env->error_code);
- qemu_get_be32s(f, &env->hflags);
- qemu_get_betls(f, &env->btarget);
- qemu_get_betls(f, &env->bcond);
-
- /* Load remaining CP1 registers */
- qemu_get_sbe32s(f, &env->CP0_Index);
- qemu_get_sbe32s(f, &env->CP0_Random);
- qemu_get_sbe32s(f, &env->CP0_VPEControl);
- qemu_get_sbe32s(f, &env->CP0_VPEConf0);
- qemu_get_sbe32s(f, &env->CP0_VPEConf1);
- qemu_get_betls(f, &env->CP0_YQMask);
- qemu_get_betls(f, &env->CP0_VPESchedule);
- qemu_get_betls(f, &env->CP0_VPEScheFBack);
- qemu_get_sbe32s(f, &env->CP0_VPEOpt);
- qemu_get_betls(f, &env->CP0_EntryLo0);
- qemu_get_betls(f, &env->CP0_EntryLo1);
- qemu_get_betls(f, &env->CP0_Context);
- qemu_get_sbe32s(f, &env->CP0_PageMask);
- qemu_get_sbe32s(f, &env->CP0_PageGrain);
- qemu_get_sbe32s(f, &env->CP0_Wired);
- qemu_get_sbe32s(f, &env->CP0_SRSConf0);
- qemu_get_sbe32s(f, &env->CP0_SRSConf1);
- qemu_get_sbe32s(f, &env->CP0_SRSConf2);
- qemu_get_sbe32s(f, &env->CP0_SRSConf3);
- qemu_get_sbe32s(f, &env->CP0_SRSConf4);
- qemu_get_sbe32s(f, &env->CP0_HWREna);
- qemu_get_betls(f, &env->CP0_BadVAddr);
- qemu_get_sbe32s(f, &env->CP0_Count);
- qemu_get_betls(f, &env->CP0_EntryHi);
- qemu_get_sbe32s(f, &env->CP0_Compare);
- qemu_get_sbe32s(f, &env->CP0_Status);
- qemu_get_sbe32s(f, &env->CP0_IntCtl);
- qemu_get_sbe32s(f, &env->CP0_SRSCtl);
- qemu_get_sbe32s(f, &env->CP0_SRSMap);
- qemu_get_sbe32s(f, &env->CP0_Cause);
- qemu_get_betls(f, &env->CP0_EPC);
- qemu_get_sbe32s(f, &env->CP0_PRid);
- qemu_get_sbe32s(f, &env->CP0_EBase);
- qemu_get_sbe32s(f, &env->CP0_Config0);
- qemu_get_sbe32s(f, &env->CP0_Config1);
- qemu_get_sbe32s(f, &env->CP0_Config2);
- qemu_get_sbe32s(f, &env->CP0_Config3);
- qemu_get_sbe32s(f, &env->CP0_Config6);
- qemu_get_sbe32s(f, &env->CP0_Config7);
- qemu_get_betls(f, &env->lladdr);
- for(i = 0; i < 8; i++)
- qemu_get_betls(f, &env->CP0_WatchLo[i]);
- for(i = 0; i < 8; i++)
- qemu_get_sbe32s(f, &env->CP0_WatchHi[i]);
- qemu_get_betls(f, &env->CP0_XContext);
- qemu_get_sbe32s(f, &env->CP0_Framemask);
- qemu_get_sbe32s(f, &env->CP0_Debug);
- qemu_get_betls(f, &env->CP0_DEPC);
- qemu_get_sbe32s(f, &env->CP0_Performance0);
- qemu_get_sbe32s(f, &env->CP0_TagLo);
- qemu_get_sbe32s(f, &env->CP0_DataLo);
- qemu_get_sbe32s(f, &env->CP0_TagHi);
- qemu_get_sbe32s(f, &env->CP0_DataHi);
- qemu_get_betls(f, &env->CP0_ErrorEPC);
- qemu_get_sbe32s(f, &env->CP0_DESAVE);
-
- /* Load inactive TC state */
- for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)
- load_tc(f, &env->tcs[i]);
- for (i = 0; i < MIPS_FPU_MAX; i++)
- load_fpu(f, &env->fpus[i]);
/* XXX: ensure compatiblity for halted bit ? */
tlb_flush(env, 1);
return 0;
}
+
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .version_id = 4,
+ .minimum_version_id = 4,
+ .minimum_version_id_old = 4,
+ .pre_save = cpu_pre_save,
+ .post_load = cpu_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT(active_tc, CPUState, 0, vmstate_tc, TCState),
+ VMSTATE_STRUCT(active_fpu, CPUState, 0, vmstate_fpu_context,
+ CPUMIPSFPUContext),
+ /* Save MVP */
+ VMSTATE_INT32(mvp.CP0_MVPControl, CPUState),
+ VMSTATE_INT32(mvp.CP0_MVPConf0, CPUState),
+ VMSTATE_INT32(mvp.CP0_MVPConf1, CPUState),
+ /* Save TLB */
+ VMSTATE_UINT32(tlb.nb_tlb, CPUState),
+ VMSTATE_UINT32(tlb.tlb_in_use, CPUState),
+ VMSTATE_STRUCT_ARRAY(tlb.mmu.r4k.tlb, CPUState, MIPS_TLB_MAX, 0,
+ vmstate_tlb, r4k_tlb_t),
+ /* Save CPU metastate */
+ VMSTATE_UINT32(current_tc, CPUState),
+ VMSTATE_UINT32(current_fpu, CPUState),
+ VMSTATE_INT32(error_code, CPUState),
+ VMSTATE_UINT32(hflags, CPUState),
+ VMSTATE_UINTTL(btarget, CPUState),
+ VMSTATE_UINTTL(bcond, CPUState),
+ /* Save remaining CP1 registers */
+ VMSTATE_INT32(CP0_Index, CPUState),
+ VMSTATE_INT32(CP0_Random, CPUState),
+ VMSTATE_INT32(CP0_VPEControl, CPUState),
+ VMSTATE_INT32(CP0_VPEConf0, CPUState),
+ VMSTATE_INT32(CP0_VPEConf1, CPUState),
+ VMSTATE_UINTTL(CP0_YQMask, CPUState),
+ VMSTATE_UINTTL(CP0_VPESchedule, CPUState),
+ VMSTATE_UINTTL(CP0_VPEScheFBack, CPUState),
+ VMSTATE_INT32(CP0_VPEOpt, CPUState),
+ VMSTATE_UINTTL(CP0_EntryLo0, CPUState),
+ VMSTATE_UINTTL(CP0_EntryLo1, CPUState),
+ VMSTATE_UINTTL(CP0_Context, CPUState),
+ VMSTATE_INT32(CP0_PageMask, CPUState),
+ VMSTATE_INT32(CP0_PageGrain, CPUState),
+ VMSTATE_INT32(CP0_Wired, CPUState),
+ VMSTATE_INT32(CP0_SRSConf0, CPUState),
+ VMSTATE_INT32(CP0_SRSConf1, CPUState),
+ VMSTATE_INT32(CP0_SRSConf2, CPUState),
+ VMSTATE_INT32(CP0_SRSConf3, CPUState),
+ VMSTATE_INT32(CP0_SRSConf4, CPUState),
+ VMSTATE_INT32(CP0_HWREna, CPUState),
+ VMSTATE_UINTTL(CP0_BadVAddr, CPUState),
+ VMSTATE_INT32(CP0_Count, CPUState),
+ VMSTATE_UINTTL(CP0_EntryHi, CPUState),
+ VMSTATE_INT32(CP0_Compare, CPUState),
+ VMSTATE_INT32(CP0_Status, CPUState),
+ VMSTATE_INT32(CP0_IntCtl, CPUState),
+ VMSTATE_INT32(CP0_SRSCtl, CPUState),
+ VMSTATE_INT32(CP0_SRSMap, CPUState),
+ VMSTATE_INT32(CP0_Cause, CPUState),
+ VMSTATE_UINTTL(CP0_EPC, CPUState),
+ VMSTATE_INT32(CP0_PRid, CPUState),
+ VMSTATE_INT32(CP0_EBase, CPUState),
+ VMSTATE_INT32(CP0_Config0, CPUState),
+ VMSTATE_INT32(CP0_Config1, CPUState),
+ VMSTATE_INT32(CP0_Config2, CPUState),
+ VMSTATE_INT32(CP0_Config3, CPUState),
+ VMSTATE_INT32(CP0_Config6, CPUState),
+ VMSTATE_INT32(CP0_Config7, CPUState),
+ VMSTATE_UINTTL(lladdr, CPUState),
+ VMSTATE_UINTTL_ARRAY(CP0_WatchLo, CPUState, 8),
+ VMSTATE_INT32_ARRAY(CP0_WatchHi, CPUState, 8),
+ VMSTATE_UINTTL(CP0_XContext, CPUState),
+ VMSTATE_INT32(CP0_Framemask, CPUState),
+ VMSTATE_INT32(CP0_Debug, CPUState),
+ VMSTATE_UINTTL(CP0_DEPC, CPUState),
+ VMSTATE_INT32(CP0_Performance0, CPUState),
+ VMSTATE_INT32(CP0_TagLo, CPUState),
+ VMSTATE_INT32(CP0_DataLo, CPUState),
+ VMSTATE_INT32(CP0_TagHi, CPUState),
+ VMSTATE_INT32(CP0_DataHi, CPUState),
+ VMSTATE_UINTTL(CP0_ErrorEPC, CPUState),
+ VMSTATE_INT32(CP0_DESAVE, CPUState),
+ /* Save inactive TC state */
+ VMSTATE_STRUCT_ARRAY(tcs, CPUState, MIPS_SHADOW_SET_MAX, 0,
+ vmstate_tc, TCState),
+ VMSTATE_STRUCT_ARRAY(fpus, CPUState, MIPS_FPU_MAX, 0,
+ vmstate_fpu_context, CPUMIPSFPUContext),
+ VMSTATE_END_OF_LIST()
+ },
+};
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 23/25] arm: save always 32 fpu registers
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (21 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 22/25] vmstate: port mips cpu Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 24/25] vmstate: port arm cpu Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 25/25] vmstate: all cpus converted Juan Quintela
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, aliguori, Paul Brook
This way, we fix a bug (we were overwritten the 16 first registers on
load), and we don't need to check for ARM_FEATUR_VPF3, we always send
the 32 registers.
Signed-off-by: Juan Quintela <quintela@redhat.com>
CC: Paul Brook <paul@codesourcery.com>
CC: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.h | 2 +-
target-arm/machine.c | 22 ++--------------------
2 files changed, 3 insertions(+), 21 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 6ab780d..f6d9436 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -446,7 +446,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list
-#define CPU_SAVE_VERSION 4
+#define CPU_SAVE_VERSION 5
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 7d4fc54..3a3b325 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -60,7 +60,7 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, env->features);
if (arm_feature(env, ARM_FEATURE_VFP)) {
- for (i = 0; i < 16; i++) {
+ for (i = 0; i < 32; i++) {
CPU_DoubleU u;
u.d = env->vfp.regs[i];
qemu_put_be32(f, u.l.upper);
@@ -73,15 +73,6 @@ void cpu_save(QEMUFile *f, void *opaque)
/* TODO: Should use proper FPSCR access functions. */
qemu_put_be32(f, env->vfp.vec_len);
qemu_put_be32(f, env->vfp.vec_stride);
-
- if (arm_feature(env, ARM_FEATURE_VFP3)) {
- for (i = 16; i < 32; i++) {
- CPU_DoubleU u;
- u.d = env->vfp.regs[i];
- qemu_put_be32(f, u.l.upper);
- qemu_put_be32(f, u.l.lower);
- }
- }
}
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
@@ -174,7 +165,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
env->features = qemu_get_be32(f);
if (arm_feature(env, ARM_FEATURE_VFP)) {
- for (i = 0; i < 16; i++) {
+ for (i = 0; i < 32; i++) {
CPU_DoubleU u;
u.l.upper = qemu_get_be32(f);
u.l.lower = qemu_get_be32(f);
@@ -187,15 +178,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
/* TODO: Should use proper FPSCR access functions. */
env->vfp.vec_len = qemu_get_be32(f);
env->vfp.vec_stride = qemu_get_be32(f);
-
- if (arm_feature(env, ARM_FEATURE_VFP3)) {
- for (i = 0; i < 16; i++) {
- CPU_DoubleU u;
- u.l.upper = qemu_get_be32(f);
- u.l.lower = qemu_get_be32(f);
- env->vfp.regs[i] = u.d;
- }
- }
}
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 24/25] vmstate: port arm cpu
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (22 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 23/25] arm: save always 32 fpu registers Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
2011-10-25 18:27 ` Paul Brook
2011-10-25 14:00 ` [Qemu-devel] [PATCH 25/25] vmstate: all cpus converted Juan Quintela
24 siblings, 1 reply; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: Peter Maydell, aliguori, Paul Brook
Use one subsection for each feature. This means that we don't need to
bump the version field each time that a new feature gets introduced.
Introduce cpsr_vmstate field, as I am not sure if I can "use"
uncached_cpsr for saving state.
Signed-off-by: Juan Quintela <quintela@redhat.com>
CC: Paul Brook <paul@codesourcery.com>
CC: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/cpu.h | 4 +-
target-arm/machine.c | 332 ++++++++++++++++++++++---------------------------
2 files changed, 151 insertions(+), 185 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index f6d9436..ec02f85 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -228,6 +228,8 @@ typedef struct CPUARMState {
} cp[15];
void *nvic;
const struct arm_boot_info *boot_info;
+
+ uint32_t cpsr_vmstate;
} CPUARMState;
CPUARMState *cpu_arm_init(const char *cpu_model);
@@ -446,8 +448,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list
-#define CPU_SAVE_VERSION 5
-
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 3a3b325..b97b06b 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -1,207 +1,173 @@
#include "hw/hw.h"
#include "hw/boards.h"
-void cpu_save(QEMUFile *f, void *opaque)
+static bool feature_vfp_needed(void *opaque)
{
- int i;
- CPUARMState *env = (CPUARMState *)opaque;
+ CPUState *env = opaque;
- for (i = 0; i < 16; i++) {
- qemu_put_be32(f, env->regs[i]);
- }
- qemu_put_be32(f, cpsr_read(env));
- qemu_put_be32(f, env->spsr);
- for (i = 0; i < 6; i++) {
- qemu_put_be32(f, env->banked_spsr[i]);
- qemu_put_be32(f, env->banked_r13[i]);
- qemu_put_be32(f, env->banked_r14[i]);
- }
- for (i = 0; i < 5; i++) {
- qemu_put_be32(f, env->usr_regs[i]);
- qemu_put_be32(f, env->fiq_regs[i]);
- }
- qemu_put_be32(f, env->cp15.c0_cpuid);
- qemu_put_be32(f, env->cp15.c0_cachetype);
- qemu_put_be32(f, env->cp15.c0_cssel);
- qemu_put_be32(f, env->cp15.c1_sys);
- qemu_put_be32(f, env->cp15.c1_coproc);
- qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
- qemu_put_be32(f, env->cp15.c2_base0);
- qemu_put_be32(f, env->cp15.c2_base1);
- qemu_put_be32(f, env->cp15.c2_control);
- qemu_put_be32(f, env->cp15.c2_mask);
- qemu_put_be32(f, env->cp15.c2_base_mask);
- qemu_put_be32(f, env->cp15.c2_data);
- qemu_put_be32(f, env->cp15.c2_insn);
- qemu_put_be32(f, env->cp15.c3);
- qemu_put_be32(f, env->cp15.c5_insn);
- qemu_put_be32(f, env->cp15.c5_data);
- for (i = 0; i < 8; i++) {
- qemu_put_be32(f, env->cp15.c6_region[i]);
- }
- qemu_put_be32(f, env->cp15.c6_insn);
- qemu_put_be32(f, env->cp15.c6_data);
- qemu_put_be32(f, env->cp15.c7_par);
- qemu_put_be32(f, env->cp15.c9_insn);
- qemu_put_be32(f, env->cp15.c9_data);
- qemu_put_be32(f, env->cp15.c9_pmcr);
- qemu_put_be32(f, env->cp15.c9_pmcnten);
- qemu_put_be32(f, env->cp15.c9_pmovsr);
- qemu_put_be32(f, env->cp15.c9_pmxevtyper);
- qemu_put_be32(f, env->cp15.c9_pmuserenr);
- qemu_put_be32(f, env->cp15.c9_pminten);
- qemu_put_be32(f, env->cp15.c13_fcse);
- qemu_put_be32(f, env->cp15.c13_context);
- qemu_put_be32(f, env->cp15.c13_tls1);
- qemu_put_be32(f, env->cp15.c13_tls2);
- qemu_put_be32(f, env->cp15.c13_tls3);
- qemu_put_be32(f, env->cp15.c15_cpar);
-
- qemu_put_be32(f, env->features);
-
- if (arm_feature(env, ARM_FEATURE_VFP)) {
- for (i = 0; i < 32; i++) {
- CPU_DoubleU u;
- u.d = env->vfp.regs[i];
- qemu_put_be32(f, u.l.upper);
- qemu_put_be32(f, u.l.lower);
- }
- for (i = 0; i < 16; i++) {
- qemu_put_be32(f, env->vfp.xregs[i]);
- }
+ return arm_feature(env, ARM_FEATURE_VFP);
+}
+static const VMStateDescription vmstate_feature_vfp = {
+ .name = "feature_vfp",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_FLOAT64_ARRAY(vfp.regs, CPUState, 32),
+ VMSTATE_UINT32_ARRAY(vfp.xregs, CPUState, 16),
/* TODO: Should use proper FPSCR access functions. */
- qemu_put_be32(f, env->vfp.vec_len);
- qemu_put_be32(f, env->vfp.vec_stride);
+ VMSTATE_INT32(vfp.vec_len, CPUState),
+ VMSTATE_INT32(vfp.vec_stride, CPUState),
+ VMSTATE_END_OF_LIST()
}
+};
- if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
- for (i = 0; i < 16; i++) {
- qemu_put_be64(f, env->iwmmxt.regs[i]);
- }
- for (i = 0; i < 16; i++) {
- qemu_put_be32(f, env->iwmmxt.cregs[i]);
- }
- }
+static bool feature_iwmmxt_needed(void *opaque)
+{
+ CPUState *env = opaque;
- if (arm_feature(env, ARM_FEATURE_M)) {
- qemu_put_be32(f, env->v7m.other_sp);
- qemu_put_be32(f, env->v7m.vecbase);
- qemu_put_be32(f, env->v7m.basepri);
- qemu_put_be32(f, env->v7m.control);
- qemu_put_be32(f, env->v7m.current_sp);
- qemu_put_be32(f, env->v7m.exception);
- }
+ return arm_feature(env, ARM_FEATURE_IWMMXT);
+}
- if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
- qemu_put_be32(f, env->teecr);
- qemu_put_be32(f, env->teehbr);
+static const VMStateDescription vmstate_feature_iwmmxt = {
+ .name = "feature_iwmmxt",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64_ARRAY(iwmmxt.regs, CPUState, 16),
+ VMSTATE_UINT32_ARRAY(iwmmxt.cregs, CPUState, 16),
+ VMSTATE_END_OF_LIST()
}
-}
+};
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
+static bool feature_m_needed(void *opaque)
{
- CPUARMState *env = (CPUARMState *)opaque;
- int i;
- uint32_t val;
+ CPUState *env = opaque;
- if (version_id != CPU_SAVE_VERSION)
- return -EINVAL;
+ return arm_feature(env, ARM_FEATURE_M);
+}
- for (i = 0; i < 16; i++) {
- env->regs[i] = qemu_get_be32(f);
- }
- val = qemu_get_be32(f);
- /* Avoid mode switch when restoring CPSR. */
- env->uncached_cpsr = val & CPSR_M;
- cpsr_write(env, val, 0xffffffff);
- env->spsr = qemu_get_be32(f);
- for (i = 0; i < 6; i++) {
- env->banked_spsr[i] = qemu_get_be32(f);
- env->banked_r13[i] = qemu_get_be32(f);
- env->banked_r14[i] = qemu_get_be32(f);
- }
- for (i = 0; i < 5; i++) {
- env->usr_regs[i] = qemu_get_be32(f);
- env->fiq_regs[i] = qemu_get_be32(f);
- }
- env->cp15.c0_cpuid = qemu_get_be32(f);
- env->cp15.c0_cachetype = qemu_get_be32(f);
- env->cp15.c0_cssel = qemu_get_be32(f);
- env->cp15.c1_sys = qemu_get_be32(f);
- env->cp15.c1_coproc = qemu_get_be32(f);
- env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
- env->cp15.c2_base0 = qemu_get_be32(f);
- env->cp15.c2_base1 = qemu_get_be32(f);
- env->cp15.c2_control = qemu_get_be32(f);
- env->cp15.c2_mask = qemu_get_be32(f);
- env->cp15.c2_base_mask = qemu_get_be32(f);
- env->cp15.c2_data = qemu_get_be32(f);
- env->cp15.c2_insn = qemu_get_be32(f);
- env->cp15.c3 = qemu_get_be32(f);
- env->cp15.c5_insn = qemu_get_be32(f);
- env->cp15.c5_data = qemu_get_be32(f);
- for (i = 0; i < 8; i++) {
- env->cp15.c6_region[i] = qemu_get_be32(f);
- }
- env->cp15.c6_insn = qemu_get_be32(f);
- env->cp15.c6_data = qemu_get_be32(f);
- env->cp15.c7_par = qemu_get_be32(f);
- env->cp15.c9_insn = qemu_get_be32(f);
- env->cp15.c9_data = qemu_get_be32(f);
- env->cp15.c9_pmcr = qemu_get_be32(f);
- env->cp15.c9_pmcnten = qemu_get_be32(f);
- env->cp15.c9_pmovsr = qemu_get_be32(f);
- env->cp15.c9_pmxevtyper = qemu_get_be32(f);
- env->cp15.c9_pmuserenr = qemu_get_be32(f);
- env->cp15.c9_pminten = qemu_get_be32(f);
- env->cp15.c13_fcse = qemu_get_be32(f);
- env->cp15.c13_context = qemu_get_be32(f);
- env->cp15.c13_tls1 = qemu_get_be32(f);
- env->cp15.c13_tls2 = qemu_get_be32(f);
- env->cp15.c13_tls3 = qemu_get_be32(f);
- env->cp15.c15_cpar = qemu_get_be32(f);
-
- env->features = qemu_get_be32(f);
-
- if (arm_feature(env, ARM_FEATURE_VFP)) {
- for (i = 0; i < 32; i++) {
- CPU_DoubleU u;
- u.l.upper = qemu_get_be32(f);
- u.l.lower = qemu_get_be32(f);
- env->vfp.regs[i] = u.d;
- }
- for (i = 0; i < 16; i++) {
- env->vfp.xregs[i] = qemu_get_be32(f);
- }
+static const VMStateDescription vmstate_feature_m = {
+ .name = "feature_m",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(v7m.other_sp, CPUState),
+ VMSTATE_UINT32(v7m.vecbase, CPUState),
+ VMSTATE_UINT32(v7m.basepri, CPUState),
+ VMSTATE_UINT32(v7m.control, CPUState),
+ VMSTATE_INT32(v7m.current_sp, CPUState),
+ VMSTATE_INT32(v7m.exception, CPUState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static bool feature_thumb2ee_needed(void *opaque)
+{
+ CPUState *env = opaque;
- /* TODO: Should use proper FPSCR access functions. */
- env->vfp.vec_len = qemu_get_be32(f);
- env->vfp.vec_stride = qemu_get_be32(f);
- }
+ return arm_feature(env, ARM_FEATURE_THUMB2EE);
+}
- if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
- for (i = 0; i < 16; i++) {
- env->iwmmxt.regs[i] = qemu_get_be64(f);
- }
- for (i = 0; i < 16; i++) {
- env->iwmmxt.cregs[i] = qemu_get_be32(f);
- }
+static const VMStateDescription vmstate_feature_thumb2ee = {
+ .name = "feature_thumb2ee",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(teecr, CPUState),
+ VMSTATE_UINT32(teehbr, CPUState),
+ VMSTATE_END_OF_LIST()
}
+};
- if (arm_feature(env, ARM_FEATURE_M)) {
- env->v7m.other_sp = qemu_get_be32(f);
- env->v7m.vecbase = qemu_get_be32(f);
- env->v7m.basepri = qemu_get_be32(f);
- env->v7m.control = qemu_get_be32(f);
- env->v7m.current_sp = qemu_get_be32(f);
- env->v7m.exception = qemu_get_be32(f);
- }
+static void cpu_pre_save(void *opaque)
+{
+ CPUState *env = opaque;
- if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
- env->teecr = qemu_get_be32(f);
- env->teehbr = qemu_get_be32(f);
- }
+ env->cpsr_vmstate = cpsr_read(env);
+}
+static int cpu_post_load(void *opaque, int version_id)
+{
+ CPUState *env = opaque;
+
+ env->uncached_cpsr = env->cpsr_vmstate & CPSR_M;
+ cpsr_write(env, env->cpsr_vmstate, 0xffffffff);
return 0;
}
+
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .version_id = 6,
+ .minimum_version_id = 6,
+ .minimum_version_id_old = 6,
+ .pre_save = cpu_pre_save,
+ .post_load = cpu_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, CPUState, 16),
+ VMSTATE_UINT32(cpsr_vmstate, CPUState),
+ VMSTATE_UINT32(spsr, CPUState),
+ VMSTATE_UINT32_ARRAY(banked_spsr, CPUState, 6),
+ VMSTATE_UINT32_ARRAY(banked_r13, CPUState, 6),
+ VMSTATE_UINT32_ARRAY(banked_r14, CPUState, 6),
+ VMSTATE_UINT32_ARRAY(usr_regs, CPUState, 5),
+ VMSTATE_UINT32_ARRAY(fiq_regs, CPUState, 5),
+ VMSTATE_UINT32(cp15.c0_cpuid, CPUState),
+ VMSTATE_UINT32(cp15.c0_cachetype, CPUState),
+ VMSTATE_UINT32(cp15.c0_cssel, CPUState),
+ VMSTATE_UINT32(cp15.c1_sys, CPUState),
+ VMSTATE_UINT32(cp15.c1_coproc, CPUState),
+ VMSTATE_UINT32(cp15.c1_xscaleauxcr, CPUState),
+ VMSTATE_UINT32(cp15.c2_base0, CPUState),
+ VMSTATE_UINT32(cp15.c2_base1, CPUState),
+ VMSTATE_UINT32(cp15.c2_control, CPUState),
+ VMSTATE_UINT32(cp15.c2_mask, CPUState),
+ VMSTATE_UINT32(cp15.c2_base_mask, CPUState),
+ VMSTATE_UINT32(cp15.c2_data, CPUState),
+ VMSTATE_UINT32(cp15.c2_insn, CPUState),
+ VMSTATE_UINT32(cp15.c3, CPUState),
+ VMSTATE_UINT32(cp15.c5_insn, CPUState),
+ VMSTATE_UINT32(cp15.c5_data, CPUState),
+ VMSTATE_UINT32_ARRAY(cp15.c6_region, CPUState, 8),
+ VMSTATE_UINT32(cp15.c6_insn, CPUState),
+ VMSTATE_UINT32(cp15.c6_data, CPUState),
+ VMSTATE_UINT32(cp15.c7_par, CPUState),
+ VMSTATE_UINT32(cp15.c9_insn, CPUState),
+ VMSTATE_UINT32(cp15.c9_data, CPUState),
+ VMSTATE_UINT32(cp15.c9_pmcr, CPUState),
+ VMSTATE_UINT32(cp15.c9_pmcnten, CPUState),
+ VMSTATE_UINT32(cp15.c9_pmovsr, CPUState),
+ VMSTATE_UINT32(cp15.c9_pmxevtyper, CPUState),
+ VMSTATE_UINT32(cp15.c9_pmuserenr, CPUState),
+ VMSTATE_UINT32(cp15.c9_pminten, CPUState),
+ VMSTATE_UINT32(cp15.c13_fcse, CPUState),
+ VMSTATE_UINT32(cp15.c13_context, CPUState),
+ VMSTATE_UINT32(cp15.c13_tls1, CPUState),
+ VMSTATE_UINT32(cp15.c13_tls2, CPUState),
+ VMSTATE_UINT32(cp15.c13_tls3, CPUState),
+ VMSTATE_UINT32(cp15.c15_cpar, CPUState),
+ VMSTATE_UINT32(features, CPUState),
+ VMSTATE_END_OF_LIST()
+ },
+ .subsections = (VMStateSubsection[]) {
+ {
+ .vmsd = &vmstate_feature_vfp,
+ .needed = feature_vfp_needed,
+ } , {
+ .vmsd = &vmstate_feature_iwmmxt,
+ .needed = feature_iwmmxt_needed,
+ } , {
+ .vmsd = &vmstate_feature_m,
+ .needed = feature_m_needed,
+ } , {
+ .vmsd = &vmstate_feature_thumb2ee,
+ .needed = feature_thumb2ee_needed,
+ } , {
+ /* empty */
+ }
+ }
+};
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [Qemu-devel] [PATCH 25/25] vmstate: all cpus converted
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
` (23 preceding siblings ...)
2011-10-25 14:00 ` [Qemu-devel] [PATCH 24/25] vmstate: port arm cpu Juan Quintela
@ 2011-10-25 14:00 ` Juan Quintela
24 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 14:00 UTC (permalink / raw)
To: qemu-devel; +Cc: aliguori
We don't have any more CPU_SAVEVM_VERSION users, neither
cpu_save/load() ones.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
exec.c | 5 -----
qemu-common.h | 4 ----
2 files changed, 0 insertions(+), 9 deletions(-)
diff --git a/exec.c b/exec.c
index 09f3f01..cc84378 100644
--- a/exec.c
+++ b/exec.c
@@ -660,13 +660,8 @@ void cpu_exec_init(CPUState *env)
#endif
#if !defined(CONFIG_USER_ONLY)
vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env);
-#if defined(CPU_SAVE_VERSION)
- register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
- cpu_save, cpu_load, env);
-#else
vmstate_register(NULL, cpu_index, &vmstate_cpu, env);
#endif
-#endif
}
/* Allocate a new translation block. Flush the translation buffer if
diff --git a/qemu-common.h b/qemu-common.h
index 1c15cb1..fd0fc30 100644
--- a/qemu-common.h
+++ b/qemu-common.h
@@ -246,10 +246,6 @@ bool tcg_enabled(void);
void cpu_exec_init_all(void);
-/* CPU save/load. */
-void cpu_save(QEMUFile *f, void *opaque);
-int cpu_load(QEMUFile *f, void *opaque, int version_id);
-
/* Unblock cpu */
void qemu_cpu_kick(void *env);
void qemu_cpu_kick_self(void);
--
1.7.6.4
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH 03/25] vmstate: make all architectures export a way to migrate cpu's
2011-10-25 14:00 ` [Qemu-devel] [PATCH 03/25] vmstate: make all architectures export a way to migrate cpu's Juan Quintela
@ 2011-10-25 15:33 ` Andreas Färber
2011-10-25 15:50 ` Juan Quintela
2011-10-25 17:55 ` Max Filippov
` (2 subsequent siblings)
3 siblings, 1 reply; 39+ messages in thread
From: Andreas Färber @ 2011-10-25 15:33 UTC (permalink / raw)
To: Juan Quintela
Cc: aliguori, qemu-devel, Alexander Graf, Max Filippov, Michael Walle,
Paul Brook, Aurelien Jarno, Richard Henderson
Am 25.10.2011 16:00, schrieb Juan Quintela:
> This makes several changes:
> - exports VMStateDescription vmstate_cpu non-static.
> - makes sure that every cpu has a vmstate_cpu or cpu_save/load defined
> - for the architecture that had nothing, it just register the cpu as unmigratable.
> - Depending on CPU_SAVE_VERSION we register old/new migration style
>
> Signed-off-by: Juan Quintela <quintela@redhat.com>
I like that move in general.
> diff --git a/target-m68k/machine.c b/target-m68k/machine.c
> index e69de29..86b6fe9 100644
> --- a/target-m68k/machine.c
> +++ b/target-m68k/machine.c
> @@ -0,0 +1,10 @@
> +
> +#include "hw/hw.h"
> +
> +/* To make this architecture migratable, we need to define cpu state
> + here. Other things need to be done elsewhere */
> +
> +const VMStateDescription vmstate_cpu = {
> + .name = "cpu",
> + .unmigratable = 1,
> +};
Here ...
> diff --git a/target-sh4/machine.c b/target-sh4/machine.c
> index e69de29..86b6fe9 100644
> --- a/target-sh4/machine.c
> +++ b/target-sh4/machine.c
> @@ -0,0 +1,10 @@
> +
> +#include "hw/hw.h"
> +
> +/* To make this architecture migratable, we need to define cpu state
> + here. Other things need to be done elsewhere */
> +
> +const VMStateDescription vmstate_cpu = {
> + .name = "cpu",
> + .unmigratable = 1,
> +};
... and here you sort-of create new files (empty before) without a
license header. The contents is trivial right now, but it would get a
case for the Wiki trying to figure out what license to put on other
people's code.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH 03/25] vmstate: make all architectures export a way to migrate cpu's
2011-10-25 15:33 ` Andreas Färber
@ 2011-10-25 15:50 ` Juan Quintela
2011-10-25 20:41 ` Andreas Färber
0 siblings, 1 reply; 39+ messages in thread
From: Juan Quintela @ 2011-10-25 15:50 UTC (permalink / raw)
To: Andreas Färber
Cc: aliguori, qemu-devel, Alexander Graf, Max Filippov, Michael Walle,
Paul Brook, Aurelien Jarno, Richard Henderson
Andreas Färber <afaerber@suse.de> wrote:
> Am 25.10.2011 16:00, schrieb Juan Quintela:
>> This makes several changes:
>> - exports VMStateDescription vmstate_cpu non-static.
>> - makes sure that every cpu has a vmstate_cpu or cpu_save/load defined
>> - for the architecture that had nothing, it just register the cpu as unmigratable.
>> - Depending on CPU_SAVE_VERSION we register old/new migration style
>>
>> Signed-off-by: Juan Quintela <quintela@redhat.com>
>
> I like that move in general.
>
>> diff --git a/target-m68k/machine.c b/target-m68k/machine.c
>> index e69de29..86b6fe9 100644
>> --- a/target-m68k/machine.c
>> +++ b/target-m68k/machine.c
>> @@ -0,0 +1,10 @@
>> +
>> +#include "hw/hw.h"
>> +
>> +/* To make this architecture migratable, we need to define cpu state
>> + here. Other things need to be done elsewhere */
>> +
>> +const VMStateDescription vmstate_cpu = {
>> + .name = "cpu",
>> + .unmigratable = 1,
>> +};
>
> Here ...
>
>> diff --git a/target-sh4/machine.c b/target-sh4/machine.c
>> index e69de29..86b6fe9 100644
>> --- a/target-sh4/machine.c
>> +++ b/target-sh4/machine.c
>> @@ -0,0 +1,10 @@
>> +
>> +#include "hw/hw.h"
>> +
>> +/* To make this architecture migratable, we need to define cpu state
>> + here. Other things need to be done elsewhere */
>> +
>> +const VMStateDescription vmstate_cpu = {
>> + .name = "cpu",
>> + .unmigratable = 1,
>> +};
>
> ... and here you sort-of create new files (empty before) without a
> license header. The contents is trivial right now, but it would get a
> case for the Wiki trying to figure out what license to put on other
> people's code.
None of target-*/machine.c files have a license line. I can put the
normal boilerplate on them, but I have just transformed them, So .. who
should I put as copyright owner? Puting me is (at least) a bit
presumptuous, if not just plain false O:-)
Later, Juan.
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH 03/25] vmstate: make all architectures export a way to migrate cpu's
2011-10-25 14:00 ` [Qemu-devel] [PATCH 03/25] vmstate: make all architectures export a way to migrate cpu's Juan Quintela
2011-10-25 15:33 ` Andreas Färber
@ 2011-10-25 17:55 ` Max Filippov
2011-10-25 17:58 ` Richard Henderson
2011-10-25 19:02 ` Michael Walle
3 siblings, 0 replies; 39+ messages in thread
From: Max Filippov @ 2011-10-25 17:55 UTC (permalink / raw)
To: Juan Quintela
Cc: aliguori, Alexander Graf, qemu-devel, Michael Walle, Paul Brook,
Aurelien Jarno, Richard Henderson
> This makes several changes:
> - exports VMStateDescription vmstate_cpu non-static.
> - makes sure that every cpu has a vmstate_cpu or cpu_save/load defined
> - for the architecture that had nothing, it just register the cpu as unmigratable.
> - Depending on CPU_SAVE_VERSION we register old/new migration style
>
> Signed-off-by: Juan Quintela <quintela@redhat.com>
[...snip...]
> diff --git a/target-xtensa/machine.c b/target-xtensa/machine.c
> index ddeffb2..3f98330 100644
> --- a/target-xtensa/machine.c
> +++ b/target-xtensa/machine.c
> @@ -26,13 +26,11 @@
> */
>
> #include "hw/hw.h"
> -#include "hw/boards.h"
>
> -void cpu_save(QEMUFile *f, void *opaque)
> -{
> -}
> +/* To make this architecture migratable, we need to define cpu state
> + here. Other things need to be done elsewhere */
>
> -int cpu_load(QEMUFile *f, void *opaque, int version_id)
> -{
> - return 0;
> -}
> +const VMStateDescription vmstate_cpu = {
> + .name = "cpu",
> + .unmigratable = 1,
> +};
>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Thanks.
-- Max
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH 03/25] vmstate: make all architectures export a way to migrate cpu's
2011-10-25 14:00 ` [Qemu-devel] [PATCH 03/25] vmstate: make all architectures export a way to migrate cpu's Juan Quintela
2011-10-25 15:33 ` Andreas Färber
2011-10-25 17:55 ` Max Filippov
@ 2011-10-25 17:58 ` Richard Henderson
2011-10-25 19:02 ` Michael Walle
3 siblings, 0 replies; 39+ messages in thread
From: Richard Henderson @ 2011-10-25 17:58 UTC (permalink / raw)
To: Juan Quintela
Cc: aliguori, qemu-devel, Alexander Graf, Max Filippov, Michael Walle,
Paul Brook, Aurelien Jarno
On 10/25/2011 07:00 AM, Juan Quintela wrote:
> This makes several changes:
> - exports VMStateDescription vmstate_cpu non-static.
> - makes sure that every cpu has a vmstate_cpu or cpu_save/load defined
> - for the architecture that had nothing, it just register the cpu as unmigratable.
> - Depending on CPU_SAVE_VERSION we register old/new migration style
>
> Signed-off-by: Juan Quintela <quintela@redhat.com>
> CC: Richard Henderson <rth@twiddle.net>
> CC: Michael Walle <michael@walle.cc>
> CC: Paul Brook <paul@codesourcery.com>
> CC: Alexander Graf <agraf@suse.de>
> CC: Aurelien Jarno <aurelien@aurel32.net>
> CC: Max Filippov <jcmvbkbc@gmail.com>
> ---
> exec.c | 2 ++
> hw/hw.h | 2 ++
> target-alpha/machine.c | 12 +-----------
> target-i386/machine.c | 2 +-
> target-lm32/machine.c | 2 +-
> target-m68k/machine.c | 10 ++++++++++
> target-s390x/machine.c | 14 ++++++--------
> target-sh4/machine.c | 10 ++++++++++
> target-xtensa/machine.c | 14 ++++++--------
...
> --- a/target-alpha/machine.c
> +++ b/target-alpha/machine.c
> @@ -68,20 +68,10 @@ static VMStateField vmstate_cpu_fields[] = {
> VMSTATE_END_OF_LIST()
> };
>
> -static const VMStateDescription vmstate_cpu = {
> +const VMStateDescription vmstate_cpu = {
> .name = "cpu",
> .version_id = 1,
> .minimum_version_id = 1,
> .minimum_version_id_old = 1,
> .fields = vmstate_cpu_fields,
> };
> -
> -void cpu_save(QEMUFile *f, void *opaque)
> -{
> - vmstate_save_state(f, &vmstate_cpu, opaque);
> -}
> -
> -int cpu_load(QEMUFile *f, void *opaque, int version_id)
> -{
> - return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
> -}
Acked-by: Richard Henderson <rth@twiddle.net>
r~
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH 24/25] vmstate: port arm cpu
2011-10-25 14:00 ` [Qemu-devel] [PATCH 24/25] vmstate: port arm cpu Juan Quintela
@ 2011-10-25 18:27 ` Paul Brook
2011-10-25 19:08 ` Richard Henderson
0 siblings, 1 reply; 39+ messages in thread
From: Paul Brook @ 2011-10-25 18:27 UTC (permalink / raw)
To: Juan Quintela; +Cc: Peter Maydell, aliguori, qemu-devel
> - /* Avoid mode switch when restoring CPSR. */
> - env->uncached_cpsr = val & CPSR_M;
> - cpsr_write(env, val, 0xffffffff);
> +
> + env->uncached_cpsr = env->cpsr_vmstate & CPSR_M;
> + cpsr_write(env, env->cpsr_vmstate, 0xffffffff);
You've removed the helpful comment explaining why this wierdness exists.
Please put it back.
A comment in cpu.h explaining what cpsr_vmstate is for would also be nice.
Specifically it's a hack[1] to transfer data between the pre_save/post_load
hooks and the vmstate machinery. IMO "vmstate" is a sufficiently generic term
that it could be confused with some actual cpu register, especially once we
get round to implementing the hypervisor extensions.
Paul
[1] Maybe a necessary hack, but still a wart from requiring static table
driven vmstate descriptions.
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH 03/25] vmstate: make all architectures export a way to migrate cpu's
2011-10-25 14:00 ` [Qemu-devel] [PATCH 03/25] vmstate: make all architectures export a way to migrate cpu's Juan Quintela
` (2 preceding siblings ...)
2011-10-25 17:58 ` Richard Henderson
@ 2011-10-25 19:02 ` Michael Walle
3 siblings, 0 replies; 39+ messages in thread
From: Michael Walle @ 2011-10-25 19:02 UTC (permalink / raw)
To: Juan Quintela
Cc: aliguori, Alexander Graf, qemu-devel, Max Filippov, Paul Brook,
Aurelien Jarno, Richard Henderson
Am Dienstag 25 Oktober 2011, 16:00:37 schrieb Juan Quintela:
> This makes several changes:
> - exports VMStateDescription vmstate_cpu non-static.
> - makes sure that every cpu has a vmstate_cpu or cpu_save/load defined
> - for the architecture that had nothing, it just register the cpu as
> unmigratable. - Depending on CPU_SAVE_VERSION we register old/new
> migration style
[..]
> diff --git a/target-lm32/machine.c b/target-lm32/machine.c
> index 70ca52a..9014a9f 100644
> --- a/target-lm32/machine.c
> +++ b/target-lm32/machine.c
> @@ -1,7 +1,7 @@
> #include "hw/hw.h"
> #include "hw/boards.h"
>
> -static const VMStateDescription vmstate_cpu = {
> +const VMStateDescription vmstate_cpu = {
> .name = "cpu",
> .version_id = CPU_SAVE_VERSION,
> .minimum_version_id = 1,
> diff --git a/target-m68k/machine.c b/target-m68k/machine.c
> index e69de29..86b6fe9 100644
[..]
Acked-by: Michael Walle <michael@walle.cc>
--
Michael
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH 06/25] vmstate: use new style for lm32 cpus
2011-10-25 14:00 ` [Qemu-devel] [PATCH 06/25] vmstate: use new style for lm32 cpus Juan Quintela
@ 2011-10-25 19:02 ` Michael Walle
0 siblings, 0 replies; 39+ messages in thread
From: Michael Walle @ 2011-10-25 19:02 UTC (permalink / raw)
To: Juan Quintela; +Cc: aliguori, qemu-devel
Am Dienstag 25 Oktober 2011, 16:00:40 schrieb Juan Quintela:
> Signed-off-by: Juan Quintela <quintela@redhat.com>
> CC: Michael Walle <michael@walle.cc>
> ---
> target-lm32/cpu.h | 2 --
> target-lm32/machine.c | 12 +-----------
> 2 files changed, 1 insertions(+), 13 deletions(-)
>
> diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
> index 037ef52..bd37af8 100644
> --- a/target-lm32/cpu.h
> +++ b/target-lm32/cpu.h
> @@ -202,8 +202,6 @@ void cpu_lm32_set_phys_msb_ignore(CPUState *env, int
> value); #define cpu_gen_code cpu_lm32_gen_code
> #define cpu_signal_handler cpu_lm32_signal_handler
>
> -#define CPU_SAVE_VERSION 1
> -
> int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
> int mmu_idx);
> #define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault
> diff --git a/target-lm32/machine.c b/target-lm32/machine.c
> index 9014a9f..e9ed250 100644
> --- a/target-lm32/machine.c
> +++ b/target-lm32/machine.c
> @@ -3,7 +3,7 @@
>
> const VMStateDescription vmstate_cpu = {
> .name = "cpu",
> - .version_id = CPU_SAVE_VERSION,
> + .version_id = 1,
> .minimum_version_id = 1,
> .minimum_version_id_old = 1,
> .fields = (VMStateField[]) {
> @@ -21,13 +21,3 @@ const VMStateDescription vmstate_cpu = {
> VMSTATE_END_OF_LIST()
> }
> };
> -
> -void cpu_save(QEMUFile *f, void *opaque)
> -{
> - vmstate_save_state(f, &vmstate_cpu, opaque);
> -}
> -
> -int cpu_load(QEMUFile *f, void *opaque, int version_id)
> -{
> - return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
> -}
Acked-by: Michael Walle <michael@walle.cc>
--
Michael
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH 24/25] vmstate: port arm cpu
2011-10-25 18:27 ` Paul Brook
@ 2011-10-25 19:08 ` Richard Henderson
2011-10-25 20:39 ` Paul Brook
0 siblings, 1 reply; 39+ messages in thread
From: Richard Henderson @ 2011-10-25 19:08 UTC (permalink / raw)
To: Paul Brook; +Cc: Peter Maydell, aliguori, qemu-devel, Juan Quintela
On 10/25/2011 11:27 AM, Paul Brook wrote:
>> - /* Avoid mode switch when restoring CPSR. */
>> - env->uncached_cpsr = val & CPSR_M;
>> - cpsr_write(env, val, 0xffffffff);
>> +
>> + env->uncached_cpsr = env->cpsr_vmstate & CPSR_M;
>> + cpsr_write(env, env->cpsr_vmstate, 0xffffffff);
>
> You've removed the helpful comment explaining why this wierdness exists.
> Please put it back.
>
> A comment in cpu.h explaining what cpsr_vmstate is for would also be nice.
> Specifically it's a hack[1] to transfer data between the pre_save/post_load
> hooks and the vmstate machinery. IMO "vmstate" is a sufficiently generic term
> that it could be confused with some actual cpu register, especially once we
> get round to implementing the hypervisor extensions.
>
> Paul
>
> [1] Maybe a necessary hack, but still a wart from requiring static table
> driven vmstate descriptions.
I wonder if we shouldn't make it easier to do what I do for Alpha
with the rather different hack for the fpcr.
That might avoid some of the other pre/post_load hooks, and the
extra data fields that requires in the cpu structure.
r~
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH 17/25] vmstate: make incompatible change for sparc
2011-10-25 14:00 ` [Qemu-devel] [PATCH 17/25] vmstate: make incompatible change for sparc Juan Quintela
@ 2011-10-25 20:30 ` Blue Swirl
0 siblings, 0 replies; 39+ messages in thread
From: Blue Swirl @ 2011-10-25 20:30 UTC (permalink / raw)
To: Juan Quintela; +Cc: aliguori, qemu-devel
On Tue, Oct 25, 2011 at 14:00, Juan Quintela <quintela@redhat.com> wrote:
> With this change, we sent arrays as arrays, making state description
> much simpler. The change is incompatible, but as far as I know, sparc
> don't care about migration compatibility beteween versions.
Can't speak for other sparc, but at least I don't care much and nobody
has complained IIRC.
> Signed-off-by: Juan Quintela <quintela@redhat.com>
> CC: Blue Swirl <blauwirbel@gmail.com>
> ---
> target-sparc/machine.c | 172 +++---------------------------------------------
> 1 files changed, 9 insertions(+), 163 deletions(-)
>
> diff --git a/target-sparc/machine.c b/target-sparc/machine.c
> index 2186756..ccca36f 100644
> --- a/target-sparc/machine.c
> +++ b/target-sparc/machine.c
> @@ -74,9 +74,9 @@ static int cpu_post_load(void *opaque, int version_id)
>
> const VMStateDescription vmstate_cpu = {
> .name = "cpu",
> - .version_id = 7,
> - .minimum_version_id = 7,
> - .minimum_version_id_old = 7,
> + .version_id = 8,
> + .minimum_version_id = 8,
> + .minimum_version_id_old = 8,
> .pre_save = cpu_pre_save,
> .post_load = cpu_post_load,
> .fields = (VMStateField[]) {
> @@ -106,166 +106,12 @@ const VMStateDescription vmstate_cpu = {
> VMSTATE_UINT64_ARRAY(mmubpregs, CPUState, 4),
> #else
> VMSTATE_UINT64(lsu, CPUState),
> - VMSTATE_UINT64(immuregs[0], CPUState),
> - VMSTATE_UINT64(dmmuregs[0], CPUState),
> - VMSTATE_UINT64(immuregs[1], CPUState),
> - VMSTATE_UINT64(dmmuregs[1], CPUState),
> - VMSTATE_UINT64(immuregs[2], CPUState),
> - VMSTATE_UINT64(dmmuregs[2], CPUState),
> - VMSTATE_UINT64(immuregs[3], CPUState),
> - VMSTATE_UINT64(dmmuregs[3], CPUState),
> - VMSTATE_UINT64(immuregs[4], CPUState),
> - VMSTATE_UINT64(dmmuregs[4], CPUState),
> - VMSTATE_UINT64(immuregs[5], CPUState),
> - VMSTATE_UINT64(dmmuregs[5], CPUState),
> - VMSTATE_UINT64(immuregs[6], CPUState),
> - VMSTATE_UINT64(dmmuregs[6], CPUState),
> - VMSTATE_UINT64(immuregs[7], CPUState),
> - VMSTATE_UINT64(dmmuregs[7], CPUState),
> - VMSTATE_UINT64(immuregs[8], CPUState),
> - VMSTATE_UINT64(dmmuregs[8], CPUState),
> - VMSTATE_UINT64(immuregs[9], CPUState),
> - VMSTATE_UINT64(dmmuregs[9], CPUState),
> - VMSTATE_UINT64(immuregs[10], CPUState),
> - VMSTATE_UINT64(dmmuregs[10], CPUState),
> - VMSTATE_UINT64(immuregs[11], CPUState),
> - VMSTATE_UINT64(dmmuregs[11], CPUState),
> - VMSTATE_UINT64(immuregs[12], CPUState),
> - VMSTATE_UINT64(dmmuregs[12], CPUState),
> - VMSTATE_UINT64(immuregs[13], CPUState),
> - VMSTATE_UINT64(dmmuregs[13], CPUState),
> - VMSTATE_UINT64(immuregs[14], CPUState),
> - VMSTATE_UINT64(dmmuregs[14], CPUState),
> - VMSTATE_UINT64(immuregs[15], CPUState),
> - VMSTATE_UINT64(dmmuregs[15], CPUState),
> - VMSTATE_STRUCT(itlb[0], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[0], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[1], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[1], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[2], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[2], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[3], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[3], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[4], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[4], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[5], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[5], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[6], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[6], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[7], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[7], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[8], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[8], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[9], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[9], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[10], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[10], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[11], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[11], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[12], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[12], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[13], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[13], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[14], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[14], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[15], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[15], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[16], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[16], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[17], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[17], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[18], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[18], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[19], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[19], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[20], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[20], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[21], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[21], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[22], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[22], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[23], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[23], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[24], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[24], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[25], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[25], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[26], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[26], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[27], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[27], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[28], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[28], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[29], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[29], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[30], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[30], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[31], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[31], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[32], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[32], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[33], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[33], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[34], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[34], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[35], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[35], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[36], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[36], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[37], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[37], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[38], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[38], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[39], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[39], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[40], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[40], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[41], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[41], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[42], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[42], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[43], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[43], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[44], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[44], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[45], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[45], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[46], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[46], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[47], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[47], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[48], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[48], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[49], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[49], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[50], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[50], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[51], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[51], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[52], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[52], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[53], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[53], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[54], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[54], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[55], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[55], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[56], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[56], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[57], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[57], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[58], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[58], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[59], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[59], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[60], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[60], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[61], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[61], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[62], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[62], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(itlb[63], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> - VMSTATE_STRUCT(dtlb[63], CPUState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_UINT64_ARRAY(immuregs, CPUState, 16),
> + VMSTATE_UINT64_ARRAY(dmmuregs, CPUState, 16),
> + VMSTATE_STRUCT_ARRAY(itlb, CPUState, 64, 0,
> + vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT_ARRAY(dtlb, CPUState, 64, 0,
> + vmstate_tlb_entry, SparcTLBEntry),
> VMSTATE_UINT32(mmu_version, CPUState),
> VMSTATE_STRUCT_ARRAY(ts, CPUState, MAXTL_MAX, 0,
> vmstate_trap_state, trap_state),
> --
> 1.7.6.4
>
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH 24/25] vmstate: port arm cpu
2011-10-25 19:08 ` Richard Henderson
@ 2011-10-25 20:39 ` Paul Brook
0 siblings, 0 replies; 39+ messages in thread
From: Paul Brook @ 2011-10-25 20:39 UTC (permalink / raw)
To: Richard Henderson; +Cc: Peter Maydell, aliguori, qemu-devel, Juan Quintela
> >> + env->uncached_cpsr = env->cpsr_vmstate & CPSR_M;
> >> + cpsr_write(env, env->cpsr_vmstate, 0xffffffff);
> >
> > [1] Maybe a necessary hack, but still a wart from requiring static table
> > driven vmstate descriptions.
>
> I wonder if we shouldn't make it easier to do what I do for Alpha
> with the rather different hack for the fpcr.
>
> That might avoid some of the other pre/post_load hooks, and the
> extra data fields that requires in the cpu structure.
Sounds reasonable.
Having either woraround is a bit lame. Having ARM and Alpha use different
workarounds for the same problem really sucks.
Paul
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH 03/25] vmstate: make all architectures export a way to migrate cpu's
2011-10-25 15:50 ` Juan Quintela
@ 2011-10-25 20:41 ` Andreas Färber
0 siblings, 0 replies; 39+ messages in thread
From: Andreas Färber @ 2011-10-25 20:41 UTC (permalink / raw)
To: quintela
Cc: aliguori, qemu-devel, Alexander Graf, Max Filippov, Michael Walle,
Paul Brook, Aurelien Jarno, Richard Henderson
Am 25.10.2011 17:50, schrieb Juan Quintela:
> Andreas Färber <afaerber@suse.de> wrote:
>>> diff --git a/target-m68k/machine.c b/target-m68k/machine.c
>>> index e69de29..86b6fe9 100644
>>> --- a/target-m68k/machine.c
>>> +++ b/target-m68k/machine.c
>>> @@ -0,0 +1,10 @@
>>> +
>>> +#include "hw/hw.h"
>>> +
>>> +/* To make this architecture migratable, we need to define cpu state
>>> + here. Other things need to be done elsewhere */
>>> +
>>> +const VMStateDescription vmstate_cpu = {
>>> + .name = "cpu",
>>> + .unmigratable = 1,
>>> +};
>>
>> Here ...
>>
>>> diff --git a/target-sh4/machine.c b/target-sh4/machine.c
>>> index e69de29..86b6fe9 100644
>>> --- a/target-sh4/machine.c
>>> +++ b/target-sh4/machine.c
>>> @@ -0,0 +1,10 @@
>>> +
>>> +#include "hw/hw.h"
>>> +
>>> +/* To make this architecture migratable, we need to define cpu state
>>> + here. Other things need to be done elsewhere */
>>> +
>>> +const VMStateDescription vmstate_cpu = {
>>> + .name = "cpu",
>>> + .unmigratable = 1,
>>> +};
>>
>> ... and here you sort-of create new files (empty before) without a
>> license header. The contents is trivial right now, but it would get a
>> case for the Wiki trying to figure out what license to put on other
>> people's code.
>
> None of target-*/machine.c files have a license line. I can put the
> normal boilerplate on them, but I have just transformed them, So .. who
> should I put as copyright owner? Puting me is (at least) a bit
> presumptuous, if not just plain false O:-)
Note my comment was specific to those that you did not really transform.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH 13/25] vmstate: port ppc cpu
2011-10-25 14:00 ` [Qemu-devel] [PATCH 13/25] vmstate: port ppc cpu Juan Quintela
@ 2011-10-30 16:36 ` Alexander Graf
2011-10-31 19:43 ` Juan Quintela
0 siblings, 1 reply; 39+ messages in thread
From: Alexander Graf @ 2011-10-30 16:36 UTC (permalink / raw)
To: Juan Quintela; +Cc: aliguori, qemu-devel
On 25.10.2011, at 16:00, Juan Quintela wrote:
> Added sdr1_vmstate because storing the value requires calling ppc_store_sdr1().
> The position when the function is called also changes (I think it is save).
Thanks for converting this. I'm fairly sure that vmsave is broken atm anyways and that someone will have to go through all the fields and make sure they're still working properly. However you're definitely not making the situation worse, so here's only a small comment:
>
> Signed-off-by: Juan Quintela <quintela@redhat.com>
> CC: Alexander Graf <agraf@suse.de>
> ---
> target-ppc/cpu.h | 4 +-
> target-ppc/machine.c | 245 ++++++++++++++++++--------------------------------
> 2 files changed, 89 insertions(+), 160 deletions(-)
>
> + VMSTATE_UINTTL_ARRAY(spr, CPUState, 1024),
Shouldn't sizeof(((CPUState*)NULL)->spr / sizeof(target_ulong)) work as size field?
Alex
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [Qemu-devel] [PATCH 13/25] vmstate: port ppc cpu
2011-10-30 16:36 ` Alexander Graf
@ 2011-10-31 19:43 ` Juan Quintela
0 siblings, 0 replies; 39+ messages in thread
From: Juan Quintela @ 2011-10-31 19:43 UTC (permalink / raw)
To: Alexander Graf; +Cc: aliguori, qemu-devel
Alexander Graf <agraf@suse.de> wrote:
> On 25.10.2011, at 16:00, Juan Quintela wrote:
>
>> Added sdr1_vmstate because storing the value requires calling ppc_store_sdr1().
>> The position when the function is called also changes (I think it is save).
>
> Thanks for converting this. I'm fairly sure that vmsave is broken atm anyways and that someone will have to go through all the fields and make sure they're still working properly. However you're definitely not making the situation worse, so here's only a small comment:
>
>>
>> Signed-off-by: Juan Quintela <quintela@redhat.com>
>> CC: Alexander Graf <agraf@suse.de>
>> ---
>> target-ppc/cpu.h | 4 +-
>> target-ppc/machine.c | 245 ++++++++++++++++++--------------------------------
>> 2 files changed, 89 insertions(+), 160 deletions(-)
>>
>> + VMSTATE_UINTTL_ARRAY(spr, CPUState, 1024),
>
> Shouldn't sizeof(((CPUState*)NULL)->spr / sizeof(target_ulong)) work as size field?
vmstate is inconsistent about this.
It "calculates" sizes for "strings" (ar uint8_t * if your preffer), but
not for arrays.
#define VMSTATE_BUFFER_V(_f, _s, _v) \
VMSTATE_STATIC_BUFFER(_f, _s, _v, NULL, 0, sizeof(typeof_field(_s, _f)))
#define VMSTATE_BUFFER(_f, _s) \
VMSTATE_BUFFER_V(_f, _s, 0)
And I don't know what the "right" solution is:
- Putting explicit size helps detect changes on that size (good)
- But, on lots of places, we are putting there a constant:
VMSTATE_INT32_ARRAY(tx_fifo, smc91c111_state, NUM_PACKETS),
So, we are not going to detect changes either.
Next on my plate is to get someway of unittesting and being able to
detect this kind of changes (then we can actually drop the sizes
always).
Later, Juan.
^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2011-10-31 19:44 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-10-25 14:00 [Qemu-devel] [PATCH 00/25] VMState port of all cpus Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 01/25] vmstate: Fix VMSTATE_VARRAY_UINT32 Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 02/25] vmstate: Simplify test for CPU_SAVE_VERSION Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 03/25] vmstate: make all architectures export a way to migrate cpu's Juan Quintela
2011-10-25 15:33 ` Andreas Färber
2011-10-25 15:50 ` Juan Quintela
2011-10-25 20:41 ` Andreas Färber
2011-10-25 17:55 ` Max Filippov
2011-10-25 17:58 ` Richard Henderson
2011-10-25 19:02 ` Michael Walle
2011-10-25 14:00 ` [Qemu-devel] [PATCH 04/25] vmstate: unicore32 don't support cpu migration Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 05/25] vmstate: use new cpu style for x86 Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 06/25] vmstate: use new style for lm32 cpus Juan Quintela
2011-10-25 19:02 ` Michael Walle
2011-10-25 14:00 ` [Qemu-devel] [PATCH 07/25] vmstate: make microblaze cpus not migrateable Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 08/25] vmstate: port cris cpu to vmstate Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 09/25] vmstate: machine.c is only compiled for !CONFIG_USER_ONLY Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 10/25] vmstate: introduce float32 arrays Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 11/25] vmstate: introduce float64 arrays Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 12/25] vmstate: Introduce VMSTATE_STRUCT_VARRAY_INT32_TEST Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 13/25] vmstate: port ppc cpu Juan Quintela
2011-10-30 16:36 ` Alexander Graf
2011-10-31 19:43 ` Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 14/25] vmstate: introduce VMSTATE_VARRAY_MULTIPLY Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 15/25] vmstate: define vmstate_info_uinttls Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 16/25] vmstate: port sparc cpu Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 17/25] vmstate: make incompatible change for sparc Juan Quintela
2011-10-25 20:30 ` Blue Swirl
2011-10-25 14:00 ` [Qemu-devel] [PATCH 18/25] mips_fulong2e: cpu vmstate already registered in cpu_exec_init Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 19/25] mips: make mvp an embedded struct instead of pointer Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 20/25] mips: make tlb an embedded struct instead of a pointer Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 21/25] mips: bump migration version to 4 Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 22/25] vmstate: port mips cpu Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 23/25] arm: save always 32 fpu registers Juan Quintela
2011-10-25 14:00 ` [Qemu-devel] [PATCH 24/25] vmstate: port arm cpu Juan Quintela
2011-10-25 18:27 ` Paul Brook
2011-10-25 19:08 ` Richard Henderson
2011-10-25 20:39 ` Paul Brook
2011-10-25 14:00 ` [Qemu-devel] [PATCH 25/25] vmstate: all cpus converted Juan Quintela
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