* [Qemu-devel] [PATCH 0/7] trace: Add some simple TCG tracing events
@ 2011-12-09 20:14 Lluís Vilanova
2011-12-09 20:14 ` [Qemu-devel] [PATCH 1/7] Make 'qemu_init_vcpu' a function (instead of a macro) Lluís Vilanova
` (6 more replies)
0 siblings, 7 replies; 8+ messages in thread
From: Lluís Vilanova @ 2011-12-09 20:14 UTC (permalink / raw)
To: qemu-devel
Adds the following TCG tracing events:
* vbbl : guest starts executing a basic block (a QEMU TB, in fact)
* vfetch: guest starts executing an instruction
* vmem : guest starts performing a memory access
Also includes events for tracing the lifecycle of a vCPU (previously sent
separately in the list).
Depends on the "trace-tcg" series.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
---
Lluís Vilanova (7):
Make 'qemu_init_vcpu' a function (instead of a macro)
trace: Add "vcpu_init" event
trace: Add "vcpu_reset" event
trace: [all] Add "vbbl" TCG tracing event
[all] Trivial 'tcg_gen_debug_insn_start' unification in 'gen_intermediate_code_internal'
trace: [all] Add "vfetch" TCG tracing event
trace: [all] Add "vmem" TCG tracing event
Makefile.objs | 1 +
cpu-all.h | 58 +++++++++++++++++---------------
cpus-user.c | 17 +++++++++
cpus.c | 2 +
exec-all.h | 3 ++
qemu-common.h | 4 --
softmmu_header.h | 15 ++++++++
target-alpha/translate.c | 14 +++++---
target-arm/helper.c | 3 ++
target-arm/translate.c | 3 ++
target-cris/translate.c | 18 +++++++---
target-i386/helper.c | 3 ++
target-i386/translate.c | 8 +++-
target-lm32/helper.c | 3 ++
target-lm32/translate.c | 10 +++---
target-m68k/helper.c | 3 ++
target-m68k/translate.c | 9 ++++-
target-microblaze/translate.c | 12 +++++--
target-mips/translate.c | 12 +++++--
target-ppc/helper.c | 3 ++
target-ppc/translate.c | 9 ++++-
target-s390x/helper.c | 3 ++
target-s390x/translate.c | 8 ++++
target-sh4/translate.c | 14 ++++++--
target-sparc/cpu_init.c | 2 +
target-sparc/helper.c | 2 +
target-sparc/translate.c | 9 ++++-
target-unicore32/translate.c | 6 +++
target-xtensa/translate.c | 10 +++---
tcg/tcg-op.h | 6 +++
trace-events | 38 +++++++++++++++++++++
trace/tcg-op-internal.h | 74 +++++++++++++++++++++++++++++++++++++++++
32 files changed, 315 insertions(+), 67 deletions(-)
create mode 100644 cpus-user.c
create mode 100644 trace/tcg-op-internal.h
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH 1/7] Make 'qemu_init_vcpu' a function (instead of a macro)
2011-12-09 20:14 [Qemu-devel] [PATCH 0/7] trace: Add some simple TCG tracing events Lluís Vilanova
@ 2011-12-09 20:14 ` Lluís Vilanova
2011-12-09 20:15 ` [Qemu-devel] [PATCH 2/7] trace: Add "vcpu_init" event Lluís Vilanova
` (5 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Lluís Vilanova @ 2011-12-09 20:14 UTC (permalink / raw)
To: qemu-devel
Implementation with 'CONFIG_USER_ONLY' is moved into new file 'cpus-user.c'.
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
---
Makefile.objs | 1 +
cpus-user.c | 15 +++++++++++++++
qemu-common.h | 4 ----
3 files changed, 16 insertions(+), 4 deletions(-)
create mode 100644 cpus-user.c
diff --git a/Makefile.objs b/Makefile.objs
index f153fa5..b17b64f 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -178,6 +178,7 @@ user-obj-y =
user-obj-y += envlist.o path.o
user-obj-y += tcg-runtime.o host-utils.o
user-obj-y += cutils.o cache-utils.o
+user-obj-y += cpus-user.o
user-obj-y += $(trace-obj-y)
######################################################################
diff --git a/cpus-user.c b/cpus-user.c
new file mode 100644
index 0000000..50e45ce
--- /dev/null
+++ b/cpus-user.c
@@ -0,0 +1,15 @@
+/*
+ * Implementation of routines in "cpus.c" when compiling for CONFIG_USER_ONLY.
+ *
+ * Copyright (C) 2011 Lluís Vilanova <vilanova@ac.upc.edu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "qemu-common.h"
+
+
+void qemu_init_vcpu(void *env)
+{
+}
diff --git a/qemu-common.h b/qemu-common.h
index 2ce47aa..2cd838a 100644
--- a/qemu-common.h
+++ b/qemu-common.h
@@ -265,11 +265,7 @@ struct qemu_work_item {
int done;
};
-#ifdef CONFIG_USER_ONLY
-#define qemu_init_vcpu(env) do { } while (0)
-#else
void qemu_init_vcpu(void *env);
-#endif
typedef struct QEMUIOVector {
struct iovec *iov;
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH 2/7] trace: Add "vcpu_init" event
2011-12-09 20:14 [Qemu-devel] [PATCH 0/7] trace: Add some simple TCG tracing events Lluís Vilanova
2011-12-09 20:14 ` [Qemu-devel] [PATCH 1/7] Make 'qemu_init_vcpu' a function (instead of a macro) Lluís Vilanova
@ 2011-12-09 20:15 ` Lluís Vilanova
2011-12-09 20:15 ` [Qemu-devel] [PATCH 3/7] trace: Add "vcpu_reset" event Lluís Vilanova
` (4 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Lluís Vilanova @ 2011-12-09 20:15 UTC (permalink / raw)
To: qemu-devel
Signals the creation of a new vCPU (CPUState structure).
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
---
cpus-user.c | 2 ++
cpus.c | 2 ++
trace-events | 7 +++++++
3 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/cpus-user.c b/cpus-user.c
index 50e45ce..69b580d 100644
--- a/cpus-user.c
+++ b/cpus-user.c
@@ -8,8 +8,10 @@
*/
#include "qemu-common.h"
+#include "trace.h"
void qemu_init_vcpu(void *env)
{
+ trace_vcpu_init(env);
}
diff --git a/cpus.c b/cpus.c
index 82530c4..9049011 100644
--- a/cpus.c
+++ b/cpus.c
@@ -35,6 +35,7 @@
#include "qemu-thread.h"
#include "cpus.h"
#include "main-loop.h"
+#include "trace.h"
#ifndef _WIN32
#include "compatfd.h"
@@ -944,6 +945,7 @@ void qemu_init_vcpu(void *_env)
} else {
qemu_tcg_init_vcpu(env);
}
+ trace_vcpu_init(env);
}
void cpu_stop_current(void)
diff --git a/trace-events b/trace-events
index 962caca..1a2d302 100644
--- a/trace-events
+++ b/trace-events
@@ -631,3 +631,10 @@ win_helper_no_switch_pstate(uint32_t new_pstate_regs) "change_pstate: regs new=%
win_helper_wrpil(uint32_t psrpil, uint32_t new_pil) "old=%x new=%x"
win_helper_done(uint32_t tl) "tl=%d"
win_helper_retry(uint32_t tl) "tl=%d"
+
+### Abstract events (not specific to a file; keep at bottom)
+
+## vCPU
+
+# Create a new vCPU (CPUState structure)
+vcpu_init(void *vcpu) "%p"
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH 3/7] trace: Add "vcpu_reset" event
2011-12-09 20:14 [Qemu-devel] [PATCH 0/7] trace: Add some simple TCG tracing events Lluís Vilanova
2011-12-09 20:14 ` [Qemu-devel] [PATCH 1/7] Make 'qemu_init_vcpu' a function (instead of a macro) Lluís Vilanova
2011-12-09 20:15 ` [Qemu-devel] [PATCH 2/7] trace: Add "vcpu_init" event Lluís Vilanova
@ 2011-12-09 20:15 ` Lluís Vilanova
2011-12-09 20:15 ` [Qemu-devel] [PATCH 4/7] trace: [all] Add "vbbl" TCG tracing event Lluís Vilanova
` (3 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Lluís Vilanova @ 2011-12-09 20:15 UTC (permalink / raw)
To: qemu-devel
Signals the reset of the state a vCPU (CPUState structure).
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
---
target-arm/helper.c | 3 +++
target-cris/translate.c | 3 +++
target-i386/helper.c | 3 +++
target-lm32/helper.c | 3 +++
target-m68k/helper.c | 3 +++
target-microblaze/translate.c | 3 +++
target-mips/translate.c | 3 +++
target-ppc/helper.c | 3 +++
target-s390x/helper.c | 3 +++
target-sh4/translate.c | 3 +++
target-sparc/cpu_init.c | 2 ++
target-sparc/helper.c | 2 ++
trace-events | 2 ++
13 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 97af4d0..789fd8b 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -10,6 +10,7 @@
#if !defined(CONFIG_USER_ONLY)
#include "hw/loader.h"
#endif
+#include "trace.h"
static uint32_t cortexa9_cp15_c0_c1[8] =
{ 0x1031, 0x11, 0x000, 0, 0x00100103, 0x20000000, 0x01230000, 0x00002111 };
@@ -325,6 +326,8 @@ void cpu_reset(CPUARMState *env)
set_float_detect_tininess(float_tininess_before_rounding,
&env->vfp.standard_fp_status);
tlb_flush(env, 1);
+
+ trace_vcpu_reset(env);
}
static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 70abf8a..a871e7f 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -36,6 +36,7 @@
#include "mmu.h"
#include "crisv32-decode.h"
#include "qemu-common.h"
+#include "trace.h"
#define GEN_HELPER 1
#include "helper.h"
@@ -3601,6 +3602,8 @@ void cpu_reset (CPUCRISState *env)
cris_mmu_init(env);
env->pregs[PR_CCS] = 0;
#endif
+
+ trace_vcpu_reset(env);
}
void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 2586aff..3b0106b 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -29,6 +29,7 @@
#include "sysemu.h"
#include "monitor.h"
#endif
+#include "trace.h"
//#define DEBUG_MMU
@@ -105,6 +106,8 @@ void cpu_reset(CPUX86State *env)
env->dr[7] = DR7_FIXED_1;
cpu_breakpoint_remove_all(env, BP_CPU);
cpu_watchpoint_remove_all(env, BP_CPU);
+
+ trace_vcpu_reset(env);
}
void cpu_x86_close(CPUX86State *env)
diff --git a/target-lm32/helper.c b/target-lm32/helper.c
index fc0b444..10ad3b5 100644
--- a/target-lm32/helper.c
+++ b/target-lm32/helper.c
@@ -24,6 +24,7 @@
#include "config.h"
#include "cpu.h"
#include "host-utils.h"
+#include "trace.h"
int cpu_lm32_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
int mmu_idx)
@@ -251,5 +252,7 @@ void cpu_reset(CPUState *env)
/* reset cpu state */
memset(env, 0, offsetof(CPULM32State, breakpoints));
+
+ trace_vcpu_reset(env);
}
diff --git a/target-m68k/helper.c b/target-m68k/helper.c
index 123e1d9..3a89f29 100644
--- a/target-m68k/helper.c
+++ b/target-m68k/helper.c
@@ -25,6 +25,7 @@
#include "cpu.h"
#include "qemu-common.h"
#include "gdbstub.h"
+#include "trace.h"
#include "helper.h"
@@ -165,6 +166,8 @@ void cpu_reset(CPUM68KState *env)
/* TODO: We should set PC from the interrupt vector. */
env->pc = 0;
tlb_flush(env, 1);
+
+ trace_vcpu_reset(env);
}
CPUM68KState *cpu_m68k_init(const char *cpu_model)
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 366fd3e..f976311 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -30,6 +30,7 @@
#include "helper.h"
#include "microblaze-decode.h"
#include "qemu-common.h"
+#include "trace.h"
#define GEN_HELPER 1
#include "helper.h"
@@ -1943,6 +1944,8 @@ void cpu_reset (CPUState *env)
env->mmu.c_mmu_tlb_access = 3;
env->mmu.c_mmu_zones = 16;
#endif
+
+ trace_vcpu_reset(env);
}
void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index d5b1c76..73c4c5e 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -30,6 +30,7 @@
#include "disas.h"
#include "tcg-op.h"
#include "qemu-common.h"
+#include "trace.h"
#include "helper.h"
#define GEN_HELPER 1
@@ -12846,6 +12847,8 @@ void cpu_reset (CPUMIPSState *env)
}
#endif
env->exception_index = EXCP_NONE;
+
+ trace_vcpu_reset(env);
}
void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index 137a494..84bf282 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -28,6 +28,7 @@
#include "kvm.h"
#include "kvm_ppc.h"
#include "cpus.h"
+#include "trace.h"
//#define DEBUG_MMU
//#define DEBUG_BATS
@@ -3175,6 +3176,8 @@ void cpu_reset(CPUPPCState *env)
env->error_code = 0;
/* Flush all TLBs */
tlb_flush(env, 1);
+
+ trace_vcpu_reset(env);
}
CPUPPCState *cpu_ppc_init (const char *cpu_model)
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index 10cc9dd..d0ccc86 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -29,6 +29,7 @@
#ifndef CONFIG_USER_ONLY
#include "sysemu.h"
#endif
+#include "trace.h"
//#define DEBUG_S390
//#define DEBUG_S390_PTE
@@ -135,6 +136,8 @@ void cpu_reset(CPUS390XState *env)
/* FIXME: reset vector? */
tlb_flush(env, 1);
s390_add_running_cpu(env);
+
+ trace_vcpu_reset(env);
}
#ifndef CONFIG_USER_ONLY
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index bad3577..2487451 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -30,6 +30,7 @@
#include "disas.h"
#include "tcg-op.h"
#include "qemu-common.h"
+#include "trace.h"
#include "helper.h"
#define GEN_HELPER 1
@@ -205,6 +206,8 @@ void cpu_reset(CPUSH4State * env)
set_flush_to_zero(1, &env->fp_status);
#endif
set_default_nan_mode(1, &env->fp_status);
+
+ trace_vcpu_reset(env);
}
typedef struct {
diff --git a/target-sparc/cpu_init.c b/target-sparc/cpu_init.c
index c7269b5..074932e 100644
--- a/target-sparc/cpu_init.c
+++ b/target-sparc/cpu_init.c
@@ -64,6 +64,8 @@ void cpu_reset(CPUSPARCState *env)
env->npc = env->pc + 4;
#endif
env->cache_control = 0;
+
+ trace_vcpu_reset(env);
}
static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 037a72c..de12c2b 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -21,6 +21,8 @@
#include "host-utils.h"
#include "helper.h"
#include "sysemu.h"
+#include "qemu-common.h"
+#include "trace.h"
void helper_raise_exception(CPUState *env, int tt)
{
diff --git a/trace-events b/trace-events
index 1a2d302..8278959 100644
--- a/trace-events
+++ b/trace-events
@@ -638,3 +638,5 @@ win_helper_retry(uint32_t tl) "tl=%d"
# Create a new vCPU (CPUState structure)
vcpu_init(void *vcpu) "%p"
+# Reset the state of a vCPU
+vcpu_reset(void *vcpu) "%p"
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH 4/7] trace: [all] Add "vbbl" TCG tracing event
2011-12-09 20:14 [Qemu-devel] [PATCH 0/7] trace: Add some simple TCG tracing events Lluís Vilanova
` (2 preceding siblings ...)
2011-12-09 20:15 ` [Qemu-devel] [PATCH 3/7] trace: Add "vcpu_reset" event Lluís Vilanova
@ 2011-12-09 20:15 ` Lluís Vilanova
2011-12-09 20:15 ` [Qemu-devel] [PATCH 5/7] [all] Trivial 'tcg_gen_debug_insn_start' unification in 'gen_intermediate_code_internal' Lluís Vilanova
` (2 subsequent siblings)
6 siblings, 0 replies; 8+ messages in thread
From: Lluís Vilanova @ 2011-12-09 20:15 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
---
target-alpha/translate.c | 1 +
target-arm/translate.c | 1 +
target-cris/translate.c | 1 +
target-i386/translate.c | 1 +
target-lm32/translate.c | 1 +
target-m68k/translate.c | 1 +
target-microblaze/translate.c | 1 +
target-mips/translate.c | 1 +
target-ppc/translate.c | 1 +
target-s390x/translate.c | 1 +
target-sh4/translate.c | 1 +
target-sparc/translate.c | 1 +
target-unicore32/translate.c | 1 +
target-xtensa/translate.c | 1 +
trace-events | 13 +++++++++++++
15 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index a961159..18f5428 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -3368,6 +3368,7 @@ static inline void gen_intermediate_code_internal(CPUState *env,
max_insns = CF_COUNT_MASK;
gen_icount_start();
+ gen_helper_trace_vbbl(pc_start);
do {
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 0f35b60..b0b36f3 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -9877,6 +9877,7 @@ static inline void gen_intermediate_code_internal(CPUState *env,
max_insns = CF_COUNT_MASK;
gen_icount_start();
+ gen_helper_trace_vbbl(pc_start);
tcg_clear_temp_count();
diff --git a/target-cris/translate.c b/target-cris/translate.c
index a871e7f..cac22c9 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3266,6 +3266,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
max_insns = CF_COUNT_MASK;
gen_icount_start();
+ gen_helper_trace_vbbl(pc_start);
do
{
check_breakpoint(env, dc);
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 1ef8d16..7192ce9 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -7797,6 +7797,7 @@ static inline void gen_intermediate_code_internal(CPUState *env,
max_insns = CF_COUNT_MASK;
gen_icount_start();
+ gen_helper_trace_vbbl(pc_start);
for(;;) {
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 0be105d..2535fb7 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -1053,6 +1053,7 @@ static void gen_intermediate_code_internal(CPUState *env,
}
gen_icount_start();
+ gen_helper_trace_vbbl(pc_start);
do {
check_breakpoint(env, dc);
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index fe750e2..9cb8139 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2990,6 +2990,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
max_insns = CF_COUNT_MASK;
gen_icount_start();
+ gen_helper_trace_vbbl(pc_start);
do {
pc_offset = dc->pc - pc_start;
gen_throws_exception = NULL;
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index f976311..6b6a593 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1658,6 +1658,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
max_insns = CF_COUNT_MASK;
gen_icount_start();
+ gen_helper_trace_vbbl(pc_start);
do
{
#if SIM_COMPAT
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 73c4c5e..0076058 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12414,6 +12414,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
max_insns = CF_COUNT_MASK;
LOG_DISAS("\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags);
gen_icount_start();
+ gen_helper_trace_vbbl(pc_start);
while (ctx.bstate == BS_NONE) {
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 66eae30..af78360 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9463,6 +9463,7 @@ static inline void gen_intermediate_code_internal(CPUState *env,
max_insns = CF_COUNT_MASK;
gen_icount_start();
+ gen_helper_trace_vbbl(pc_start);
/* Set env in case of segfault during code fetch */
while (ctx.exception == POWERPC_EXCP_NONE && gen_opc_ptr < gen_opc_end) {
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 9fef77c..c2a04a5 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -5147,6 +5147,7 @@ static inline void gen_intermediate_code_internal(CPUState *env,
}
gen_icount_start();
+ gen_helper_trace_vbbl(pc_start);
do {
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 2487451..d75c065 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1968,6 +1968,7 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
gen_icount_start();
+ gen_helper_trace_vbbl(pc_start);
while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index d261112..415d996 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -5268,6 +5268,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
if (max_insns == 0)
max_insns = CF_COUNT_MASK;
gen_icount_start();
+ gen_helper_trace_vbbl(pc_start);
do {
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 4d0aa43..8edca98 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -1888,6 +1888,7 @@ static inline void gen_intermediate_code_internal(CPUState *env,
}
gen_icount_start();
+ gen_helper_trace_vbbl(pc_start);
do {
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 8b9d9ed..3f741ac 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -2434,6 +2434,7 @@ static void gen_intermediate_code_internal(
reset_used_window(&dc);
gen_icount_start();
+ gen_helper_trace_vbbl(pc_start);
if (env->singlestep_enabled && env->exception_taken) {
env->exception_taken = 0;
diff --git a/trace-events b/trace-events
index 8278959..6dac6ae 100644
--- a/trace-events
+++ b/trace-events
@@ -640,3 +640,16 @@ win_helper_retry(uint32_t tl) "tl=%d"
vcpu_init(void *vcpu) "%p"
# Reset the state of a vCPU
vcpu_reset(void *vcpu) "%p"
+
+
+## Guest events
+
+# Start BBL execution
+#
+# Note: QEMU's basic blocks do not necessarily finish in a control flow
+# instruction.
+#
+# Targets: all
+#
+# vaddr : starting virtual address
+disable tcg vbbl(uint64_t vaddr) "vaddr=0x%016"PRIx64
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH 5/7] [all] Trivial 'tcg_gen_debug_insn_start' unification in 'gen_intermediate_code_internal'
2011-12-09 20:14 [Qemu-devel] [PATCH 0/7] trace: Add some simple TCG tracing events Lluís Vilanova
` (3 preceding siblings ...)
2011-12-09 20:15 ` [Qemu-devel] [PATCH 4/7] trace: [all] Add "vbbl" TCG tracing event Lluís Vilanova
@ 2011-12-09 20:15 ` Lluís Vilanova
2011-12-09 20:16 ` [Qemu-devel] [PATCH 6/7] trace: [all] Add "vfetch" TCG tracing event Lluís Vilanova
2011-12-09 20:16 ` [Qemu-devel] [PATCH 7/7] trace: [all] Add "vmem" " Lluís Vilanova
6 siblings, 0 replies; 8+ messages in thread
From: Lluís Vilanova @ 2011-12-09 20:15 UTC (permalink / raw)
To: qemu-devel
Make sure 'tcg_gen_debug_insn_start' is always called in
'gen_intermediate_code_internal' and after calls to 'gen_io_start' (before the
instruction decoding).
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
---
target-alpha/translate.c | 11 ++++++-----
target-cris/translate.c | 12 +++++++-----
target-i386/translate.c | 5 +++--
target-lm32/translate.c | 7 +++----
target-m68k/translate.c | 6 +++++-
target-microblaze/translate.c | 6 +++---
target-mips/translate.c | 6 +++---
target-ppc/translate.c | 6 ++++--
target-s390x/translate.c | 4 ++++
target-sh4/translate.c | 8 ++++----
target-sparc/translate.c | 6 ++++--
target-unicore32/translate.c | 3 +++
target-xtensa/translate.c | 7 +++----
13 files changed, 52 insertions(+), 35 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 18f5428..5efc605 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -3389,15 +3389,16 @@ static inline void gen_intermediate_code_internal(CPUState *env,
gen_opc_instr_start[lj] = 1;
gen_opc_icount[lj] = num_insns;
}
- if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
+ if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start();
- insn = ldl_code(ctx.pc);
- num_insns++;
-
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ }
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
tcg_gen_debug_insn_start(ctx.pc);
}
+ insn = ldl_code(ctx.pc);
+ num_insns++;
+
ctx.pc += 4;
ret = translate_one(ctxp, insn);
diff --git a/target-cris/translate.c b/target-cris/translate.c
index cac22c9..f6bebea 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3080,9 +3080,6 @@ static unsigned int crisv32_decoder(DisasContext *dc)
int insn_len = 2;
int i;
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
- tcg_gen_debug_insn_start(dc->pc);
-
/* Load a halfword onto the instruction register. */
dc->ir = cris_fetch(dc, dc->pc, 2, 0);
@@ -3291,9 +3288,14 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
- dc->clear_x = 1;
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ tcg_gen_debug_insn_start(dc->pc);
+ }
+
+ dc->clear_x = 1;
+
+ insn_len = dc->decoder(dc);
- insn_len = dc->decoder(dc);
dc->ppc = dc->pc;
dc->pc += insn_len;
if (dc->clear_x)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 7192ce9..9818ebb 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -4081,8 +4081,6 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
target_ulong next_eip, tval;
int rex_w, rex_r;
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
- tcg_gen_debug_insn_start(pc_start);
s->pc = pc_start;
prefixes = 0;
aflag = s->code32;
@@ -7822,6 +7820,9 @@ static inline void gen_intermediate_code_internal(CPUState *env,
}
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ tcg_gen_debug_insn_start(pc_ptr);
+ }
pc_ptr = disas_insn(dc, pc_ptr);
num_insns++;
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 2535fb7..c0d9195 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -952,10 +952,6 @@ static inline void decode(DisasContext *dc)
{
uint32_t ir;
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
- tcg_gen_debug_insn_start(dc->pc);
- }
-
dc->ir = ir = ldl_code(dc->pc);
LOG_DIS("%8.8x\t", dc->ir);
@@ -1076,6 +1072,9 @@ static void gen_intermediate_code_internal(CPUState *env,
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start();
}
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ tcg_gen_debug_insn_start(dc->pc);
+ }
decode(dc);
dc->pc += 4;
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 9cb8139..5e735f3 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3018,8 +3018,12 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
}
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ tcg_gen_debug_insn_start(dc->pc);
+ }
+
dc->insn_pc = dc->pc;
- disas_m68k_insn(env, dc);
+ disas_m68k_insn(env, dc);
num_insns++;
} while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
!env->singlestep_enabled &&
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 6b6a593..a1a9ce6 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1550,9 +1550,6 @@ static inline void decode(DisasContext *dc)
uint32_t ir;
int i;
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
- tcg_gen_debug_insn_start(dc->pc);
-
dc->ir = ir = ldl_code(dc->pc);
LOG_DIS("%8.8x\t", dc->ir);
@@ -1686,6 +1683,9 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ tcg_gen_debug_insn_start(dc->pc);
+ }
dc->clear_imm = 1;
decode(dc);
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 0076058..6f67b36 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -11715,9 +11715,6 @@ static void decode_opc (CPUState *env, DisasContext *ctx, int *is_branch)
gen_set_label(l1);
}
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
- tcg_gen_debug_insn_start(ctx->pc);
-
op = MASK_OP_MAJOR(ctx->opcode);
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
@@ -12444,6 +12441,9 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
}
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ tcg_gen_debug_insn_start(ctx.pc);
+ }
is_branch = 0;
if (!(ctx.hflags & MIPS_HFLAG_M16)) {
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index af78360..c515ea4 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9490,6 +9490,10 @@ static inline void gen_intermediate_code_internal(CPUState *env,
ctx.nip, ctx.mem_idx, (int)msr_ir);
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ tcg_gen_debug_insn_start(ctx.nip);
+ }
+
if (unlikely(ctx.le_mode)) {
ctx.opcode = bswap32(ldl_code(ctx.nip));
} else {
@@ -9498,8 +9502,6 @@ static inline void gen_intermediate_code_internal(CPUState *env,
LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
opc3(ctx.opcode), little_endian ? "little" : "big");
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
- tcg_gen_debug_insn_start(ctx.nip);
ctx.nip += 4;
table = env->opcodes;
num_insns++;
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index c2a04a5..f0b877e 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -5174,6 +5174,10 @@ static inline void gen_intermediate_code_internal(CPUState *env,
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start();
}
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ tcg_gen_debug_insn_start(dc.pc);
+ }
+
#if defined(S390X_DEBUG_DISAS_VERBOSE)
LOG_DISAS("pc " TARGET_FMT_lx "\n",
dc.pc);
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index d75c065..6c1872c 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1904,10 +1904,6 @@ static void decode_opc(DisasContext * ctx)
{
uint32_t old_flags = ctx->flags;
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
- tcg_gen_debug_insn_start(ctx->pc);
- }
-
_decode_opc(ctx);
if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
@@ -1995,6 +1991,10 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
}
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ tcg_gen_debug_insn_start(ctx.pc);
+ }
+
#if 0
fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
fflush(stderr);
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 415d996..5c7cca0 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -2381,8 +2381,6 @@ static void disas_sparc_insn(DisasContext * dc)
TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
target_long simm;
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
- tcg_gen_debug_insn_start(dc->pc);
insn = ldl_code(dc->pc);
opc = GET_FIELD(insn, 0, 1);
@@ -5297,6 +5295,10 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
}
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ tcg_gen_debug_insn_start(dc->pc);
+ }
+
last_pc = dc->pc;
disas_sparc_insn(dc);
num_insns++;
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 8edca98..74172ea 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -1920,6 +1920,9 @@ static inline void gen_intermediate_code_internal(CPUState *env,
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start();
}
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ tcg_gen_debug_insn_start(dc->pc);
+ }
disas_uc32_insn(env, dc);
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 3f741ac..96db089 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -2458,15 +2458,14 @@ static void gen_intermediate_code_internal(
gen_opc_icount[lj] = insn_count;
}
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
- tcg_gen_debug_insn_start(dc.pc);
- }
-
++dc.ccount_delta;
if (insn_count + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
gen_io_start();
}
+ if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
+ tcg_gen_debug_insn_start(dc.pc);
+ }
disas_xtensa_insn(&dc);
++insn_count;
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH 6/7] trace: [all] Add "vfetch" TCG tracing event
2011-12-09 20:14 [Qemu-devel] [PATCH 0/7] trace: Add some simple TCG tracing events Lluís Vilanova
` (4 preceding siblings ...)
2011-12-09 20:15 ` [Qemu-devel] [PATCH 5/7] [all] Trivial 'tcg_gen_debug_insn_start' unification in 'gen_intermediate_code_internal' Lluís Vilanova
@ 2011-12-09 20:16 ` Lluís Vilanova
2011-12-09 20:16 ` [Qemu-devel] [PATCH 7/7] trace: [all] Add "vmem" " Lluís Vilanova
6 siblings, 0 replies; 8+ messages in thread
From: Lluís Vilanova @ 2011-12-09 20:16 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
---
target-alpha/translate.c | 2 ++
target-arm/translate.c | 2 ++
target-cris/translate.c | 2 ++
target-i386/translate.c | 2 ++
target-lm32/translate.c | 2 ++
target-m68k/translate.c | 2 ++
target-microblaze/translate.c | 2 ++
target-mips/translate.c | 2 ++
target-ppc/translate.c | 2 ++
target-s390x/translate.c | 3 +++
target-sh4/translate.c | 2 ++
target-sparc/translate.c | 2 ++
target-unicore32/translate.c | 2 ++
target-xtensa/translate.c | 2 ++
trace-events | 7 +++++++
15 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index 5efc605..375cfa4 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -3396,6 +3396,8 @@ static inline void gen_intermediate_code_internal(CPUState *env,
tcg_gen_debug_insn_start(ctx.pc);
}
+ gen_helper_trace_vfetch(ctx.pc);
+
insn = ldl_code(ctx.pc);
num_insns++;
diff --git a/target-arm/translate.c b/target-arm/translate.c
index b0b36f3..d0b386a 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -9972,6 +9972,8 @@ static inline void gen_intermediate_code_internal(CPUState *env,
tcg_gen_debug_insn_start(dc->pc);
}
+ gen_helper_trace_vfetch(dc->pc);
+
if (dc->thumb) {
disas_thumb_insn(env, dc);
if (dc->condexec_mask) {
diff --git a/target-cris/translate.c b/target-cris/translate.c
index f6bebea..4abd1d7 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3294,6 +3294,8 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
dc->clear_x = 1;
+ gen_helper_trace_vfetch(dc->pc);
+
insn_len = dc->decoder(dc);
dc->ppc = dc->pc;
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 9818ebb..9ae8c34 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -7824,6 +7824,8 @@ static inline void gen_intermediate_code_internal(CPUState *env,
tcg_gen_debug_insn_start(pc_ptr);
}
+ gen_helper_trace_vfetch(pc_ptr);
+
pc_ptr = disas_insn(dc, pc_ptr);
num_insns++;
/* stop translation if indicated */
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index c0d9195..f57bd70 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -1076,6 +1076,8 @@ static void gen_intermediate_code_internal(CPUState *env,
tcg_gen_debug_insn_start(dc->pc);
}
+ gen_helper_trace_vfetch(dc->pc);
+
decode(dc);
dc->pc += 4;
num_insns++;
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 5e735f3..ce92a7f 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3022,6 +3022,8 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
tcg_gen_debug_insn_start(dc->pc);
}
+ gen_helper_trace_vfetch(dc->pc);
+
dc->insn_pc = dc->pc;
disas_m68k_insn(env, dc);
num_insns++;
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index a1a9ce6..53b6e73 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1687,6 +1687,8 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
tcg_gen_debug_insn_start(dc->pc);
}
+ gen_helper_trace_vfetch(dc->pc);
+
dc->clear_imm = 1;
decode(dc);
if (dc->clear_imm)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 6f67b36..3318e88 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -12445,6 +12445,8 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
tcg_gen_debug_insn_start(ctx.pc);
}
+ gen_helper_trace_vfetch(ctx.pc);
+
is_branch = 0;
if (!(ctx.hflags & MIPS_HFLAG_M16)) {
ctx.opcode = ldl_code(ctx.pc);
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index c515ea4..8d898d0 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9494,6 +9494,8 @@ static inline void gen_intermediate_code_internal(CPUState *env,
tcg_gen_debug_insn_start(ctx.nip);
}
+ gen_helper_trace_vfetch(ctx.nip);
+
if (unlikely(ctx.le_mode)) {
ctx.opcode = bswap32(ldl_code(ctx.nip));
} else {
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index f0b877e..a8ac111 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -5182,6 +5182,9 @@ static inline void gen_intermediate_code_internal(CPUState *env,
LOG_DISAS("pc " TARGET_FMT_lx "\n",
dc.pc);
#endif
+
+ gen_helper_trace_vfetch(dc.pc);
+
disas_s390_insn(&dc);
num_insns++;
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 6c1872c..00cbe28 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1999,6 +1999,8 @@ gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb,
fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
fflush(stderr);
#endif
+ gen_helper_trace_vfetch(ctx.pc);
+
ctx.opcode = lduw_code(ctx.pc);
decode_opc(&ctx);
num_insns++;
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 5c7cca0..cdd7dbd 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -5299,6 +5299,8 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
tcg_gen_debug_insn_start(dc->pc);
}
+ gen_helper_trace_vfetch(dc->pc);
+
last_pc = dc->pc;
disas_sparc_insn(dc);
num_insns++;
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index 74172ea..33a201b 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -1924,6 +1924,8 @@ static inline void gen_intermediate_code_internal(CPUState *env,
tcg_gen_debug_insn_start(dc->pc);
}
+ gen_helper_trace_vfetch(dc->pc);
+
disas_uc32_insn(env, dc);
if (num_temps) {
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 96db089..c020ffa 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -2467,6 +2467,8 @@ static void gen_intermediate_code_internal(
tcg_gen_debug_insn_start(dc.pc);
}
+ gen_helper_trace_vfetch(dc.pc);
+
disas_xtensa_insn(&dc);
++insn_count;
if (env->singlestep_enabled) {
diff --git a/trace-events b/trace-events
index 6dac6ae..9b315c5 100644
--- a/trace-events
+++ b/trace-events
@@ -653,3 +653,10 @@ vcpu_reset(void *vcpu) "%p"
#
# vaddr : starting virtual address
disable tcg vbbl(uint64_t vaddr) "vaddr=0x%016"PRIx64
+
+# Start instruction execution
+#
+# Targets: all
+#
+# vaddr : instruction's virtual address
+disable tcg vfetch(uint64_t vaddr) "vaddr=0x%016"PRIx64
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Qemu-devel] [PATCH 7/7] trace: [all] Add "vmem" TCG tracing event
2011-12-09 20:14 [Qemu-devel] [PATCH 0/7] trace: Add some simple TCG tracing events Lluís Vilanova
` (5 preceding siblings ...)
2011-12-09 20:16 ` [Qemu-devel] [PATCH 6/7] trace: [all] Add "vfetch" TCG tracing event Lluís Vilanova
@ 2011-12-09 20:16 ` Lluís Vilanova
6 siblings, 0 replies; 8+ messages in thread
From: Lluís Vilanova @ 2011-12-09 20:16 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
---
cpu-all.h | 58 +++++++++++++++++++------------------
exec-all.h | 3 ++
| 15 ++++++++++
tcg/tcg-op.h | 6 ++++
trace-events | 9 ++++++
trace/tcg-op-internal.h | 74 +++++++++++++++++++++++++++++++++++++++++++++++
6 files changed, 137 insertions(+), 28 deletions(-)
create mode 100644 trace/tcg-op-internal.h
diff --git a/cpu-all.h b/cpu-all.h
index 5f47ab8..5a4c2f6 100644
--- a/cpu-all.h
+++ b/cpu-all.h
@@ -243,21 +243,23 @@ extern unsigned long reserved_va;
#if defined(CONFIG_USER_ONLY)
+#include "trace.h"
+
/* if user mode, no other memory access functions */
-#define ldub(p) ldub_raw(p)
-#define ldsb(p) ldsb_raw(p)
-#define lduw(p) lduw_raw(p)
-#define ldsw(p) ldsw_raw(p)
-#define ldl(p) ldl_raw(p)
-#define ldq(p) ldq_raw(p)
-#define ldfl(p) ldfl_raw(p)
-#define ldfq(p) ldfq_raw(p)
-#define stb(p, v) stb_raw(p, v)
-#define stw(p, v) stw_raw(p, v)
-#define stl(p, v) stl_raw(p, v)
-#define stq(p, v) stq_raw(p, v)
-#define stfl(p, v) stfl_raw(p, v)
-#define stfq(p, v) stfq_raw(p, v)
+#define ldub(p) ({ trace_vmem(p, 1, 0); ldub_raw(p); })
+#define ldsb(p) ({ trace_vmem(p, 1, 0); ldsb_raw(p); })
+#define lduw(p) ({ trace_vmem(p, 2, 0); lduw_raw(p); })
+#define ldsw(p) ({ trace_vmem(p, 2, 0); ldsw_raw(p); })
+#define ldl(p) ({ trace_vmem(p, 4, 0); ldl_raw(p); })
+#define ldq(p) ({ trace_vmem(p, 8, 0); ldq_raw(p); })
+#define ldfl(p) ({ trace_vmem(p, 4, 0); ldfl_raw(p); })
+#define ldfq(p) ({ trace_vmem(p, 8, 0); ldfq_raw(p); })
+#define stb(p, v) ({ trace_vmem(p, 1, 1); stb_raw(p, v); })
+#define stw(p, v) ({ trace_vmem(p, 2, 1); stw_raw(p, v); })
+#define stl(p, v) ({ trace_vmem(p, 4, 1); stl_raw(p, v); })
+#define stq(p, v) ({ trace_vmem(p, 8, 1); stq_raw(p, v); })
+#define stfl(p, v) ({ trace_vmem(p, 4, 1); stfl_raw(p, v); })
+#define stfq(p, v) ({ trace_vmem(p, 8, 1); stfq_raw(p, v); })
#define ldub_code(p) ldub_raw(p)
#define ldsb_code(p) ldsb_raw(p)
@@ -266,20 +268,20 @@ extern unsigned long reserved_va;
#define ldl_code(p) ldl_raw(p)
#define ldq_code(p) ldq_raw(p)
-#define ldub_kernel(p) ldub_raw(p)
-#define ldsb_kernel(p) ldsb_raw(p)
-#define lduw_kernel(p) lduw_raw(p)
-#define ldsw_kernel(p) ldsw_raw(p)
-#define ldl_kernel(p) ldl_raw(p)
-#define ldq_kernel(p) ldq_raw(p)
-#define ldfl_kernel(p) ldfl_raw(p)
-#define ldfq_kernel(p) ldfq_raw(p)
-#define stb_kernel(p, v) stb_raw(p, v)
-#define stw_kernel(p, v) stw_raw(p, v)
-#define stl_kernel(p, v) stl_raw(p, v)
-#define stq_kernel(p, v) stq_raw(p, v)
-#define stfl_kernel(p, v) stfl_raw(p, v)
-#define stfq_kernel(p, vt) stfq_raw(p, v)
+#define ldub_kernel(p) ({ trace_vmem(p, 1, 0); ldub_raw(p); })
+#define ldsb_kernel(p) ({ trace_vmem(p, 1, 0); ldsb_raw(p); })
+#define lduw_kernel(p) ({ trace_vmem(p, 2, 0); lduw_raw(p); })
+#define ldsw_kernel(p) ({ trace_vmem(p, 2, 0); ldsw_raw(p); })
+#define ldl_kernel(p) ({ trace_vmem(p, 4, 0); ldl_raw(p); })
+#define ldq_kernel(p) ({ trace_vmem(p, 8, 0); ldq_raw(p); })
+#define ldfl_kernel(p) ({ trace_vmem(p, 4, 0); ldfl_raw(p); })
+#define ldfq_kernel(p) ({ trace_vmem(p, 8, 0); ldfq_raw(p); })
+#define stb_kernel(p, v) ({ trace_vmem(p, 1, 1); stb_raw(p, v); })
+#define stw_kernel(p, v) ({ trace_vmem(p, 2, 1); stw_raw(p, v); })
+#define stl_kernel(p, v) ({ trace_vmem(p, 4, 1); stl_raw(p, v); })
+#define stq_kernel(p, v) ({ trace_vmem(p, 8, 1); stq_raw(p, v); })
+#define stfl_kernel(p, v) ({ trace_vmem(p, 4, 1); stfl_raw(p, v); })
+#define stfq_kernel(p, vt) ({ trace_vmem(p, 8, 1); stfq_raw(p, v); })
#endif /* defined(CONFIG_USER_ONLY) */
diff --git a/exec-all.h b/exec-all.h
index c211242..2c97ff1 100644
--- a/exec-all.h
+++ b/exec-all.h
@@ -309,6 +309,8 @@ void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
#include "softmmu_defs.h"
#define ACCESS_TYPE (NB_MMU_MODES + 1)
+/* do not trace '*_code' accesses during instruction disassembly */
+#define TRACE_TCG_CODE_ACCESSOR 1
#define MEMSUFFIX _code
#define env cpu_single_env
@@ -325,6 +327,7 @@ void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
#include "softmmu_header.h"
#undef ACCESS_TYPE
+#undef TRACE_TCG_CODE_ACCESSOR
#undef MEMSUFFIX
#undef env
--git a/softmmu_header.h b/softmmu_header.h
index 818d7b6..a50c71f 100644
--- a/softmmu_header.h
+++ b/softmmu_header.h
@@ -25,6 +25,9 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
+
+#include "trace.h"
+
#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
@@ -88,6 +91,10 @@ static inline RES_TYPE glue(glue(ld, USUFFIX), MEMSUFFIX)(target_ulong ptr)
unsigned long physaddr;
int mmu_idx;
+#if !defined(TRACE_TCG_CODE_ACCESSOR)
+ trace_vmem(ptr, DATA_SIZE, 0);
+#endif
+
addr = ptr;
page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
mmu_idx = CPU_MMU_INDEX;
@@ -109,6 +116,10 @@ static inline int glue(glue(lds, SUFFIX), MEMSUFFIX)(target_ulong ptr)
unsigned long physaddr;
int mmu_idx;
+#if !defined(TRACE_TCG_CODE_ACCESSOR)
+ trace_vmem(ptr, DATA_SIZE, 0);
+#endif
+
addr = ptr;
page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
mmu_idx = CPU_MMU_INDEX;
@@ -134,6 +145,10 @@ static inline void glue(glue(st, SUFFIX), MEMSUFFIX)(target_ulong ptr, RES_TYPE
unsigned long physaddr;
int mmu_idx;
+#if !defined(TRACE_TCG_CODE_ACCESSOR)
+ trace_vmem(ptr, DATA_SIZE, 1);
+#endif
+
addr = ptr;
page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
mmu_idx = CPU_MMU_INDEX;
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 82e04e7..8b738f0 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -2522,3 +2522,9 @@ static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
TCGV_PTR_TO_NAT(A), (B))
#define tcg_gen_ext_i32_ptr(R, A) tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A))
#endif /* TCG_TARGET_REG_BITS != 32 */
+
+/* To avoid a circular dependency with helper.h, overload tcg_gen_qemu_*
+ * routines with preprocessor macros to insert TCG virtual memory access
+ * tracing.
+ */
+#include "trace/tcg-op-internal.h"
diff --git a/trace-events b/trace-events
index 9b315c5..14ea7ef 100644
--- a/trace-events
+++ b/trace-events
@@ -660,3 +660,12 @@ disable tcg vbbl(uint64_t vaddr) "vaddr=0x%016"PRIx64
#
# vaddr : instruction's virtual address
disable tcg vfetch(uint64_t vaddr) "vaddr=0x%016"PRIx64
+
+# Start virtual memory access (before any potential access violation)
+#
+# Targets: all
+#
+# vaddr : access' virtual address
+# size : access' size (bytes)
+# write : whether the access is a write
+disable tcg vmem(TCGv vaddr, uint8_t size, uint8_t write) "vaddr=0x%016"PRIx64" size=%d write=%d"
diff --git a/trace/tcg-op-internal.h b/trace/tcg-op-internal.h
new file mode 100644
index 0000000..e19657d
--- /dev/null
+++ b/trace/tcg-op-internal.h
@@ -0,0 +1,74 @@
+/* -*- mode: c -*-
+ * Copyright (c) 2011 Lluís Vilanova <vilanova@ac.upc.edu>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+/**
+ * @file Capture TCG code generation for virtual memory accesses.
+ *
+ * Assumes that no other lower-level call will be performed by target
+ * architecture disassembly code on TCG instructions for accessing memory.
+ */
+
+#ifndef TRACE__TCG_OP_INTERNAL_H
+#define TRACE__TCG_OP_INTERNAL_H
+
+#define tcg_gen_qemu_ld8u(arg, addr, mem_index) \
+ do { \
+ gen_helper_trace_vmem(addr, 1, 0); \
+ (tcg_gen_qemu_ld8u)(arg, addr, mem_index); \
+ } while (0)
+#define tcg_gen_qemu_ld8s(arg, addr, mem_index) \
+ do { \
+ gen_helper_trace_vmem(addr, 1, 0); \
+ (tcg_gen_qemu_ld8s)(arg, addr, mem_index); \
+ } while (0)
+#define tcg_gen_qemu_ld16u(arg, addr, mem_index) \
+ do { \
+ gen_helper_trace_vmem(addr, 2, 0); \
+ (tcg_gen_qemu_ld16u)(arg, addr, mem_index); \
+ } while (0)
+#define tcg_gen_qemu_ld16s(arg, addr, mem_index) \
+ do { \
+ gen_helper_trace_vmem(addr, 2, 0); \
+ (tcg_gen_qemu_ld16s)(arg, addr, mem_index); \
+ } while (0)
+#define tcg_gen_qemu_ld32u(arg, addr, mem_index) \
+ do { \
+ gen_helper_trace_vmem(addr, 4, 0); \
+ (tcg_gen_qemu_ld32u)(arg, addr, mem_index); \
+ } while (0)
+#define tcg_gen_qemu_ld32s(arg, addr, mem_index) \
+ do { \
+ gen_helper_trace_vmem(addr, 4, 0); \
+ (tcg_gen_qemu_ld32s)(arg, addr, mem_index); \
+ } while (0)
+#define tcg_gen_qemu_ld64(arg, addr, mem_index) \
+ do { \
+ gen_helper_trace_vmem(addr, 8, 0); \
+ (tcg_gen_qemu_ld64)(arg, addr, mem_index); \
+ } while (0)
+#define tcg_gen_qemu_st8(arg, addr, mem_index) \
+ do { \
+ gen_helper_trace_vmem(addr, 1, 1); \
+ (tcg_gen_qemu_st8)(arg, addr, mem_index); \
+ } while (0)
+#define tcg_gen_qemu_st16(arg, addr, mem_index) \
+ do { \
+ gen_helper_trace_vmem(addr, 2, 1); \
+ (tcg_gen_qemu_st16)(arg, addr, mem_index); \
+ } while (0)
+#define tcg_gen_qemu_st32(arg, addr, mem_index) \
+ do { \
+ gen_helper_trace_vmem(addr, 4, 1); \
+ (tcg_gen_qemu_st32)(arg, addr, mem_index); \
+ } while (0)
+#define tcg_gen_qemu_st64(arg, addr, mem_index) \
+ do { \
+ gen_helper_trace_vmem(addr, 8, 1); \
+ (tcg_gen_qemu_st64)(arg, addr, mem_index); \
+ } while (0)
+
+#endif /* TRACE__TCG_OP_INTERNAL_H */
^ permalink raw reply related [flat|nested] 8+ messages in thread
end of thread, other threads:[~2011-12-09 20:16 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-12-09 20:14 [Qemu-devel] [PATCH 0/7] trace: Add some simple TCG tracing events Lluís Vilanova
2011-12-09 20:14 ` [Qemu-devel] [PATCH 1/7] Make 'qemu_init_vcpu' a function (instead of a macro) Lluís Vilanova
2011-12-09 20:15 ` [Qemu-devel] [PATCH 2/7] trace: Add "vcpu_init" event Lluís Vilanova
2011-12-09 20:15 ` [Qemu-devel] [PATCH 3/7] trace: Add "vcpu_reset" event Lluís Vilanova
2011-12-09 20:15 ` [Qemu-devel] [PATCH 4/7] trace: [all] Add "vbbl" TCG tracing event Lluís Vilanova
2011-12-09 20:15 ` [Qemu-devel] [PATCH 5/7] [all] Trivial 'tcg_gen_debug_insn_start' unification in 'gen_intermediate_code_internal' Lluís Vilanova
2011-12-09 20:16 ` [Qemu-devel] [PATCH 6/7] trace: [all] Add "vfetch" TCG tracing event Lluís Vilanova
2011-12-09 20:16 ` [Qemu-devel] [PATCH 7/7] trace: [all] Add "vmem" " Lluís Vilanova
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