From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:49239) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RZ6rP-0000Gn-8W for qemu-devel@nongnu.org; Fri, 09 Dec 2011 15:16:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RZ6rN-0003JG-B9 for qemu-devel@nongnu.org; Fri, 09 Dec 2011 15:15:59 -0500 Received: from gw.ac.upc.edu ([147.83.30.3]:40203) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RZ6rM-0003J2-S9 for qemu-devel@nongnu.org; Fri, 09 Dec 2011 15:15:57 -0500 Received: from localhost (unknown [84.88.53.92]) by gw.ac.upc.edu (Postfix) with ESMTP id B78AC6B01CA for ; Fri, 9 Dec 2011 21:15:55 +0100 (CET) From: =?utf-8?b?TGx1w61z?= Vilanova Date: Fri, 09 Dec 2011 21:15:48 +0100 Message-ID: <20111209201548.11487.97143.stgit@ginnungagap.bsc.es> In-Reply-To: <20111209201430.11487.82078.stgit@ginnungagap.bsc.es> References: <20111209201430.11487.82078.stgit@ginnungagap.bsc.es> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 5/7] [all] Trivial 'tcg_gen_debug_insn_start' unification in 'gen_intermediate_code_internal' List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Make sure 'tcg_gen_debug_insn_start' is always called in 'gen_intermediate_code_internal' and after calls to 'gen_io_start' (befor= e the instruction decoding). Signed-off-by: Llu=C3=ADs Vilanova --- target-alpha/translate.c | 11 ++++++----- target-cris/translate.c | 12 +++++++----- target-i386/translate.c | 5 +++-- target-lm32/translate.c | 7 +++---- target-m68k/translate.c | 6 +++++- target-microblaze/translate.c | 6 +++--- target-mips/translate.c | 6 +++--- target-ppc/translate.c | 6 ++++-- target-s390x/translate.c | 4 ++++ target-sh4/translate.c | 8 ++++---- target-sparc/translate.c | 6 ++++-- target-unicore32/translate.c | 3 +++ target-xtensa/translate.c | 7 +++---- 13 files changed, 52 insertions(+), 35 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 18f5428..5efc605 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -3389,15 +3389,16 @@ static inline void gen_intermediate_code_internal= (CPUState *env, gen_opc_instr_start[lj] =3D 1; gen_opc_icount[lj] =3D num_insns; } - if (num_insns + 1 =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) + if (num_insns + 1 =3D=3D max_insns && (tb->cflags & CF_LAST_IO))= { gen_io_start(); - insn =3D ldl_code(ctx.pc); - num_insns++; - - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + } + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { tcg_gen_debug_insn_start(ctx.pc); } =20 + insn =3D ldl_code(ctx.pc); + num_insns++; + ctx.pc +=3D 4; ret =3D translate_one(ctxp, insn); =20 diff --git a/target-cris/translate.c b/target-cris/translate.c index cac22c9..f6bebea 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3080,9 +3080,6 @@ static unsigned int crisv32_decoder(DisasContext *d= c) int insn_len =3D 2; int i; =20 - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) - tcg_gen_debug_insn_start(dc->pc); - /* Load a halfword onto the instruction register. */ dc->ir =3D cris_fetch(dc, dc->pc, 2, 0); =20 @@ -3291,9 +3288,14 @@ gen_intermediate_code_internal(CPUState *env, Tran= slationBlock *tb, =20 if (num_insns + 1 =3D=3D max_insns && (tb->cflags & CF_L= AST_IO)) gen_io_start(); - dc->clear_x =3D 1; + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(dc->pc); + } + + dc->clear_x =3D 1; + + insn_len =3D dc->decoder(dc); =20 - insn_len =3D dc->decoder(dc); dc->ppc =3D dc->pc; dc->pc +=3D insn_len; if (dc->clear_x) diff --git a/target-i386/translate.c b/target-i386/translate.c index 7192ce9..9818ebb 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -4081,8 +4081,6 @@ static target_ulong disas_insn(DisasContext *s, tar= get_ulong pc_start) target_ulong next_eip, tval; int rex_w, rex_r; =20 - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) - tcg_gen_debug_insn_start(pc_start); s->pc =3D pc_start; prefixes =3D 0; aflag =3D s->code32; @@ -7822,6 +7820,9 @@ static inline void gen_intermediate_code_internal(C= PUState *env, } if (num_insns + 1 =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(pc_ptr); + } =20 pc_ptr =3D disas_insn(dc, pc_ptr); num_insns++; diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 2535fb7..c0d9195 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -952,10 +952,6 @@ static inline void decode(DisasContext *dc) { uint32_t ir; =20 - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { - tcg_gen_debug_insn_start(dc->pc); - } - dc->ir =3D ir =3D ldl_code(dc->pc); LOG_DIS("%8.8x\t", dc->ir); =20 @@ -1076,6 +1072,9 @@ static void gen_intermediate_code_internal(CPUState= *env, if (num_insns + 1 =3D=3D max_insns && (tb->cflags & CF_LAST_IO))= { gen_io_start(); } + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(dc->pc); + } =20 decode(dc); dc->pc +=3D 4; diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 9cb8139..5e735f3 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3018,8 +3018,12 @@ gen_intermediate_code_internal(CPUState *env, Tran= slationBlock *tb, } if (num_insns + 1 =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(dc->pc); + } + dc->insn_pc =3D dc->pc; - disas_m68k_insn(env, dc); + disas_m68k_insn(env, dc); num_insns++; } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end && !env->singlestep_enabled && diff --git a/target-microblaze/translate.c b/target-microblaze/translate.= c index 6b6a593..a1a9ce6 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1550,9 +1550,6 @@ static inline void decode(DisasContext *dc) uint32_t ir; int i; =20 - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) - tcg_gen_debug_insn_start(dc->pc); - dc->ir =3D ir =3D ldl_code(dc->pc); LOG_DIS("%8.8x\t", dc->ir); =20 @@ -1686,6 +1683,9 @@ gen_intermediate_code_internal(CPUState *env, Trans= lationBlock *tb, =20 if (num_insns + 1 =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(dc->pc); + } =20 dc->clear_imm =3D 1; decode(dc); diff --git a/target-mips/translate.c b/target-mips/translate.c index 0076058..6f67b36 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -11715,9 +11715,6 @@ static void decode_opc (CPUState *env, DisasConte= xt *ctx, int *is_branch) gen_set_label(l1); } =20 - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) - tcg_gen_debug_insn_start(ctx->pc); - op =3D MASK_OP_MAJOR(ctx->opcode); rs =3D (ctx->opcode >> 21) & 0x1f; rt =3D (ctx->opcode >> 16) & 0x1f; @@ -12444,6 +12441,9 @@ gen_intermediate_code_internal (CPUState *env, Tr= anslationBlock *tb, } if (num_insns + 1 =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(ctx.pc); + } =20 is_branch =3D 0; if (!(ctx.hflags & MIPS_HFLAG_M16)) { diff --git a/target-ppc/translate.c b/target-ppc/translate.c index af78360..c515ea4 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9490,6 +9490,10 @@ static inline void gen_intermediate_code_internal(= CPUState *env, ctx.nip, ctx.mem_idx, (int)msr_ir); if (num_insns + 1 =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(ctx.nip); + } + if (unlikely(ctx.le_mode)) { ctx.opcode =3D bswap32(ldl_code(ctx.nip)); } else { @@ -9498,8 +9502,6 @@ static inline void gen_intermediate_code_internal(C= PUState *env, LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n", ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode), opc3(ctx.opcode), little_endian ? "little" : "big"); - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) - tcg_gen_debug_insn_start(ctx.nip); ctx.nip +=3D 4; table =3D env->opcodes; num_insns++; diff --git a/target-s390x/translate.c b/target-s390x/translate.c index c2a04a5..f0b877e 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -5174,6 +5174,10 @@ static inline void gen_intermediate_code_internal(= CPUState *env, if (num_insns + 1 =3D=3D max_insns && (tb->cflags & CF_LAST_IO))= { gen_io_start(); } + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(dc.pc); + } + #if defined(S390X_DEBUG_DISAS_VERBOSE) LOG_DISAS("pc " TARGET_FMT_lx "\n", dc.pc); diff --git a/target-sh4/translate.c b/target-sh4/translate.c index d75c065..6c1872c 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1904,10 +1904,6 @@ static void decode_opc(DisasContext * ctx) { uint32_t old_flags =3D ctx->flags; =20 - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { - tcg_gen_debug_insn_start(ctx->pc); - } - _decode_opc(ctx); =20 if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { @@ -1995,6 +1991,10 @@ gen_intermediate_code_internal(CPUState * env, Tra= nslationBlock * tb, } if (num_insns + 1 =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(ctx.pc); + } + #if 0 fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc); fflush(stderr); diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 415d996..5c7cca0 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -2381,8 +2381,6 @@ static void disas_sparc_insn(DisasContext * dc) TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; target_long simm; =20 - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) - tcg_gen_debug_insn_start(dc->pc); insn =3D ldl_code(dc->pc); opc =3D GET_FIELD(insn, 0, 1); =20 @@ -5297,6 +5295,10 @@ static inline void gen_intermediate_code_internal(= TranslationBlock * tb, } if (num_insns + 1 =3D=3D max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(dc->pc); + } + last_pc =3D dc->pc; disas_sparc_insn(dc); num_insns++; diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 8edca98..74172ea 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -1920,6 +1920,9 @@ static inline void gen_intermediate_code_internal(C= PUState *env, if (num_insns + 1 =3D=3D max_insns && (tb->cflags & CF_LAST_IO))= { gen_io_start(); } + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(dc->pc); + } =20 disas_uc32_insn(env, dc); =20 diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 3f741ac..96db089 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -2458,15 +2458,14 @@ static void gen_intermediate_code_internal( gen_opc_icount[lj] =3D insn_count; } =20 - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { - tcg_gen_debug_insn_start(dc.pc); - } - ++dc.ccount_delta; =20 if (insn_count + 1 =3D=3D max_insns && (tb->cflags & CF_LAST_IO)= ) { gen_io_start(); } + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) { + tcg_gen_debug_insn_start(dc.pc); + } =20 disas_xtensa_insn(&dc); ++insn_count;