From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:49339) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RZ6re-0000xQ-UX for qemu-devel@nongnu.org; Fri, 09 Dec 2011 15:16:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RZ6rc-0003LV-Rm for qemu-devel@nongnu.org; Fri, 09 Dec 2011 15:16:14 -0500 Received: from gw.ac.upc.edu ([147.83.30.3]:40206) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RZ6rc-0003LL-Cp for qemu-devel@nongnu.org; Fri, 09 Dec 2011 15:16:12 -0500 Received: from localhost (unknown [84.88.53.92]) by gw.ac.upc.edu (Postfix) with ESMTP id 20D596B01CA for ; Fri, 9 Dec 2011 21:16:11 +0100 (CET) From: =?utf-8?b?TGx1w61z?= Vilanova Date: Fri, 09 Dec 2011 21:16:04 +0100 Message-ID: <20111209201604.11487.12137.stgit@ginnungagap.bsc.es> In-Reply-To: <20111209201430.11487.82078.stgit@ginnungagap.bsc.es> References: <20111209201430.11487.82078.stgit@ginnungagap.bsc.es> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH 6/7] trace: [all] Add "vfetch" TCG tracing event List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Signed-off-by: Llu=C3=ADs Vilanova --- target-alpha/translate.c | 2 ++ target-arm/translate.c | 2 ++ target-cris/translate.c | 2 ++ target-i386/translate.c | 2 ++ target-lm32/translate.c | 2 ++ target-m68k/translate.c | 2 ++ target-microblaze/translate.c | 2 ++ target-mips/translate.c | 2 ++ target-ppc/translate.c | 2 ++ target-s390x/translate.c | 3 +++ target-sh4/translate.c | 2 ++ target-sparc/translate.c | 2 ++ target-unicore32/translate.c | 2 ++ target-xtensa/translate.c | 2 ++ trace-events | 7 +++++++ 15 files changed, 36 insertions(+), 0 deletions(-) diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 5efc605..375cfa4 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -3396,6 +3396,8 @@ static inline void gen_intermediate_code_internal(C= PUState *env, tcg_gen_debug_insn_start(ctx.pc); } =20 + gen_helper_trace_vfetch(ctx.pc); + insn =3D ldl_code(ctx.pc); num_insns++; =20 diff --git a/target-arm/translate.c b/target-arm/translate.c index b0b36f3..d0b386a 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -9972,6 +9972,8 @@ static inline void gen_intermediate_code_internal(C= PUState *env, tcg_gen_debug_insn_start(dc->pc); } =20 + gen_helper_trace_vfetch(dc->pc); + if (dc->thumb) { disas_thumb_insn(env, dc); if (dc->condexec_mask) { diff --git a/target-cris/translate.c b/target-cris/translate.c index f6bebea..4abd1d7 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3294,6 +3294,8 @@ gen_intermediate_code_internal(CPUState *env, Trans= lationBlock *tb, =20 dc->clear_x =3D 1; =20 + gen_helper_trace_vfetch(dc->pc); + insn_len =3D dc->decoder(dc); =20 dc->ppc =3D dc->pc; diff --git a/target-i386/translate.c b/target-i386/translate.c index 9818ebb..9ae8c34 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7824,6 +7824,8 @@ static inline void gen_intermediate_code_internal(C= PUState *env, tcg_gen_debug_insn_start(pc_ptr); } =20 + gen_helper_trace_vfetch(pc_ptr); + pc_ptr =3D disas_insn(dc, pc_ptr); num_insns++; /* stop translation if indicated */ diff --git a/target-lm32/translate.c b/target-lm32/translate.c index c0d9195..f57bd70 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -1076,6 +1076,8 @@ static void gen_intermediate_code_internal(CPUState= *env, tcg_gen_debug_insn_start(dc->pc); } =20 + gen_helper_trace_vfetch(dc->pc); + decode(dc); dc->pc +=3D 4; num_insns++; diff --git a/target-m68k/translate.c b/target-m68k/translate.c index 5e735f3..ce92a7f 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3022,6 +3022,8 @@ gen_intermediate_code_internal(CPUState *env, Trans= lationBlock *tb, tcg_gen_debug_insn_start(dc->pc); } =20 + gen_helper_trace_vfetch(dc->pc); + dc->insn_pc =3D dc->pc; disas_m68k_insn(env, dc); num_insns++; diff --git a/target-microblaze/translate.c b/target-microblaze/translate.= c index a1a9ce6..53b6e73 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1687,6 +1687,8 @@ gen_intermediate_code_internal(CPUState *env, Trans= lationBlock *tb, tcg_gen_debug_insn_start(dc->pc); } =20 + gen_helper_trace_vfetch(dc->pc); + dc->clear_imm =3D 1; decode(dc); if (dc->clear_imm) diff --git a/target-mips/translate.c b/target-mips/translate.c index 6f67b36..3318e88 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12445,6 +12445,8 @@ gen_intermediate_code_internal (CPUState *env, Tr= anslationBlock *tb, tcg_gen_debug_insn_start(ctx.pc); } =20 + gen_helper_trace_vfetch(ctx.pc); + is_branch =3D 0; if (!(ctx.hflags & MIPS_HFLAG_M16)) { ctx.opcode =3D ldl_code(ctx.pc); diff --git a/target-ppc/translate.c b/target-ppc/translate.c index c515ea4..8d898d0 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9494,6 +9494,8 @@ static inline void gen_intermediate_code_internal(C= PUState *env, tcg_gen_debug_insn_start(ctx.nip); } =20 + gen_helper_trace_vfetch(ctx.nip); + if (unlikely(ctx.le_mode)) { ctx.opcode =3D bswap32(ldl_code(ctx.nip)); } else { diff --git a/target-s390x/translate.c b/target-s390x/translate.c index f0b877e..a8ac111 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -5182,6 +5182,9 @@ static inline void gen_intermediate_code_internal(C= PUState *env, LOG_DISAS("pc " TARGET_FMT_lx "\n", dc.pc); #endif + + gen_helper_trace_vfetch(dc.pc); + disas_s390_insn(&dc); =20 num_insns++; diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 6c1872c..00cbe28 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -1999,6 +1999,8 @@ gen_intermediate_code_internal(CPUState * env, Tran= slationBlock * tb, fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc); fflush(stderr); #endif + gen_helper_trace_vfetch(ctx.pc); + ctx.opcode =3D lduw_code(ctx.pc); decode_opc(&ctx); num_insns++; diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 5c7cca0..cdd7dbd 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -5299,6 +5299,8 @@ static inline void gen_intermediate_code_internal(T= ranslationBlock * tb, tcg_gen_debug_insn_start(dc->pc); } =20 + gen_helper_trace_vfetch(dc->pc); + last_pc =3D dc->pc; disas_sparc_insn(dc); num_insns++; diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 74172ea..33a201b 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -1924,6 +1924,8 @@ static inline void gen_intermediate_code_internal(C= PUState *env, tcg_gen_debug_insn_start(dc->pc); } =20 + gen_helper_trace_vfetch(dc->pc); + disas_uc32_insn(env, dc); =20 if (num_temps) { diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index 96db089..c020ffa 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -2467,6 +2467,8 @@ static void gen_intermediate_code_internal( tcg_gen_debug_insn_start(dc.pc); } =20 + gen_helper_trace_vfetch(dc.pc); + disas_xtensa_insn(&dc); ++insn_count; if (env->singlestep_enabled) { diff --git a/trace-events b/trace-events index 6dac6ae..9b315c5 100644 --- a/trace-events +++ b/trace-events @@ -653,3 +653,10 @@ vcpu_reset(void *vcpu) "%p" # # vaddr : starting virtual address disable tcg vbbl(uint64_t vaddr) "vaddr=3D0x%016"PRIx64 + +# Start instruction execution +# +# Targets: all +# +# vaddr : instruction's virtual address +disable tcg vfetch(uint64_t vaddr) "vaddr=3D0x%016"PRIx64