From: Kevin O'Connor <kevin@koconnor.net>
To: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Alexey Korolev <alexey.korolev@endace.com>,
sfd@endace.com, seabios@seabios.org, qemu-devel@nongnu.org,
yamahata@valinux.co.jp
Subject: Re: [Qemu-devel] [PATCH 3/3] Changes related to secondary buses and 64bit regions
Date: Fri, 30 Dec 2011 00:03:05 -0500 [thread overview]
Message-ID: <20111230050305.GA16616@morn.localdomain> (raw)
In-Reply-To: <20111228114302.GB26310@redhat.com>
On Wed, Dec 28, 2011 at 01:43:02PM +0200, Michael S. Tsirkin wrote:
> On Wed, Dec 28, 2011 at 06:35:55PM +1300, Alexey Korolev wrote:
> > All devices behind a bridge need to have all their regions consecutive and
> > not overlapping with all the normal memory ranges.
> > Since prefetchable memory is described by one record, we must avoid the situations
> > when 32bit and 64bit prefetchable regions are present within one secondary bus.
>
> How do we avoid this? Assume we have two devices:
> a 32 bit and a 64 bit one, behind a bridge.
> There are two main things we can do:
> 1. Make the 64 bit device only use the low 32 bit
> 2. Put the 32 bit one in the non-prefetcheable range
I would vote for option 1. Supporting option 2 seems complex and it
would only help the case where there is a large 64bit prefmem bar
(that can't reliably fit in low memory) behind a bridge that supports
64bit prefmem bars that also has a small 32bit prefmem bar (which can
reliably fit in low memory) behind it. This condition seems too
unlikely to be worth supporting the additional complexity.
-Kevin
next prev parent reply other threads:[~2011-12-30 5:03 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-12-28 4:41 [Qemu-devel] [Seabios] [PATCH 0/3] 64bit PCI BARs allocations Alexey Korolev
2011-12-28 5:00 ` [Qemu-devel] [PATCH 1/3] Add new range above 4GB in _CRS table Alexey Korolev
2011-12-28 5:26 ` [Qemu-devel] [PATCH 2/3] Add a new PCI region type to supports 64 bit ranges Alexey Korolev
2011-12-28 11:30 ` Michael S. Tsirkin
2011-12-29 3:57 ` Alexey Korolev
2011-12-29 2:56 ` Kevin O'Connor
2011-12-29 5:00 ` Alexey Korolev
2011-12-30 5:57 ` Kevin O'Connor
2011-12-29 5:32 ` Alexey Korolev
2011-12-29 16:16 ` Michael S. Tsirkin
2012-01-03 15:14 ` Gerd Hoffmann
2012-01-04 3:10 ` Kevin O'Connor
2011-12-28 5:35 ` [Qemu-devel] [PATCH 3/3] Changes related to secondary buses and 64bit regions Alexey Korolev
2011-12-28 6:30 ` [Qemu-devel] [SeaBIOS] " Alexey Korolev
2011-12-28 11:43 ` [Qemu-devel] " Michael S. Tsirkin
2011-12-29 5:40 ` Alexey Korolev
2011-12-29 16:18 ` Michael S. Tsirkin
2011-12-30 4:56 ` Alexey Korolev
2011-12-29 5:41 ` Alexey Korolev
2011-12-29 16:19 ` Michael S. Tsirkin
2011-12-29 16:21 ` Michael S. Tsirkin
2011-12-30 5:10 ` Alexey Korolev
2011-12-30 6:02 ` Kevin O'Connor
2011-12-30 5:10 ` Alexey Korolev
2011-12-30 6:22 ` Kevin O'Connor
2011-12-30 7:05 ` Alexey Korolev
2011-12-30 5:03 ` Kevin O'Connor [this message]
2011-12-28 11:43 ` [Qemu-devel] [Seabios] [PATCH 0/3] 64bit PCI BARs allocations Michael S. Tsirkin
2011-12-29 9:20 ` Alexey Korolev
2011-12-29 16:21 ` Michael S. Tsirkin
2011-12-29 22:17 ` Alexey Korolev
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