From: Kevin O'Connor <kevin@koconnor.net>
To: Alexey Korolev <alexey.korolev@endace.com>
Cc: sfd@endace.com, yamahata@valinux.co.jp, seabios@seabios.org,
qemu-devel@nongnu.org, "Michael S. Tsirkin" <mst@redhat.com>
Subject: Re: [Qemu-devel] [PATCH 3/3] Changes related to secondary buses and 64bit regions
Date: Fri, 30 Dec 2011 01:02:16 -0500 [thread overview]
Message-ID: <20111230060216.GC16616@morn.localdomain> (raw)
In-Reply-To: <4EFD47B5.800@endace.com>
On Fri, Dec 30, 2011 at 06:10:13PM +1300, Alexey Korolev wrote:
> On 30/12/11 05:21, Michael S. Tsirkin wrote:
> >On Thu, Dec 29, 2011 at 06:41:36PM +1300, Alexey Korolev wrote:
> >>>Can't figure this out. What does this do?
> >>Bios will panic if it founds prefmem BARs in both 32bit and 64bit areas.
> >That's not good, it's a legal configuration.
> >
> To be more complete : Bios will panic if it founds prefmem BARs in
> both 32bit and 64bit areas
> on the same secondary Bus.
> I agree about that this limitation is too strict at the moment. But
> this is just a limitation, there are
> plenty of them in Seabios.
There are very few panic calls in seabios. Halting in the system
firmware is very unfriendly and should be avoided.
As described in my other email, if there is a mix of prefmem bars on a
secondary bus, then just allocate all those bars in the first 4gig.
No reason to halt the boot.
> To answer if it is a legal or not we need to have a look how real
> BIOS would behave in a such
> scenario. Unfortunately I have no chance to have this configuration
> on hand. If you have (may
> have) this I would appreciate if you let us know how the Bios will behave?
You can look at the pci allocation code in coreboot.
-Kevin
next prev parent reply other threads:[~2011-12-30 6:02 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-12-28 4:41 [Qemu-devel] [Seabios] [PATCH 0/3] 64bit PCI BARs allocations Alexey Korolev
2011-12-28 5:00 ` [Qemu-devel] [PATCH 1/3] Add new range above 4GB in _CRS table Alexey Korolev
2011-12-28 5:26 ` [Qemu-devel] [PATCH 2/3] Add a new PCI region type to supports 64 bit ranges Alexey Korolev
2011-12-28 11:30 ` Michael S. Tsirkin
2011-12-29 3:57 ` Alexey Korolev
2011-12-29 2:56 ` Kevin O'Connor
2011-12-29 5:00 ` Alexey Korolev
2011-12-30 5:57 ` Kevin O'Connor
2011-12-29 5:32 ` Alexey Korolev
2011-12-29 16:16 ` Michael S. Tsirkin
2012-01-03 15:14 ` Gerd Hoffmann
2012-01-04 3:10 ` Kevin O'Connor
2011-12-28 5:35 ` [Qemu-devel] [PATCH 3/3] Changes related to secondary buses and 64bit regions Alexey Korolev
2011-12-28 6:30 ` [Qemu-devel] [SeaBIOS] " Alexey Korolev
2011-12-28 11:43 ` [Qemu-devel] " Michael S. Tsirkin
2011-12-29 5:40 ` Alexey Korolev
2011-12-29 16:18 ` Michael S. Tsirkin
2011-12-30 4:56 ` Alexey Korolev
2011-12-29 5:41 ` Alexey Korolev
2011-12-29 16:19 ` Michael S. Tsirkin
2011-12-29 16:21 ` Michael S. Tsirkin
2011-12-30 5:10 ` Alexey Korolev
2011-12-30 6:02 ` Kevin O'Connor [this message]
2011-12-30 5:10 ` Alexey Korolev
2011-12-30 6:22 ` Kevin O'Connor
2011-12-30 7:05 ` Alexey Korolev
2011-12-30 5:03 ` Kevin O'Connor
2011-12-28 11:43 ` [Qemu-devel] [Seabios] [PATCH 0/3] 64bit PCI BARs allocations Michael S. Tsirkin
2011-12-29 9:20 ` Alexey Korolev
2011-12-29 16:21 ` Michael S. Tsirkin
2011-12-29 22:17 ` Alexey Korolev
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