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[2001:44b8:2176:c800:94f0:22fe:dda1:1842]) by smtp.gmail.com with ESMTPSA id d5-20020a056a00244500b006da19433468sm11799778pfj.61.2024.01.23.08.17.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 Jan 2024 08:17:54 -0800 (PST) Message-ID: <20117cb1-b167-425d-ae7c-a5e149264f70@linaro.org> Date: Wed, 24 Jan 2024 02:17:49 +1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] target/arm: Fix A64 scalar SQSHRN and SQRSHRN Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org References: <20240123153416.877308-1-peter.maydell@linaro.org> From: Richard Henderson In-Reply-To: <20240123153416.877308-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 1/24/24 01:34, Peter Maydell wrote: > In commit 1b7bc9b5c8bf374dd we changed handle_vec_simd_sqshrn() so > that instead of starting with a 0 value and depositing in each new > element from the narrowing operation, it instead started with the raw > result of the narrowing operation of the first element. > > This is fine in the vector case, because the deposit operations for > the second and subsequent elements will always overwrite any higher > bits that might have been in the first element's result value in > tcg_rd. However in the scalar case we only go through this loop > once. The effect is that for a signed narrowing operation, if the > result is negative then we will now return a value where the bits > above the first element are incorrectly 1 (because the narrowfn > returns a sign-extended result, not one that is truncated to the > element size). > > Fix this by using an extract operation to get exactly the correct > bits of the output of the narrowfn for element 1, instead of a > plain move. > > Cc:qemu-stable@nongnu.org > Fixes: 1b7bc9b5c8bf374dd3 ("target/arm: Avoid tcg_const_ptr in handle_vec_simd_sqshrn") > Resolves:https://gitlab.com/qemu-project/qemu/-/issues/2089 > Signed-off-by: Peter Maydell > --- > target/arm/tcg/translate-a64.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Richard Henderson r~