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* [Qemu-devel] [PATCH] target-sh4: Fix operands for fipr, ftrv instructions
@ 2012-01-05 12:11 Stefan Weil
  2012-01-07 19:51 ` Aurelien Jarno
  0 siblings, 1 reply; 2+ messages in thread
From: Stefan Weil @ 2012-01-05 12:11 UTC (permalink / raw)
  To: qemu-devel; +Cc: Stefan Weil, Aurelien Jarno

Coverity complained about right shifts of opcode (16, 18) which were
larger than the size of opcode (16 bit).

Using the correct shift values fixes this.

Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Stefan Weil <sw@weilnetz.de>
---
 target-sh4/translate.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index bad3577..2ecb236 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1864,8 +1864,8 @@ static void _decode_opc(DisasContext * ctx)
         CHECK_FPU_ENABLED
         if ((ctx->fpscr & FPSCR_PR) == 0) {
             TCGv m, n;
-            m = tcg_const_i32((ctx->opcode >> 16) & 3);
-            n = tcg_const_i32((ctx->opcode >> 18) & 3);
+            m = tcg_const_i32((ctx->opcode >> 8) & 3);
+            n = tcg_const_i32((ctx->opcode >> 10) & 3);
             gen_helper_fipr(m, n);
             tcg_temp_free(m);
             tcg_temp_free(n);
@@ -1877,7 +1877,7 @@ static void _decode_opc(DisasContext * ctx)
         if ((ctx->opcode & 0x0300) == 0x0100 &&
             (ctx->fpscr & FPSCR_PR) == 0) {
             TCGv n;
-            n = tcg_const_i32((ctx->opcode >> 18) & 3);
+            n = tcg_const_i32((ctx->opcode >> 10) & 3);
             gen_helper_ftrv(n);
             tcg_temp_free(n);
             return;
-- 
1.7.2.5

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2012-01-05 12:11 [Qemu-devel] [PATCH] target-sh4: Fix operands for fipr, ftrv instructions Stefan Weil
2012-01-07 19:51 ` Aurelien Jarno

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