From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:41169) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RlpOe-000775-Kt for qemu-devel@nongnu.org; Fri, 13 Jan 2012 17:14:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RlpOd-0000TF-31 for qemu-devel@nongnu.org; Fri, 13 Jan 2012 17:14:52 -0500 Received: from hall.aurel32.net ([88.191.126.93]:46227) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RlpOc-0000TB-SV for qemu-devel@nongnu.org; Fri, 13 Jan 2012 17:14:51 -0500 Date: Fri, 13 Jan 2012 23:14:49 +0100 From: Aurelien Jarno Message-ID: <20120113221449.GC711@hall.aurel32.net> References: <1326477039-12087-1-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1326477039-12087-1-git-send-email-peter.maydell@linaro.org> Sender: Aurelien Jarno Subject: Re: [Qemu-devel] [PULL 0/2] target-arm queue List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: Blue Swirl , qemu-devel@nongnu.org On Fri, Jan 13, 2012 at 05:50:37PM +0000, Peter Maydell wrote: > A small target-arm pullreq, but I want to get the SCR change > committed because the Calxeda patchset depends on it, and then > the Samsung patchset is going to need to be updated to sit on > top of that, as are some Cortex-A15 related changes I've been > working on. > > The M profile patch only went on the list on Monday, so this > is slightly early, but it's a pretty trivial change and I > thought I'd rather get the pullreq sent out before the weekend > rather than after. > > thanks > -- PMM > > The following changes since commit 6b620ca3b052e622eef4379cfe37c5c3db5364c9: > > prepare for future GPLv2+ relicensing (2012-01-13 10:55:56 -0600) > > are available in the git repository at: > git://git.linaro.org/people/pmaydell/qemu-arm.git target-arm.for-upstream > > Peter Maydell (1): > target-arm: Fix errors in decode of M profile CPS > > Rob Herring (1): > arm: Add dummy support for co-processor 15's secure config register > > target-arm/cpu.h | 3 ++- > target-arm/helper.c | 9 +++++++++ > target-arm/machine.c | 2 ++ > target-arm/translate.c | 8 ++++---- > 4 files changed, 17 insertions(+), 5 deletions(-) > Thanks, pulled. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net