From: 陳韋任 <chenwj@iis.sinica.edu.tw>
To: Xin Tong <xerox.time.tech@gmail.com>
Cc: qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] nested page table translation for non-x86 operating system
Date: Fri, 20 Jan 2012 16:23:31 +0800 [thread overview]
Message-ID: <20120120082330.GA83580@cs.nctu.edu.tw> (raw)
In-Reply-To: <CALKntY0ZEbVF1_dLFAAaAaeP08tOwOD3DsR+DkxgE27D9-rk5A@mail.gmail.com>
> 1. The control of gCR3 and hCR3 needs kernel access. While they can
> be set with a device module as what is done in kvm. Trapping into the
> kernel every time gCR3 is reseted might be too expensive.
Why the control of gCR3 needs kernel access? Isn't gCR3 just a field of the
CPUX86State? QEMU should have the control of it. Or you mean the trapping thing?
> 2. After setting the gCR3 and hCR3. whatever memory references fall
> within the guest memory will be done correctly. However, memory
> references done by the host will be broken. Therefore, when we load
> the from the CPUstates, call to helpers for exits from the code cache,
> we need to change the paging mechanism back to non-nested. can this be
> done ? how expensive will this be ?
Why the memeory references done by the host will be broken?
Regards,
chenwj
--
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj
next prev parent reply other threads:[~2012-01-20 8:23 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-01-20 5:12 [Qemu-devel] nested page table translation for non-x86 operating system Xin Tong
2012-01-20 8:23 ` 陳韋任 [this message]
2012-01-20 13:54 ` Xin Tong
2012-01-31 7:28 ` 陳韋任
2012-06-22 7:28 ` 陳韋任 (Wei-Ren Chen)
2012-06-22 9:48 ` Xin Tong
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