From: Paul Brook <paul@codesourcery.com>
To: qemu-devel@nongnu.org
Cc: Blue Swirl <blauwirbel@gmail.com>,
Peter Maydell <peter.maydell@linaro.org>,
Aurelien Jarno <aurelien@aurel32.net>
Subject: Re: [Qemu-devel] [PATCH 5/5] Add Cortex-A15 CPU definition
Date: Fri, 10 Feb 2012 02:09:36 +0000 [thread overview]
Message-ID: <201202100209.37154.paul@codesourcery.com> (raw)
In-Reply-To: <CAFEAcA_1rp50BAR==CfRSgTuLdre8NedF-XmFLS48-eG2DZUpA@mail.gmail.com>
> >> Add a definition of a Cortex-A15 CPU. Note that for the moment we do
> >> not implement any of:
> >> * Large Physical Address Extensions (LPAE)
> >> * Virtualization Extensions
> >> * Generic Timer
> >
> > Are there feature bits that the guest can check before blindly using
> > them? I assume for at least LPAE and the timer there's a way for the OS
> > to test for these features without just poking at them and seing if they
> > explode.
> >
> > If so it's worth adding coments describing where these diverge from a
> > real A15.
>
> There are feature bits, yes, but I've followed the general current
> qemu practice of following the feature bits of the real hardware
> rather than clearing feature bits for things we don't support
> (eg for A9 we are currently claiming TrustZone and ThumbEE when
> neither are actually true for QEMU).
These are bugs.
Paul
next prev parent reply other threads:[~2012-02-10 2:09 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-01-25 15:27 [Qemu-devel] [PULL 0/5] target-arm queue Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 1/5] target-arm: Fix implementation of TLB invalidate operations Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 2/5] target-arm/helper.c: Don't assume softfloat int32 is 32 bits only Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 3/5] arm: store the config_base_register during cpu_reset Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 4/5] Add dummy implementation of generic timer cp15 registers Peter Maydell
2012-01-25 15:27 ` [Qemu-devel] [PATCH 5/5] Add Cortex-A15 CPU definition Peter Maydell
2012-02-10 1:23 ` Paul Brook
2012-02-10 1:35 ` Peter Maydell
2012-02-10 2:09 ` Paul Brook [this message]
2012-01-28 13:12 ` [Qemu-devel] [PULL 0/5] target-arm queue Blue Swirl
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