From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:33711) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rvfvk-0002z0-9K for qemu-devel@nongnu.org; Thu, 09 Feb 2012 21:09:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Rvfvg-0000nR-EZ for qemu-devel@nongnu.org; Thu, 09 Feb 2012 21:09:44 -0500 Received: from relay1.mentorg.com ([192.94.38.131]:49438) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Rvfvf-0000nJ-Sg for qemu-devel@nongnu.org; Thu, 09 Feb 2012 21:09:40 -0500 From: Paul Brook Date: Fri, 10 Feb 2012 02:09:36 +0000 References: <1327505265-5976-1-git-send-email-peter.maydell@linaro.org> <201202100123.22632.paul@codesourcery.com> In-Reply-To: MIME-Version: 1.0 Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <201202100209.37154.paul@codesourcery.com> Subject: Re: [Qemu-devel] [PATCH 5/5] Add Cortex-A15 CPU definition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , Peter Maydell , Aurelien Jarno > >> Add a definition of a Cortex-A15 CPU. Note that for the moment we do > >> not implement any of: > >> * Large Physical Address Extensions (LPAE) > >> * Virtualization Extensions > >> * Generic Timer > > > > Are there feature bits that the guest can check before blindly using > > them? I assume for at least LPAE and the timer there's a way for the OS > > to test for these features without just poking at them and seing if they > > explode. > > > > If so it's worth adding coments describing where these diverge from a > > real A15. > > There are feature bits, yes, but I've followed the general current > qemu practice of following the feature bits of the real hardware > rather than clearing feature bits for things we don't support > (eg for A9 we are currently claiming TrustZone and ThumbEE when > neither are actually true for QEMU). These are bugs. Paul