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* [Qemu-devel] questions about pci
@ 2012-03-04 12:33 WanPeng Li
  2012-03-06 10:10 ` 陳韋任
  0 siblings, 1 reply; 3+ messages in thread
From: WanPeng Li @ 2012-03-04 12:33 UTC (permalink / raw)
  To: qemu-devel

Hi all:

I read pci code in qemu about i440fx, pci.c and so on. I think if guest
os whose mainboard is based on x86, it will use IO instructions to
access PCI configuration space.If not use passthrough, qemu should
emulate these operations.I find a function called kvm_handle_io who will
emulate ioport write/read, I have traced this function, but I haven't found it has
any relationship with pci read/write configuration space functions like
i440fx_write_config and piix3_write_config.So how does it emulate pci
configuration space access when not use passthrough?


thanks 
Wanpeng Li

LTC China, IBM

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [Qemu-devel] questions about pci
  2012-03-04 12:33 [Qemu-devel] questions about pci WanPeng Li
@ 2012-03-06 10:10 ` 陳韋任
       [not found]   ` <20120307114708.GA2404@liwp@linux.vnet.ibm.com>
  0 siblings, 1 reply; 3+ messages in thread
From: 陳韋任 @ 2012-03-06 10:10 UTC (permalink / raw)
  To: WanPeng Li; +Cc: qemu-devel

> I read pci code in qemu about i440fx, pci.c and so on. I think if guest
> os whose mainboard is based on x86, it will use IO instructions to
> access PCI configuration space.If not use passthrough, qemu should
> emulate these operations.I find a function called kvm_handle_io who will
                                                    ^^^^^^^^^^^^^

  Looks suspicious. Prefix kvm mean passthrough, I guess.

> emulate ioport write/read, I have traced this function, but I haven't found it has
> any relationship with pci read/write configuration space functions like
> i440fx_write_config and piix3_write_config.So how does it emulate pci
> configuration space access when not use passthrough?

  `grep -r i440fx_write_config *` show you that you should take a look on
hw/piix_pci.c. Besides, setting breakpoint at i440fx_write_config also show you
how it get called.

HTH,
chenwj

-- 
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [Qemu-devel] questions about pci
       [not found]   ` <20120307114708.GA2404@liwp@linux.vnet.ibm.com>
@ 2012-03-08  2:50     ` 陳韋任
  0 siblings, 0 replies; 3+ messages in thread
From: 陳韋任 @ 2012-03-08  2:50 UTC (permalink / raw)
  To: WanPeng Li; +Cc: qemu-devel

  CC'ed to the list.

On Wed, Mar 07, 2012 at 07:47:08PM +0800, WanPeng Li wrote:
> On Tue, Mar 06, 2012 at 06:10:16PM +0800, 陳韋任 wrote:
> >> I read pci code in qemu about i440fx, pci.c and so on. I think if guest
> >> os whose mainboard is based on x86, it will use IO instructions to
> >> access PCI configuration space.If not use passthrough, qemu should
> >> emulate these operations.I find a function called kvm_handle_io who will
> >                                                    ^^^^^^^^^^^^^
> >
> >  Looks suspicious. Prefix kvm mean passthrough, I guess.
> 
> If want to use passthrough, you should add additional options, but I'am
> not. so not use passthrough here.

  Are you sure you are running into kvm_handle_io while booting a guest OS
by using QEMU? I set a breakpoint at kvm_handle_io but never stopping at it.
Or you're using KVM? 

> I think you know something about PCI, so I need your help to confirm
> some details.In phyical machine based on x86 platform, for example,
> during the process of kernel traverse pci devices, it needs to write pci
> configuration space, this influnce will reach the configuration space
> by two registers(0xcf8,0xcfc).In Qemu 0xcf8 and 0xcfc bind to some
> methods(read/write) of PHB.So every IO instructions(in/out) in guest os
> who intend to write pci configuration space should capture by kvm then
> pass to qemu to emulate(if not use passthrough).In guest os IO

  O.K., from here I am pretty sure you are talking about KVM which uses
QEMU to emulate devices. I am not familiar in this part, so ...

> instructions just read/write 0xcf8, 0xcfc, then pci will parse the
> address and forward to right device.In qemu it should first through PHB
> who binds methods and 0xcf8/0xcfc,then parse the address by the code
> itself.right? So every pci read/write configuration space should through
> PHB read/write methods first.

Regards,
chenwj

-- 
Wei-Ren Chen (陳韋任)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
Homepage: http://people.cs.nctu.edu.tw/~chenwj

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2012-03-08  2:51 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2012-03-04 12:33 [Qemu-devel] questions about pci WanPeng Li
2012-03-06 10:10 ` 陳韋任
     [not found]   ` <20120307114708.GA2404@liwp@linux.vnet.ibm.com>
2012-03-08  2:50     ` 陳韋任

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