From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:55816) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S4AdQ-0005uY-Sz for qemu-devel@nongnu.org; Sun, 04 Mar 2012 07:33:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S4AdP-0006Oa-89 for qemu-devel@nongnu.org; Sun, 04 Mar 2012 07:33:56 -0500 Received: from e28smtp05.in.ibm.com ([122.248.162.5]:57389) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S4AdO-0006G9-Ky for qemu-devel@nongnu.org; Sun, 04 Mar 2012 07:33:55 -0500 Received: from /spool/local by e28smtp05.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Sun, 4 Mar 2012 18:03:46 +0530 Received: from d28av05.in.ibm.com (d28av05.in.ibm.com [9.184.220.67]) by d28relay03.in.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q24CXfWp4120808 for ; Sun, 4 Mar 2012 18:03:43 +0530 Received: from d28av05.in.ibm.com (loopback [127.0.0.1]) by d28av05.in.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q24CXfdT026787 for ; Sun, 4 Mar 2012 23:33:41 +1100 Received: from localhost ([9.123.245.143]) by d28av05.in.ibm.com (8.14.4/8.13.1/NCO v10.0 AVin) with ESMTP id q24CXeBP026775 for ; Sun, 4 Mar 2012 23:33:41 +1100 Date: Sun, 4 Mar 2012 20:33:40 +0800 From: WanPeng Li Message-ID: <20120304123140.GA1760@liwp@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Subject: [Qemu-devel] questions about pci Reply-To: WanPeng Li List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel Hi all: I read pci code in qemu about i440fx, pci.c and so on. I think if guest os whose mainboard is based on x86, it will use IO instructions to access PCI configuration space.If not use passthrough, qemu should emulate these operations.I find a function called kvm_handle_io who will emulate ioport write/read, I have traced this function, but I haven't found it has any relationship with pci read/write configuration space functions like i440fx_write_config and piix3_write_config.So how does it emulate pci configuration space access when not use passthrough? thanks Wanpeng Li LTC China, IBM