From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:56095) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S4Iz6-0004ke-BI for qemu-devel@nongnu.org; Sun, 04 Mar 2012 16:28:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S4Iz2-0006tY-Cs for qemu-devel@nongnu.org; Sun, 04 Mar 2012 16:28:51 -0500 Received: from mx1.redhat.com ([209.132.183.28]:4352) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S4Iz2-0006rW-1N for qemu-devel@nongnu.org; Sun, 04 Mar 2012 16:28:48 -0500 Date: Sun, 4 Mar 2012 23:28:46 +0200 From: "Michael S. Tsirkin" Message-ID: <20120304212845.GI16058@redhat.com> References: <20120304132805.GC12047@redhat.com> <20120304142333.GA12900@redhat.com> <20120304152201.GC12776@redhat.com> <20120304173428.GA16058@redhat.com> <20120304200218.GH16058@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH] pci: fix bridge IO/BASE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: Mark Cave-Ayland , qemu-devel@nongnu.org, Anthony Liguori On Sun, Mar 04, 2012 at 08:32:26PM +0000, Blue Swirl wrote: > On Sun, Mar 4, 2012 at 20:02, Michael S. Tsirkin wrote= : > > On Sun, Mar 04, 2012 at 07:51:02PM +0000, Blue Swirl wrote: > >> On Sun, Mar 4, 2012 at 17:35, Michael S. Tsirkin wr= ote: > >> > On Sun, Mar 04, 2012 at 05:07:34PM +0000, Blue Swirl wrote: > >> >> On Sun, Mar 4, 2012 at 15:22, Michael S. Tsirkin = wrote: > >> >> > On Sun, Mar 04, 2012 at 02:35:28PM +0000, Blue Swirl wrote: > >> >> >> On Sun, Mar 4, 2012 at 14:23, Michael S. Tsirkin wrote: > >> >> >> > On Sun, Mar 04, 2012 at 01:38:38PM +0000, Blue Swirl wrote: > >> >> >> >> On Sun, Mar 4, 2012 at 13:28, Michael S. Tsirkin wrote: > >> >> >> >> > On Sun, Mar 04, 2012 at 12:37:57PM +0000, Blue Swirl wrot= e: > >> >> >> >> >> On Sun, Mar 4, 2012 at 12:21, Michael S. Tsirkin wrote: > >> >> >> >> >> > On Sun, Mar 04, 2012 at 10:27:24AM +0000, Blue Swirl w= rote: > >> >> >> >> >> >> On Sun, Mar 4, 2012 at 09:46, Michael S. Tsirkin wrote: > >> >> >> >> >> >> > commit 5caef97a16010f818ea8b950e2ee24ba876643ad int= roduced > >> >> >> >> >> >> > a regression: we do not make IO base/limit upper 16 > >> >> >> >> >> >> > bit registers writeable, so we should report a 16 b= it > >> >> >> >> >> >> > IO range type, not a 32 bit one. > >> >> >> >> >> >> > Note that PCI_PREF_RANGE_TYPE_32 is 0x0, but PCI_IO= _RANGE_TYPE_32 is 0x1. > >> >> >> >> >> >> > > >> >> >> >> >> >> > In particular, this broke sparc64. > >> >> >> >> >> >> > > >> >> >> >> >> >> > Note: this just reverts to behaviour prior to the p= atch. > >> >> >> >> >> >> > Making PCI_IO_BASE_UPPER16 and PCI_IO_LIMIT_UPPER16 > >> >> >> >> >> >> > registers writeable should, and seems to, work just= as well, but > >> >> >> >> >> >> > as no system seems to actually be interested in 32 = bit IO, > >> >> >> >> >> >> > let's not make unnecessary changes. > >> >> >> >> >> >> > > >> >> >> >> >> >> > Reported-by: Mark Cave-Ayland > >> >> >> >> >> >> > Signed-off-by: Michael S. Tsirkin > >> >> >> >> >> >> > > >> >> >> >> >> >> > Mark, can you confirm that this fixes the bug for y= ou? > >> >> >> >> >> >> > >> >> >> >> >> >> No, running > >> >> >> >> >> >> qemu-system-sparc64 -serial stdio > >> >> >> >> >> >> still shows black screen and the following on console= : > >> >> >> >> >> >> OpenBIOS for Sparc64 > >> >> >> >> >> >> Unhandled Exception 0x0000000000000032 > >> >> >> >> >> >> PC =3D 0x00000000ffd19e18 NPC =3D 0x00000000ffd19e1c > >> >> >> >> >> >> Stopping execution > >> >> >> >> >> > > >> >> >> >> >> > The weird thing is the range type does not seem to be = accessed > >> >> >> >> >> > at all. So I guessed there's some memory corruption he= re. > >> >> >> >> >> > Running valgrind shows this: > >> >> >> >> >> > > >> >> >> >> >> > --11114-- WARNING: unhandled syscall: 340 > >> >> >> >> >> > --11114-- You may be able to write your own handler. > >> >> >> >> >> > --11114-- Read the file README_MISSING_SYSCALL_OR_IOCT= L. > >> >> >> >> >> > --11114-- Nevertheless we consider this a bug. =C2=A0P= lease report > >> >> >> >> >> > --11114-- it at http://valgrind.org/support/bug_report= s.html. > >> >> >> >> >> > =3D=3D11114=3D=3D Invalid read of size 4 > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0at 0x2A68C0: pci_apb_in= it (apb_pci.c:350) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0by 0x2F7A84: sun4uv_ini= t (sun4u.c:779) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0by 0x13D716: main (vl.c= :3397) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0Address 0x156c7d30 is 0 bytes = after a block of size 64 > >> >> >> >> >> > alloc'd > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0at 0x557DD69: malloc (v= g_replace_malloc.c:236) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0by 0x225F56: malloc_and= _trace (vl.c:2156) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0by 0x584AFEC: ??? (in /= lib/libglib-2.0.so.0.2800.8) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0by 0x584B528: g_malloc0= (in /lib/libglib-2.0.so.0.2800.8) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0by 0x19C50C: qemu_alloc= ate_irqs (irq.c:47) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0by 0x2F7A4C: sun4uv_ini= t (sun4u.c:778) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0by 0x13D716: main (vl.c= :3397) > >> >> >> >> >> > =3D=3D11114=3D=3D > >> >> >> >> >> > apb: here > >> >> >> >> >> > =3D=3D11114=3D=3D Warning: client switching stacks? =C2= =A0SP change: 0xfec42cbc --> > >> >> >> >> >> > 0x16894008 > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0to= suppress, use: --max-stackframe=3D398791500 or > >> >> >> >> >> > greater > >> >> >> >> >> > =3D=3D11114=3D=3D Warning: client switching stacks? =C2= =A0SP change: 0x16893fa0 --> > >> >> >> >> >> > 0xfec42cc0 > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0to= suppress, use: --max-stackframe=3D398791392 or > >> >> >> >> >> > greater > >> >> >> >> >> > =3D=3D11114=3D=3D Warning: client switching stacks? =C2= =A0SP change: 0xfec42fe0 --> > >> >> >> >> >> > 0x16893fd0 > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0to= suppress, use: --max-stackframe=3D398790640 or > >> >> >> >> >> > greater > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0fu= rther instances of this message will not be shown. > >> >> >> >> >> > QEMU 1.0.50 monitor - type 'help' for more information > >> >> >> >> >> > (qemu) =3D=3D11114=3D=3D Thread 2: > >> >> >> >> >> > =3D=3D11114=3D=3D Conditional jump or move depends on = uninitialised value(s) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0at 0x2A8351: compute_al= l_sub (cc_helper.c:37) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0by 0x2A8782: helper_com= pute_psr (cc_helper.c:470) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0by 0x9AD9A19: ??? > >> >> >> >> >> > =3D=3D11114=3D=3D > >> >> >> >> >> > =3D=3D11114=3D=3D Conditional jump or move depends on = uninitialised value(s) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0at 0x2A827C: compute_al= l_sub_xcc (cc_helper.c:60) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0by 0x2A8795: helper_com= pute_psr (cc_helper.c:473) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0by 0x9AD9A19: ??? > >> >> >> >> >> > =3D=3D11114=3D=3D > >> >> >> >> >> > =3D=3D11114=3D=3D Conditional jump or move depends on = uninitialised value(s) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0at 0x2A8296: compute_al= l_sub_xcc (cc_helper.c:295) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0by 0x2A8795: helper_com= pute_psr (cc_helper.c:473) > >> >> >> >> >> > =3D=3D11114=3D=3D =C2=A0 =C2=A0by 0x9AD9A19: ??? > >> >> >> >> >> > =3D=3D11114=3D=3D > >> >> >> >> >> > > >> >> >> >> >> > Is the above a problem? > >> >> >> >> >> > >> >> >> >> >> It looks like Sparc does not reset registers at CPU rese= t. Nice catch. > >> >> >> >> > > >> >> >> >> > Invalid read and address after block are also worrying. > >> >> >> >> > > >> >> >> >> > irqs are allocated with > >> >> >> >> > =C2=A0#define MAX_PILS 16 > >> >> >> >> > > >> >> >> >> > =C2=A0 =C2=A0irq =3D qemu_allocate_irqs(cpu_set_irq, env,= MAX_PILS); > >> >> >> >> > > >> >> >> >> > then passed to apb: > >> >> >> >> > > >> >> >> >> > =C2=A0 =C2=A0pci_bus =3D pci_apb_init(APB_SPECIAL_BASE, A= PB_MEM_BASE, irq, &pci_bus2, > >> >> >> >> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 &pci_bus3); > >> >> >> >> > > >> >> >> >> > which does: > >> >> >> >> > PCIBus *pci_apb_init(target_phys_addr_t special_base, > >> >> >> >> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 target_phys_addr_t mem_base, > >> >> >> >> > =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 qemu_irq *pic, PCIBus **bus2, PCIBus **bus3) > >> >> >> >> > > >> >> >> >> > and > >> >> >> >> > > >> >> >> >> > =C2=A0 for (i =3D 0; i < 32; i++) { > >> >> >> >> > =C2=A0 =C2=A0 =C2=A0 =C2=A0sysbus_connect_irq(s, i, pic[i= ]); > >> >> >> >> > =C2=A0 =C2=A0} > >> >> >> >> > >> >> >> >> Awful. But using 32 for MAX_PILS does not help either. > >> >> >> > > >> >> >> > > >> >> >> > Could you please clarify what is the SABRE device? > >> >> >> > Is it, in fact, a bridge device? Or not? > >> >> >> > >> >> >> Yes, it's the host bridge, also known as PBM. It's documented = in > >> >> >> UltraSPARC IIi User's Manual > >> >> > > >> >> > Btw would be nice to host the manuals at qemu.org > >> >> > our code points at sun.com URLs :( > >> >> > >> >> I have most if not all manuals, downloaded from sun.com, but I'm = not > >> >> sure if they can be redistributed. > >> > > >> > Okay ... > >> > Let's change the link to point to some other place which has them? > >> > > >> >> > I am looking at 19.3.1 PCI Con=EF=AC=81guration Space > >> >> > and it appears to show that this is a regular device > >> >> > with a couple of custom registers at pffsets 0x40 > >> >> > and 0x41. > >> >> > > >> >> > Why do we want to pretend it is a bridge? > >> >> > >> >> It's the host bridge and the device class is PCI_CLASS_BRIDGE_HOS= T. > >> > > >> > Yes. But the *header* type is 0 (NORMAL) > >> > while the code in pci_init_mask_bridge > >> > which is the only user of the is_bridge register > >> > initializes a type 1 (BRIDGE) header. > >> > > >> > So it just happens to do a vaguely correct thing. > >> > >> Well, that is still according to device spec. > > > > I tried to find anything in the spec that says any register > > after 0x10 is implemented but failed. > > Can you tell me which chater and what it says? >=20 > 19.3.1.10 tells that the header type is 0, as you noted too. Still, > the register layout matches bridge spec instead, for example there are > bus number registers in place of BAR 2. Sorry I don't see this in 19.3.1 Where are these registers documented? In my spec all registers from 0x10 on are greyed out which it says above means 'not implemented'? My spec also says 'Base Address' for 0x10 - 0x27. I see bus number and subordinate bus number registers at 0x40 and 0x41, this is outside the configuration header. The spec also says they are unused. Are we looking at the same spec? Mine is copyright 1997. > This conflicts with bridge > spec 3.2.4.9. Maybe the device predates the specification. bridge spec 1.0 was released in 1994, 1.1 in 1998. This spec is from 1997, but the device might be older. > >> >> > > >> >> >> and there it says that the device is > >> >> >> found in the configuration space. > >> >> >> > >> >> >> The secondary bridges are Simbas and should be called APBs. > >> >> > > >> >> > As far as I can see from the code, it has header type > >> >> > NORMAL but sets is_bridge. > >> >> > This was done by this commit: > >> >> > 776e1bbb6cf4fe66a93c1a5dd814bbb650deca00 > >> >> > >> >> IIRC otherwise some registers are not writable. > >> > > >> > Yes but which ones? I looked at the manual and > >> > it does not list any registers. Playing with code, > >> > it looks like we just need to make *some* > >> > BAR writeable. I tried with > >> > pci_set_long(d->wmask + PCI_BASE_ADDRESS_0, 0xfffffff0); > >> > to > >> > pci_set_long(d->wmask + PCI_BASE_ADDRESS_5, 0xfffffff0); > >> > > >> > and any one of these makes bios get at least to > >> > the prompt. > >> > >> I now know the root cause of the problem. OpenBIOS programs the BARs > >> somewhat correctly just by accident. The initial io_base and mem_bas= e > >> for BARs are not correct, but because the host bridge BARs (and also= 6 > >> of which 4 are not even BARs!) are programmed first, the bases > >> happened to settle to values that happen to work. The commit reveale= d > >> the problem since the settling didn't happen. The mask changes just > >> let the host bridge setup continue to do the magic. > >> > >> By just changing OpenBIOS (see attached patch), I can get the device= s > >> to work (assuming that VGA is a separate problem). There's no need t= o > >> change QEMU. > >> > >> >> > > >> >> >> > > >> >> >> > > >> >> >> > -- > >> >> >> > MST > > > >> From 3f957e2dc8477f00f6d3a9491d81399ee750c725 Mon Sep 17 00:00:00 20= 01 > >> Message-Id: <3f957e2dc8477f00f6d3a9491d81399ee750c725.1330890410.git= .blauwirbel@gmail.com> > >> From: Blue Swirl > >> Date: Sun, 4 Mar 2012 19:46:38 +0000 > >> Subject: [PATCH] pci: fix BAR setup > >> > >> A change in QEMU on how PCI bridges are setup revealed > >> a bug in OpenBIOS PCI setup. On Sparc64, the BARs just > >> happened to get somewhat correct values by accident before > >> the commit but not after the change. > >> > >> Avoid to set up BARs for host bridge. Fix bridge > >> check, this lead to setting up 6 BARs instead of more > >> correct 2. If a bridge doesn't have any devices behind it, > >> disable it entirely. Fix Sparc64 PCI memory base. > >> > >> Signed-off-by: Blue Swirl > >> --- > >> =C2=A0arch/sparc64/openbios.c | =C2=A0 =C2=A02 +- > >> =C2=A0drivers/pci.c =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0 67 += +++++++++++++++++++++++++++++++++------------ > >> =C2=A0drivers/pci.h =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | =C2=A0 =C2=A0= 7 +++++ > >> =C2=A03 files changed, 57 insertions(+), 19 deletions(-) > >> > >> diff --git a/arch/sparc64/openbios.c b/arch/sparc64/openbios.c > >> index ac709fe..a1544a8 100644 > >> --- a/arch/sparc64/openbios.c > >> +++ b/arch/sparc64/openbios.c > >> @@ -64,7 +64,7 @@ static const struct hwdef hwdefs[] =3D { > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.cfg_base =3D APB_SP= ECIAL_BASE, > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.cfg_len =3D 0x20000= 00, > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.host_mem_base =3D A= PB_MEM_BASE, > >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.pci_mem_base =3D 0, > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.pci_mem_base =3D 0x10000= 000, > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.mem_len =3D 0x10000= 000, > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.io_base =3D APB_SPE= CIAL_BASE + 0x2000000ULL, // PCI Bus I/O space > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0.io_len =3D 0x10000, > >> diff --git a/drivers/pci.c b/drivers/pci.c > >> index f8c6414..6ed0c03 100644 > >> --- a/drivers/pci.c > >> +++ b/drivers/pci.c > >> @@ -966,11 +966,18 @@ static void ob_pci_configure_bar(pci_addr addr= , pci_config_t *config, > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0size =3D= min_align; > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0reloc =3D (reloc + size -1) & ~(si= ze - 1); > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (*io_base =3D=3D base) { > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0PCI_DPRINTF= ("changing io_base from 0x%lx to 0x%x\n", > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*io_base, reloc + size); > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*io_ba= se =3D reloc + size; > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0reloc = -=3D arch->io_base; > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else { > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0PCI_DPRINTF= ("changing mem_base from 0x%lx to 0x%x\n", > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*mem_base, reloc + size); > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0*mem_b= ase =3D reloc + size; > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0PCI_DPRINTF("Configuring BARs for %s: r= eloc 0x%x omask 0x%x " > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0"io_base 0x%lx mem_base 0x%lx\n", > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0config->path, reloc, *p_omask, *io_base, *mem_base); > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pci_config_write32(addr, config_ad= dr, reloc | *p_omask); > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0config->assigned[reg] =3D reloc | = *p_omask; > >> =C2=A0} > >> @@ -1021,26 +1028,30 @@ ob_pci_configure(pci_addr addr, pci_config_t= *config, int num_regs, int rom_bar, > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pci_config_write16(addr, PCI_COMMA= ND, cmd); > >> =C2=A0} > >> > >> -static void ob_configure_pci_device(const char* parent_path, > >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0int *bus_num, unsigned long *mem_base, = unsigned long *io_base, > >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0int bus, int devnum, int fn, int *p_is_= multi); > >> +static int ob_configure_pci_device(const char* parent_path, > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int *bus_num, unsign= ed long *mem_base, > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 unsigned long *io_ba= se, int bus, int devnum, > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 int fn, int *p_is_mu= lti); > >> > >> -static void ob_scan_pci_bus(int *bus_num, unsigned long *mem_base, > >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0unsigned long *io_base, const char *path, > >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int bus) > >> +static int ob_scan_pci_bus(int *bus_num, unsigned long *mem_base, > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 unsigned long *io_base, const char *path, > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 int bus) > >> =C2=A0{ > >> - =C2=A0 =C2=A0 int devnum, fn, is_multi; > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0int devnum, fn, is_multi, ndevices =3D = 0; > >> > >> =C2=A0 =C2=A0 =C2=A0 PCI_DPRINTF("\nScanning bus %d at %s...\n", bus= , path); > >> > >> =C2=A0 =C2=A0 =C2=A0 for (devnum =3D 0; devnum < 32; devnum++) { > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 is_multi =3D 0; > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 for (fn =3D 0; fn=3D= =3D0 || (is_multi && fn<8); fn++) { > >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ob_configu= re_pci_device(path, bus_num, mem_base, io_base, > >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 bus, devnum, fn, &is_multi); > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ndevices += =3D ob_configure_pci_device(path, bus_num, > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0mem_base, io_base= , > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0bus, devnum, fn, > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0&is_multi); > >> > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } > >> =C2=A0 =C2=A0 =C2=A0 } > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return ndevices; > >> =C2=A0} > >> > >> =C2=A0static void ob_configure_pci_bridge(pci_addr addr, > >> @@ -1048,6 +1059,9 @@ static void ob_configure_pci_bridge(pci_addr a= ddr, > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0unsigned l= ong *io_base, > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int primar= y_bus, pci_config_t *config) > >> =C2=A0{ > >> + =C2=A0 =C2=A0int ndevices; > >> + =C2=A0 =C2=A0uint8_t command; > >> + > >> =C2=A0 =C2=A0 =C2=A0config->primary_bus =3D primary_bus; > >> =C2=A0 =C2=A0 =C2=A0pci_config_write8(addr, PCI_PRIMARY_BUS, config-= >primary_bus); > >> > >> @@ -1062,16 +1076,30 @@ static void ob_configure_pci_bridge(pci_addr= addr, > >> > >> =C2=A0 =C2=A0 =C2=A0/* make pci bridge parent device, prepare for re= cursion */ > >> > >> - =C2=A0 =C2=A0ob_scan_pci_bus(bus_num, mem_base, io_base, > >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0config->path, config->secondary_bus); > >> + =C2=A0 =C2=A0ndevices =3D ob_scan_pci_bus(bus_num, mem_base, io_ba= se, > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 config->path, config->secondary_bu= s); > >> + =C2=A0 =C2=A0if (!ndevices) { > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0/* no devices, disable bridging */ > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0PCI_DPRINTF("disabling bridge %s\n", co= nfig->path); > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0command =3D pci_config_read8(addr, PCI_= COMMAND); > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0command &=3D ~(PCI_COMMAND_IO | PCI_COM= MAND_MEMORY | > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 PCI_COMMAND_VGA_PALETTE | PCI_COMMAND_MASTER); > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0pci_config_write8(addr, PCI_COMMAND, co= mmand); > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0pci_config_write8(addr, PCI_IO_BASE, 0)= ; > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0pci_config_write8(addr, PCI_IO_LIMIT, 0= ); > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0pci_config_write8(addr, PCI_MEMORY_BASE= , 0); > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0pci_config_write8(addr, PCI_MEMORY_LIMI= T, 0); > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return; > >> + =C2=A0 =C2=A0} > >> > >> =C2=A0 =C2=A0 =C2=A0/* bus scan updates *bus_num to last revealed pc= i bus number */ > >> =C2=A0 =C2=A0 =C2=A0config->subordinate_bus =3D *bus_num; > >> =C2=A0 =C2=A0 =C2=A0pci_config_write8(addr, PCI_SUBORDINATE_BUS, con= fig->subordinate_bus); > >> > >> - =C2=A0 =C2=A0PCI_DPRINTF("bridge %s PCI bus primary=3D%d secondary= =3D%d subordinate=3D%d\n", > >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0config->path, config->pri= mary_bus, config->secondary_bus, > >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0config->subordinate_bus); > >> + =C2=A0 =C2=A0PCI_DPRINTF("bridge %s PCI bus primary=3D%d secondary= =3D%d subordinate=3D%d" > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0" ndev=3D%d= \n", > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0config->pat= h, config->primary_bus, config->secondary_bus, > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0config->sub= ordinate_bus, ndevices); > >> > >> =C2=A0 =C2=A0 =C2=A0pci_set_bus_range(config); > >> =C2=A0} > >> @@ -1117,7 +1145,7 @@ static int ob_pci_read_identification(int bus,= int devnum, int fn, > >> =C2=A0 =C2=A0 =C2=A0return 1; > >> =C2=A0} > >> > >> -static void ob_configure_pci_device(const char* parent_path, > >> +static int ob_configure_pci_device(const char* parent_path, > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int *bus_num, unsigned long *mem_b= ase, unsigned long *io_base, > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0int bus, int devnum, int fn, int *= p_is_multi) > >> =C2=A0{ > >> @@ -1133,7 +1161,7 @@ static void ob_configure_pci_device(const char= * parent_path, > >> =C2=A0 =C2=A0 =C2=A0int is_host_bridge =3D 0; > >> > >> =C2=A0 =C2=A0 =C2=A0if (!ob_pci_read_identification(bus, devnum, fn,= &vid, &did, &class, &subclass)) { > >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0return; > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0; > >> =C2=A0 =C2=A0 =C2=A0} > >> > >> =C2=A0 =C2=A0 =C2=A0addr =3D PCI_ADDR(bus, devnum, fn); > >> @@ -1195,16 +1223,18 @@ static void ob_configure_pci_device(const ch= ar* parent_path, > >> > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (get_property(phandle, "vendor-= id", NULL)) { > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0PCI_DPRINTF("host br= idge already configured\n"); > >> - =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return; > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0; > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} > >> =C2=A0 =C2=A0 =C2=A0} > >> > >> =C2=A0 =C2=A0 =C2=A0activate_dev(phandle); > >> > >> - =C2=A0 =C2=A0if (htype & PCI_HEADER_TYPE_BRIDGE) { > >> + =C2=A0 =C2=A0if (htype & PCI_HEADER_TYPE_BRIDGE || (class =3D=3D P= CI_BASE_CLASS_BRIDGE)) { > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0PCI_DPRINTF("Bridge 2 bars, htype %x\n"= , htype); > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0num_bars =3D 2; > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rom_bar =C2=A0=3D PCI_ROM_ADDRESS1= ; > >> =C2=A0 =C2=A0 =C2=A0} else { > >> + =C2=A0 =C2=A0 =C2=A0 =C2=A0PCI_DPRINTF("Device 6 bars, htype %x\n"= , htype); > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0num_bars =3D 6; > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0rom_bar =C2=A0=3D PCI_ROM_ADDRESS; > >> =C2=A0 =C2=A0 =C2=A0} > >> @@ -1240,6 +1270,7 @@ static void ob_configure_pci_device(const char= * parent_path, > >> > >> =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ob_configure_pci_bridge(addr, bus_= num, mem_base, io_base, bus, &config); > >> =C2=A0 =C2=A0 =C2=A0} > >> + =C2=A0 =C2=A0return 1; > >> =C2=A0} > >> > >> =C2=A0int ob_pci_init(void) > >> diff --git a/drivers/pci.h b/drivers/pci.h > >> index 0f6ae1f..4314507 100644 > >> --- a/drivers/pci.h > >> +++ b/drivers/pci.h > >> @@ -7,6 +7,8 @@ > >> =C2=A0#define PCI_COMMAND =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x04 > >> =C2=A0#define =C2=A0PCI_COMMAND_IO =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A00x01 > >> =C2=A0#define =C2=A0PCI_COMMAND_MEMORY =C2=A00x02 > >> +#define =C2=A0PCI_COMMAND_MASTER =C2=A0 =C2=A0 0x4 =C2=A0 =C2=A0 /*= Enable bus mastering */ > >> +#define =C2=A0PCI_COMMAND_VGA_PALETTE 0x20 =C2=A0 /* Enable palette= snooping */ > >> > >> =C2=A0#define PCI_STATUS =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A00x06 =C2=A0 =C2=A0/* 16 bits */ > >> =C2=A0#define =C2=A0PCI_STATUS_CAP_LIST =C2=A0 =C2=A00x10 =C2=A0 =C2= =A0/* Support Capability List */ > >> @@ -44,6 +46,11 @@ > >> =C2=A0#define PCI_BASE_ADDR_4 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A00x20 > >> =C2=A0#define PCI_BASE_ADDR_5 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A00x24 > >> > >> +#define PCI_IO_BASE =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x1c = =C2=A0 =C2=A0/* I/O range behind the bridge */ > >> +#define PCI_IO_LIMIT =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A00x1d > >> +#define PCI_MEMORY_BASE =C2=A0 =C2=A0 =C2=A0 =C2=A0 0x20 =C2=A0 =C2= =A0/* Memory range behind */ > >> +#define PCI_MEMORY_LIMIT =C2=A0 =C2=A0 =C2=A0 =C2=A00x22 > >> + > >> =C2=A0#define PCI_SUBSYSTEM_VENDOR_ID 0x2c > >> =C2=A0#define PCI_SUBSYSTEM_ID =C2=A0 =C2=A0 =C2=A0 =C2=A00x2e > >> > >> -- > >> 1.7.2.5 > >> > >