From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:49557) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S4uev-0006Xz-Um for qemu-devel@nongnu.org; Tue, 06 Mar 2012 08:42:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S4ueX-0004mt-43 for qemu-devel@nongnu.org; Tue, 06 Mar 2012 08:42:33 -0500 Received: from mx1.redhat.com ([209.132.183.28]:10676) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S4ueW-0004me-Sk for qemu-devel@nongnu.org; Tue, 06 Mar 2012 08:42:09 -0500 Date: Tue, 6 Mar 2012 15:42:10 +0200 From: "Michael S. Tsirkin" Message-ID: <20120306134209.GD12096@redhat.com> References: <20120304152201.GC12776@redhat.com> <20120304173428.GA16058@redhat.com> <20120304200218.GH16058@redhat.com> <20120304212845.GI16058@redhat.com> <20120304222932.GA21671@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH] pci: fix bridge IO/BASE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: Mark Cave-Ayland , qemu-devel@nongnu.org, Anthony Liguori On Mon, Mar 05, 2012 at 06:34:51PM +0000, Blue Swirl wrote: > On Sun, Mar 4, 2012 at 22:29, Michael S. Tsirkin wrote: > > On Sun, Mar 04, 2012 at 09:54:02PM +0000, Blue Swirl wrote: > >> >> 19.3.1.10 tells that the header type is 0, as you noted too. Still, > >> >> the register layout matches bridge spec instead, for example there are > >> >> bus number registers in place of BAR 2. > >> > > >> > Sorry I don't see this in 19.3.1 > >> > Where are these registers documented? > >> > In my spec all registers from 0x10 on are greyed out which > >> > it says above means 'not implemented'? > >> > My spec also says 'Base Address' for 0x10 - 0x27. > >> > > >> > I see bus number and subordinate bus number > >> > registers at 0x40 and 0x41, this is outside > >> > the configuration header. The spec also says > >> > they are unused. > >> > >> Oh, I somehow read that they were in bridge locations 0x18 and 0x19. > >> Perhaps the is_bridge property should be removed after OpenBIOS no > >> longer wants to write to the registers. > > > > So we are in agreement then? > > The device seems to (more or less) go by the spec, > > QEMU is correct here as is your original commit. The only change > (beside bug fixes for the problems you found, thanks) should be for > is_bridge. You mean remove is_bridge? Right. > > but openbios gets confused, apparently by the absence of BARs. > > > > Can you try debugging openbios to see what is wrong? > > On second thought, I think 32 bit I/O was confusing OpenBIOS, probably > the host bridge device not so much. PCI handling in OpenBIOS should be > fixed. We can make IO 32 bit. Want to try? Anyway, so I won't revert this in core for now? > > -- > > MST