[Qemu-devel] [PATCH v2 2/3] Support for MRCC and MCRR instructions

[Alexey Starikovskiy <aystarik@gmail.com>]

Signed-off-by: Alexey Starikovskiy <aystarik@gmail.com>
---
 target-arm/helper.c    |   28 ++++++++++++++++++++++++++++
 target-arm/helper.h    |    2 ++
 target-arm/translate.c |   47 +++++++++++++++++++++++++++++------------------
 3 files changed, 59 insertions(+), 18 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index d190104..3c4c0e4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -670,6 +670,16 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
     cpu_abort(env, "cp15 insn %08x\n", insn);
 }
 
+void HELPER(set_cp15_64)(CPUState * env, uint32_t insn, uint64_t val)
+{
+    cpu_abort(env, "cp15 insn %08x\n", insn);
+}
+
+uint64_t HELPER(get_cp15_64)(CPUState * env, uint32_t insn)
+{
+    cpu_abort(env, "cp15 insn %08x\n", insn);
+}
+
 /* These should probably raise undefined insn exceptions.  */
 void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
 {
@@ -2261,6 +2271,24 @@ bad_reg:
     return 0;
 }
 
+void HELPER(set_cp15_64)(CPUState *env, uint32_t insn, uint64_t val)
+{
+    int crm = insn & 0xf;
+    int opc1 = (insn >> 4) & 0xf;
+    cpu_abort(env, "Unimplemented cp15 register 64bit write (c%d[%d])\n",
+              crm, opc1);
+}
+
+uint64_t HELPER(get_cp15_64)(CPUState *env, uint32_t insn)
+{
+    /* Used for block cache operations, so just return 0 */
+#if 0
+    cpu_abort(env, "Unimplemented cp15 register 64bit read (c%d[%d])\n",
+              crm, opc1);
+#endif
+    return 0;
+}
+
 void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
 {
     if ((env->uncached_cpsr & CPSR_M) == mode) {
diff --git a/target-arm/helper.h b/target-arm/helper.h
index 16dd5fc..bc8151c 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -60,7 +60,9 @@ DEF_HELPER_3(v7m_msr, void, env, i32, i32)
 DEF_HELPER_2(v7m_mrs, i32, env, i32)
 
 DEF_HELPER_3(set_cp15, void, env, i32, i32)
+DEF_HELPER_3(set_cp15_64, void, env, i32, i64)
 DEF_HELPER_2(get_cp15, i32, env, i32)
+DEF_HELPER_2(get_cp15_64, i64, env, i32)
 
 DEF_HELPER_3(set_cp, void, env, i32, i32)
 DEF_HELPER_2(get_cp, i32, env, i32)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 280bfca..27ba5fb 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -2559,17 +2559,9 @@ static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
 
     /* M profile cores use memory mapped registers instead of cp15.  */
     if (arm_feature(env, ARM_FEATURE_M))
-	return 1;
+        return 1;
 
-    if ((insn & (1 << 25)) == 0) {
-        if (insn & (1 << 20)) {
-            /* mrrc */
-            return 1;
-        }
-        /* mcrr.  Used for block cache operations, so implement as no-op.  */
-        return 0;
-    }
-    if ((insn & (1 << 4)) == 0) {
+    if ((insn & (1 << 4)) == 0 && (insn & (1 << 25))) {
         /* cdp */
         return 1;
     }
@@ -2636,16 +2628,35 @@ static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
 
     tmp2 = tcg_const_i32(insn);
     if (insn & ARM_CP_RW_BIT) {
-        tmp = tcg_temp_new_i32();
-        gen_helper_get_cp15(tmp, cpu_env, tmp2);
-        /* If the destination register is r15 then sets condition codes.  */
-        if (rd != 15)
-            store_reg(s, rd, tmp);
-        else
-            tcg_temp_free_i32(tmp);
+        if ((insn & (1 << 25))) {
+            tmp = tcg_temp_new_i32();
+            gen_helper_get_cp15(tmp, cpu_env, tmp2);
+            /* If the destination register is r15 then sets condition codes.  */
+            if (rd != 15) {
+                store_reg(s, rd, tmp);
+            } else {
+                tcg_temp_free_i32(tmp);
+            }
+        } else {
+            int rd1 = (insn >> 16) & 0xf;
+            TCGv_i64 tmp1 = tcg_temp_new_i64();
+            gen_helper_get_cp15_64(tmp1, cpu_env, tmp2);
+            tcg_gen_trunc_i64_i32(cpu_R[rd], tmp1);
+            tcg_gen_shri_i64(tmp1, tmp1, 32);
+            tcg_gen_trunc_i64_i32(cpu_R[rd1], tmp1);
+            tcg_temp_free_i64(tmp1);
+        }
     } else {
         tmp = load_reg(s, rd);
-        gen_helper_set_cp15(cpu_env, tmp2, tmp);
+        if ((insn & (1 << 25))) {
+            gen_helper_set_cp15(cpu_env, tmp2, tmp);
+        } else {
+            int rd1 = (insn >> 16) & 0xf;
+            TCGv_i64 tmp1 = tcg_temp_new_i64();
+            tcg_gen_concat_i32_i64(tmp1, cpu_R[rd], cpu_R[rd1]);
+            gen_helper_set_cp15_64(cpu_env, tmp2, tmp1);
+            tcg_temp_free_i64(tmp1);
+        }
         tcg_temp_free_i32(tmp);
         /* Normally we would always end the TB here, but Linux
          * arch/arm/mach-pxa/sleep.S expects two instructions following