From: Paul Brook <paul@codesourcery.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "QEMU Developers" <qemu-devel@nongnu.org>,
"Anthony Liguori" <anthony@codemonkey.ws>,
"Andreas Färber" <afaerber@suse.de>
Subject: Re: [Qemu-devel] ARM QOM conversion / class hierarchy
Date: Tue, 20 Mar 2012 14:08:55 +0000 [thread overview]
Message-ID: <201203201408.56275.paul@codesourcery.com> (raw)
In-Reply-To: <CAFEAcA_PZ-ZdbhFCWw=oHzPLNJWdx4fKA-qaHxLmuW1pwDNq9w@mail.gmail.com>
> Option two looks kind of nice, but I'm not sure whether it would
> actually work. I think you could do 95% of what you need for a
> different CPU that way (lots of properties for "value of ID_MMFR1",
> "value of "ID_MMFR2", "reset value of SCTLR", etc etc, plus properties
> for all our existing ARM_FEATURE_*, and some new ones where we're
> currently keying off "which CPU is this?" rather than using a feature
> bit, or just failing to distinguish things which aren't really
> common to all CPUs). But I'm not sure how you'd handle the genuinely
> implementation specific cp15 registers (eg cp15 crn=15). We could
> have a property which says "is this a 926/1026/1176/A8/A9/..." (or
> equivalently, key off the relevant fields of the main ID register) but
> it doesn't seem very OO-like to have one class whose behaviour changes
> based on an integer that's basically defining an ad-hoc sub-type...
IIUC the "proper OO" solution to this requires multiple inheritance, which we
don't have. The problem with subtyping is we can use it for at most one
characteristic. Everything else ends up being pushed into a common base class
and controlled by feature bits (or equivalent).
If we're going to use the class hierachy to implement functionality then there
are other candidates. Given the primary purpose of QOM is [IMO] to handle
interaction between devices, the external interface exposed by the core seems
like a better candidate for subclassing. i.e. conventional ARM cores with IRQ
and FIQ inputs[1] v.s. M profile devices where the core exception model is
intimately tied to the interrupt controller.
Paul
[1] This still applies to things like the Cortex-A9. In practice ARM may sell
you an SMP "cluster", but logically it's still a couple of normal cores and an
interrupt controller.
next prev parent reply other threads:[~2012-03-20 14:09 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-03-20 12:12 [Qemu-devel] ARM QOM conversion / class hierarchy Peter Maydell
2012-03-20 14:08 ` Paul Brook [this message]
2012-03-20 14:59 ` Peter Maydell
2012-03-20 16:06 ` Paul Brook
2012-03-20 16:20 ` Peter Maydell
2012-03-20 17:14 ` Paul Brook
2012-03-20 17:19 ` Peter Maydell
2012-03-20 16:56 ` Anthony Liguori
2012-03-20 17:14 ` Paul Brook
2012-03-20 17:20 ` Andreas Färber
2012-03-20 16:31 ` Michael Roth
2012-03-20 16:32 ` Peter Maydell
2012-03-20 19:04 ` Michael Roth
2012-03-20 17:01 ` Paul Brook
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