* [Qemu-devel] [PATCH 01/36] vmstate: Simplify test for CPU_SAVE_VERSION
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-21 20:35 ` Michael Roth
2012-03-19 22:57 ` [Qemu-devel] [PATCH 02/36] vmstate: make all architectures export a way to migrate cpu's Juan Quintela
` (35 subsequent siblings)
36 siblings, 1 reply; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Some cpu's definitions define CPU_SAVE_VERSION, others not, but they have
defined cpu_save/load.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
exec.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/exec.c b/exec.c
index 265e895..9389a61 100644
--- a/exec.c
+++ b/exec.c
@@ -657,7 +657,7 @@ void cpu_exec_init_all(void)
#endif
}
-#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
static int cpu_common_post_load(void *opaque, int version_id)
{
@@ -724,11 +724,13 @@ void cpu_exec_init(CPUArchState *env)
#if defined(CONFIG_USER_ONLY)
cpu_list_unlock();
#endif
-#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
+#if !defined(CONFIG_USER_ONLY)
vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env);
+#if defined(CPU_SAVE_VERSION)
register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
cpu_save, cpu_load, env);
#endif
+#endif
}
/* Allocate a new translation block. Flush the translation buffer if
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH 01/36] vmstate: Simplify test for CPU_SAVE_VERSION
2012-03-19 22:57 ` [Qemu-devel] [PATCH 01/36] vmstate: Simplify test for CPU_SAVE_VERSION Juan Quintela
@ 2012-03-21 20:35 ` Michael Roth
0 siblings, 0 replies; 60+ messages in thread
From: Michael Roth @ 2012-03-21 20:35 UTC (permalink / raw)
To: Juan Quintela; +Cc: qemu-devel
On Mon, Mar 19, 2012 at 11:57:29PM +0100, Juan Quintela wrote:
> Some cpu's definitions define CPU_SAVE_VERSION, others not, but they have
> defined cpu_save/load.
I'm guessing this patch becomes useful later in the series, but as it stands
I'm not seeing where this helps with cpus like target-alpha that have
cpu_save/load defined but not CPU_SAVE_VERSION, except to save off common
cpu fields as opposed to before when we saved nothing. Maybe a
add CPU_SAVE_SUPPORTED and check that instead? Or merge this elsewhere in
the series?
>
> Signed-off-by: Juan Quintela <quintela@redhat.com>
> ---
> exec.c | 6 ++++--
> 1 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/exec.c b/exec.c
> index 265e895..9389a61 100644
> --- a/exec.c
> +++ b/exec.c
> @@ -657,7 +657,7 @@ void cpu_exec_init_all(void)
> #endif
> }
>
> -#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
> +#if !defined(CONFIG_USER_ONLY)
>
> static int cpu_common_post_load(void *opaque, int version_id)
> {
> @@ -724,11 +724,13 @@ void cpu_exec_init(CPUArchState *env)
> #if defined(CONFIG_USER_ONLY)
> cpu_list_unlock();
> #endif
> -#if defined(CPU_SAVE_VERSION) && !defined(CONFIG_USER_ONLY)
> +#if !defined(CONFIG_USER_ONLY)
> vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env);
> +#if defined(CPU_SAVE_VERSION)
> register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
> cpu_save, cpu_load, env);
> #endif
> +#endif
> }
>
> /* Allocate a new translation block. Flush the translation buffer if
> --
> 1.7.7.6
>
>
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH 02/36] vmstate: make all architectures export a way to migrate cpu's
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 01/36] vmstate: Simplify test for CPU_SAVE_VERSION Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 03/36] vmstate: unicore32 don't support cpu migration Juan Quintela
` (34 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
This makes several changes:
- exports VMStateDescription vmstate_cpu non-static.
- makes sure that every cpu has a vmstate_cpu or cpu_save/load defined
- for the architecture that had nothing, it just register the cpu as unmigratable.
- Depending on CPU_SAVE_VERSION we register old/new migration style
- Add copyrights to the new files
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
exec.c | 2 ++
target-alpha/machine.c | 12 +-----------
target-i386/machine.c | 2 +-
target-lm32/machine.c | 2 +-
target-m68k/machine.c | 21 +++++++++++++++++++++
target-s390x/machine.c | 14 ++++++--------
target-sh4/machine.c | 21 +++++++++++++++++++++
target-xtensa/machine.c | 14 ++++++--------
vmstate.h | 2 ++
9 files changed, 61 insertions(+), 29 deletions(-)
diff --git a/exec.c b/exec.c
index 9389a61..c0f9c2e 100644
--- a/exec.c
+++ b/exec.c
@@ -729,6 +729,8 @@ void cpu_exec_init(CPUArchState *env)
#if defined(CPU_SAVE_VERSION)
register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
cpu_save, cpu_load, env);
+#else
+ vmstate_register(NULL, cpu_index, &vmstate_cpu, env);
#endif
#endif
}
diff --git a/target-alpha/machine.c b/target-alpha/machine.c
index 1c9edd1..8b3b42e 100644
--- a/target-alpha/machine.c
+++ b/target-alpha/machine.c
@@ -68,20 +68,10 @@ static VMStateField vmstate_cpu_fields[] = {
VMSTATE_END_OF_LIST()
};
-static const VMStateDescription vmstate_cpu = {
+const VMStateDescription vmstate_cpu = {
.name = "cpu",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = vmstate_cpu_fields,
};
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
- vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}
diff --git a/target-i386/machine.c b/target-i386/machine.c
index a8be058..fc37738 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -346,7 +346,7 @@ static const VMStateDescription vmstate_msr_ia32_misc_enable = {
}
};
-static const VMStateDescription vmstate_cpu = {
+const VMStateDescription vmstate_cpu = {
.name = "cpu",
.version_id = CPU_SAVE_VERSION,
.minimum_version_id = 3,
diff --git a/target-lm32/machine.c b/target-lm32/machine.c
index 6802e81..ed71bc4 100644
--- a/target-lm32/machine.c
+++ b/target-lm32/machine.c
@@ -1,7 +1,7 @@
#include "hw/hw.h"
#include "hw/boards.h"
-static const VMStateDescription vmstate_cpu = {
+const VMStateDescription vmstate_cpu = {
.name = "cpu",
.version_id = CPU_SAVE_VERSION,
.minimum_version_id = 1,
diff --git a/target-m68k/machine.c b/target-m68k/machine.c
index e69de29..7c89d4f 100644
--- a/target-m68k/machine.c
+++ b/target-m68k/machine.c
@@ -0,0 +1,21 @@
+/*
+ * Migration support for m68k cpus
+ *
+ * Copyright (C) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ * Juan Quintela <quintela@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later. See the COPYING file in the top-level directory.
+ */
+
+#include "hw/hw.h"
+
+/* To make this architecture migratable, we need to define cpu state
+ here. Other things need to be done elsewhere */
+
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
diff --git a/target-s390x/machine.c b/target-s390x/machine.c
index 3e79be6..5a7b219 100644
--- a/target-s390x/machine.c
+++ b/target-s390x/machine.c
@@ -18,13 +18,11 @@
*/
#include "hw/hw.h"
-#include "hw/boards.h"
-void cpu_save(QEMUFile *f, void *opaque)
-{
-}
+/* To make this architecture migratable, we need to define cpu state
+ here. Other things need to be done elsewhere */
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return 0;
-}
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
diff --git a/target-sh4/machine.c b/target-sh4/machine.c
index e69de29..b97355d 100644
--- a/target-sh4/machine.c
+++ b/target-sh4/machine.c
@@ -0,0 +1,21 @@
+/*
+ * Migration support for sh4 cpus
+ *
+ * Copyright (C) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ * Juan Quintela <quintela@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later. See the COPYING file in the top-level directory.
+ */
+
+#include "hw/hw.h"
+
+/* To make this architecture migratable, we need to define cpu state
+ here. Other things need to be done elsewhere */
+
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
diff --git a/target-xtensa/machine.c b/target-xtensa/machine.c
index ddeffb2..3f98330 100644
--- a/target-xtensa/machine.c
+++ b/target-xtensa/machine.c
@@ -26,13 +26,11 @@
*/
#include "hw/hw.h"
-#include "hw/boards.h"
-void cpu_save(QEMUFile *f, void *opaque)
-{
-}
+/* To make this architecture migratable, we need to define cpu state
+ here. Other things need to be done elsewhere */
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return 0;
-}
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
diff --git a/vmstate.h b/vmstate.h
index 82d97ae..1a4a60b 100644
--- a/vmstate.h
+++ b/vmstate.h
@@ -134,6 +134,8 @@ extern const VMStateInfo vmstate_info_timer;
extern const VMStateInfo vmstate_info_buffer;
extern const VMStateInfo vmstate_info_unused_buffer;
+extern const VMStateDescription vmstate_cpu;
+
#define type_check_array(t1,t2,n) ((t1(*)[n])0 - (t2*)0)
#define type_check_pointer(t1,t2) ((t1**)0 - (t2*)0)
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 03/36] vmstate: unicore32 don't support cpu migration
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 01/36] vmstate: Simplify test for CPU_SAVE_VERSION Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 02/36] vmstate: make all architectures export a way to migrate cpu's Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-21 20:49 ` Michael Roth
2012-03-19 22:57 ` [Qemu-devel] [PATCH 04/36] vmstate: use new cpu style for x86 Juan Quintela
` (33 subsequent siblings)
36 siblings, 1 reply; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-unicore32/cpu.h | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
index a3f8589..be85250 100644
--- a/target-unicore32/cpu.h
+++ b/target-unicore32/cpu.h
@@ -134,8 +134,6 @@ int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
int mmu_idx);
-#define CPU_SAVE_VERSION 2
-
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH 03/36] vmstate: unicore32 don't support cpu migration
2012-03-19 22:57 ` [Qemu-devel] [PATCH 03/36] vmstate: unicore32 don't support cpu migration Juan Quintela
@ 2012-03-21 20:49 ` Michael Roth
0 siblings, 0 replies; 60+ messages in thread
From: Michael Roth @ 2012-03-21 20:49 UTC (permalink / raw)
To: Juan Quintela; +Cc: qemu-devel
On Mon, Mar 19, 2012 at 11:57:31PM +0100, Juan Quintela wrote:
> Signed-off-by: Juan Quintela <quintela@redhat.com>
> ---
> target-unicore32/cpu.h | 2 --
> 1 files changed, 0 insertions(+), 2 deletions(-)
>
> diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
> index a3f8589..be85250 100644
> --- a/target-unicore32/cpu.h
> +++ b/target-unicore32/cpu.h
> @@ -134,8 +134,6 @@ int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
> int uc32_cpu_handle_mmu_fault(CPUUniCore32State *env, target_ulong address, int rw,
> int mmu_idx);
>
> -#define CPU_SAVE_VERSION 2
> -
Would it be pretty straightforward to give this the same treatment as
the cpus in #2? Would be nice to have a migration blocker registered
rather than just continuing to allow users to try it hopelessly.
> /* MMU modes definitions */
> #define MMU_MODE0_SUFFIX _kernel
> #define MMU_MODE1_SUFFIX _user
> --
> 1.7.7.6
>
>
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH 04/36] vmstate: use new cpu style for x86
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (2 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 03/36] vmstate: unicore32 don't support cpu migration Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 05/36] vmstate: use new style for lm32 cpus Juan Quintela
` (32 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-i386/cpu.h | 2 --
target-i386/machine.c | 12 +-----------
2 files changed, 1 insertions(+), 13 deletions(-)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index a1ed3e7..b2eeb9b 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -964,8 +964,6 @@ uint64_t cpu_get_tsc(CPUX86State *env);
#define cpu_list_id x86_cpu_list
#define cpudef_setup x86_cpudef_setup
-#define CPU_SAVE_VERSION 12
-
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
diff --git a/target-i386/machine.c b/target-i386/machine.c
index fc37738..127c44f 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -348,7 +348,7 @@ static const VMStateDescription vmstate_msr_ia32_misc_enable = {
const VMStateDescription vmstate_cpu = {
.name = "cpu",
- .version_id = CPU_SAVE_VERSION,
+ .version_id = 12,
.minimum_version_id = 3,
.minimum_version_id_old = 3,
.pre_save = cpu_pre_save,
@@ -467,13 +467,3 @@ const VMStateDescription vmstate_cpu = {
}
}
};
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
- vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 05/36] vmstate: use new style for lm32 cpus
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (3 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 04/36] vmstate: use new cpu style for x86 Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 06/36] vmstate: make microblaze cpus not migrateable Juan Quintela
` (31 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-lm32/cpu.h | 2 --
target-lm32/machine.c | 14 ++------------
2 files changed, 2 insertions(+), 14 deletions(-)
diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
index a7d9546..136a911 100644
--- a/target-lm32/cpu.h
+++ b/target-lm32/cpu.h
@@ -204,8 +204,6 @@ void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value);
#define cpu_gen_code cpu_lm32_gen_code
#define cpu_signal_handler cpu_lm32_signal_handler
-#define CPU_SAVE_VERSION 1
-
int cpu_lm32_handle_mmu_fault(CPULM32State *env, target_ulong address, int rw,
int mmu_idx);
#define cpu_handle_mmu_fault cpu_lm32_handle_mmu_fault
diff --git a/target-lm32/machine.c b/target-lm32/machine.c
index ed71bc4..24db6c0 100644
--- a/target-lm32/machine.c
+++ b/target-lm32/machine.c
@@ -3,10 +3,10 @@
const VMStateDescription vmstate_cpu = {
.name = "cpu",
- .version_id = CPU_SAVE_VERSION,
+ .version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
- .fields = (VMStateField[]) {
+ .fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(regs, CPULM32State, 32),
VMSTATE_UINT32(pc, CPULM32State),
VMSTATE_UINT32(ie, CPULM32State),
@@ -21,13 +21,3 @@ const VMStateDescription vmstate_cpu = {
VMSTATE_END_OF_LIST()
}
};
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
- vmstate_save_state(f, &vmstate_cpu, opaque);
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return vmstate_load_state(f, &vmstate_cpu, opaque, version_id);
-}
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 06/36] vmstate: make microblaze cpus not migrateable
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (4 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 05/36] vmstate: use new style for lm32 cpus Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 07/36] vmstate: port cris cpu to vmstate Juan Quintela
` (30 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-microblaze/cpu.h | 2 --
target-microblaze/machine.c | 26 ++++++++++++++++++--------
2 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 33b23c2..c7ea041 100644
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -294,8 +294,6 @@ enum {
#define cpu_gen_code cpu_mb_gen_code
#define cpu_signal_handler cpu_mb_signal_handler
-#define CPU_SAVE_VERSION 1
-
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _nommu
#define MMU_MODE1_SUFFIX _kernel
diff --git a/target-microblaze/machine.c b/target-microblaze/machine.c
index 1be1c35..13abf6a 100644
--- a/target-microblaze/machine.c
+++ b/target-microblaze/machine.c
@@ -1,11 +1,21 @@
+/*
+ * Migration support for microblaze cpus
+ *
+ * Copyright (C) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ * Juan Quintela <quintela@redhat.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later. See the COPYING file in the top-level directory.
+ */
+
#include "hw/hw.h"
-#include "hw/boards.h"
-void cpu_save(QEMUFile *f, void *opaque)
-{
-}
+/* To make this architecture migratable, we need to define cpu state
+ here. Other things need to be done elsewhere */
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- return 0;
-}
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .unmigratable = 1,
+};
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 07/36] vmstate: port cris cpu to vmstate
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (5 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 06/36] vmstate: make microblaze cpus not migrateable Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 08/36] vmstate: machine.c is only compiled for !CONFIG_USER_ONLY Juan Quintela
` (29 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Have to define TLBSet struct.
Multidimensional arrays in C are a mess, just unroll them.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-cris/cpu.h | 13 ++---
target-cris/machine.c | 138 +++++++++++++++++++------------------------------
2 files changed, 60 insertions(+), 91 deletions(-)
diff --git a/target-cris/cpu.h b/target-cris/cpu.h
index 31899c2..423a527 100644
--- a/target-cris/cpu.h
+++ b/target-cris/cpu.h
@@ -104,6 +104,11 @@
#define NB_MMU_MODES 2
+typedef struct {
+ uint32_t hi;
+ uint32_t lo;
+} TLBSet;
+
typedef struct CPUCRISState {
uint32_t regs[16];
/* P0 - P15 are referred to as special registers in the docs. */
@@ -157,11 +162,7 @@ typedef struct CPUCRISState {
*
* One for I and another for D.
*/
- struct
- {
- uint32_t hi;
- uint32_t lo;
- } tlbsets[2][4][16];
+ TLBSet tlbsets[2][4][16];
CPU_COMMON
@@ -219,8 +220,6 @@ enum {
#define cpu_gen_code cpu_cris_gen_code
#define cpu_signal_handler cpu_cris_signal_handler
-#define CPU_SAVE_VERSION 1
-
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
diff --git a/target-cris/machine.c b/target-cris/machine.c
index 8f9c0dd..1b96265 100644
--- a/target-cris/machine.c
+++ b/target-cris/machine.c
@@ -1,90 +1,60 @@
#include "hw/hw.h"
#include "hw/boards.h"
-void cpu_save(QEMUFile *f, void *opaque)
-{
- CPUCRISState *env = opaque;
- int i;
- int s;
- int mmu;
-
- for (i = 0; i < 16; i++)
- qemu_put_be32(f, env->regs[i]);
- for (i = 0; i < 16; i++)
- qemu_put_be32(f, env->pregs[i]);
-
- qemu_put_be32(f, env->pc);
- qemu_put_be32(f, env->ksp);
-
- qemu_put_be32(f, env->dslot);
- qemu_put_be32(f, env->btaken);
- qemu_put_be32(f, env->btarget);
-
- qemu_put_be32(f, env->cc_op);
- qemu_put_be32(f, env->cc_mask);
- qemu_put_be32(f, env->cc_dest);
- qemu_put_be32(f, env->cc_src);
- qemu_put_be32(f, env->cc_result);
- qemu_put_be32(f, env->cc_size);
- qemu_put_be32(f, env->cc_x);
-
- for (s = 0; s < 4; s++) {
- for (i = 0; i < 16; i++)
- qemu_put_be32(f, env->sregs[s][i]);
- }
-
- qemu_put_be32(f, env->mmu_rand_lfsr);
- for (mmu = 0; mmu < 2; mmu++) {
- for (s = 0; s < 4; s++) {
- for (i = 0; i < 16; i++) {
- qemu_put_be32(f, env->tlbsets[mmu][s][i].lo);
- qemu_put_be32(f, env->tlbsets[mmu][s][i].hi);
- }
- }
+static const VMStateDescription vmstate_tlbset = {
+ .name = "cpu/tlbset",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(lo, TLBSet),
+ VMSTATE_UINT32(hi, TLBSet),
+ VMSTATE_END_OF_LIST()
}
-}
-
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- CPUCRISState *env = opaque;
- int i;
- int s;
- int mmu;
-
- for (i = 0; i < 16; i++)
- env->regs[i] = qemu_get_be32(f);
- for (i = 0; i < 16; i++)
- env->pregs[i] = qemu_get_be32(f);
-
- env->pc = qemu_get_be32(f);
- env->ksp = qemu_get_be32(f);
-
- env->dslot = qemu_get_be32(f);
- env->btaken = qemu_get_be32(f);
- env->btarget = qemu_get_be32(f);
-
- env->cc_op = qemu_get_be32(f);
- env->cc_mask = qemu_get_be32(f);
- env->cc_dest = qemu_get_be32(f);
- env->cc_src = qemu_get_be32(f);
- env->cc_result = qemu_get_be32(f);
- env->cc_size = qemu_get_be32(f);
- env->cc_x = qemu_get_be32(f);
-
- for (s = 0; s < 4; s++) {
- for (i = 0; i < 16; i++)
- env->sregs[s][i] = qemu_get_be32(f);
- }
-
- env->mmu_rand_lfsr = qemu_get_be32(f);
- for (mmu = 0; mmu < 2; mmu++) {
- for (s = 0; s < 4; s++) {
- for (i = 0; i < 16; i++) {
- env->tlbsets[mmu][s][i].lo = qemu_get_be32(f);
- env->tlbsets[mmu][s][i].hi = qemu_get_be32(f);
- }
- }
+};
+
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, CPUCRISState, 16),
+ VMSTATE_UINT32_ARRAY(pregs, CPUCRISState, 16),
+ VMSTATE_UINT32(pc, CPUCRISState),
+ VMSTATE_UINT32(ksp, CPUCRISState),
+ VMSTATE_INT32(dslot, CPUCRISState),
+ VMSTATE_INT32(btaken, CPUCRISState),
+ VMSTATE_UINT32(btarget, CPUCRISState),
+ VMSTATE_UINT32(cc_op, CPUCRISState),
+ VMSTATE_UINT32(cc_mask, CPUCRISState),
+ VMSTATE_UINT32(cc_dest, CPUCRISState),
+ VMSTATE_UINT32(cc_src, CPUCRISState),
+ VMSTATE_UINT32(cc_result, CPUCRISState),
+ VMSTATE_INT32(cc_size, CPUCRISState),
+ VMSTATE_INT32(cc_x, CPUCRISState),
+ VMSTATE_UINT32_ARRAY(sregs[0], CPUCRISState, 16),
+ VMSTATE_UINT32_ARRAY(sregs[1], CPUCRISState, 16),
+ VMSTATE_UINT32_ARRAY(sregs[2], CPUCRISState, 16),
+ VMSTATE_UINT32_ARRAY(sregs[3], CPUCRISState, 16),
+ VMSTATE_UINT32(mmu_rand_lfsr, CPUCRISState),
+ VMSTATE_STRUCT_ARRAY(tlbsets[0][0], CPUCRISState, 16, 0,
+ vmstate_tlbset, TLBSet),
+ VMSTATE_STRUCT_ARRAY(tlbsets[0][1], CPUCRISState, 16, 0,
+ vmstate_tlbset, TLBSet),
+ VMSTATE_STRUCT_ARRAY(tlbsets[0][2], CPUCRISState, 16, 0,
+ vmstate_tlbset, TLBSet),
+ VMSTATE_STRUCT_ARRAY(tlbsets[0][3], CPUCRISState, 16, 0,
+ vmstate_tlbset, TLBSet),
+ VMSTATE_STRUCT_ARRAY(tlbsets[1][0], CPUCRISState, 16, 0,
+ vmstate_tlbset, TLBSet),
+ VMSTATE_STRUCT_ARRAY(tlbsets[1][1], CPUCRISState, 16, 0,
+ vmstate_tlbset, TLBSet),
+ VMSTATE_STRUCT_ARRAY(tlbsets[1][2], CPUCRISState, 16, 0,
+ vmstate_tlbset, TLBSet),
+ VMSTATE_STRUCT_ARRAY(tlbsets[1][3], CPUCRISState, 16, 0,
+ vmstate_tlbset, TLBSet),
+ VMSTATE_END_OF_LIST()
}
+};
- return 0;
-}
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 08/36] vmstate: machine.c is only compiled for !CONFIG_USER_ONLY
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (6 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 07/36] vmstate: port cris cpu to vmstate Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-21 18:09 ` Andreas Färber
2012-03-21 19:20 ` Peter Maydell
2012-03-19 22:57 ` [Qemu-devel] [PATCH 09/36] vmstate: introduce float32 arrays Juan Quintela
` (28 subsequent siblings)
36 siblings, 2 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-ppc/machine.c | 8 --------
1 files changed, 0 insertions(+), 8 deletions(-)
diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index 70e2582..d6c2ee4 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -32,7 +32,6 @@ void cpu_save(QEMUFile *f, void *opaque)
}
qemu_put_be32s(f, &env->fpscr);
qemu_put_sbe32s(f, &env->access_type);
-#if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
qemu_put_betls(f, &env->asr);
qemu_put_sbe32s(f, &env->slb_nr);
@@ -62,7 +61,6 @@ void cpu_save(QEMUFile *f, void *opaque)
}
for (i = 0; i < 4; i++)
qemu_put_betls(f, &env->pb[i]);
-#endif
for (i = 0; i < 1024; i++)
qemu_put_betls(f, &env->spr[i]);
qemu_put_be32s(f, &env->vscr);
@@ -72,7 +70,6 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_be32s(f, &env->flags);
qemu_put_sbe32s(f, &env->error_code);
qemu_put_be32s(f, &env->pending_interrupts);
-#if !defined(CONFIG_USER_ONLY)
qemu_put_be32s(f, &env->irq_input_state);
for (i = 0; i < POWERPC_EXCP_NB; i++)
qemu_put_betls(f, &env->excp_vectors[i]);
@@ -81,7 +78,6 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_betls(f, &env->ivor_mask);
qemu_put_betls(f, &env->ivpr_mask);
qemu_put_betls(f, &env->hreset_vector);
-#endif
qemu_put_betls(f, &env->nip);
qemu_put_betls(f, &env->hflags);
qemu_put_betls(f, &env->hflags_nmsr);
@@ -120,7 +116,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
}
qemu_get_be32s(f, &env->fpscr);
qemu_get_sbe32s(f, &env->access_type);
-#if !defined(CONFIG_USER_ONLY)
#if defined(TARGET_PPC64)
qemu_get_betls(f, &env->asr);
qemu_get_sbe32s(f, &env->slb_nr);
@@ -150,7 +145,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
}
for (i = 0; i < 4; i++)
qemu_get_betls(f, &env->pb[i]);
-#endif
for (i = 0; i < 1024; i++)
qemu_get_betls(f, &env->spr[i]);
ppc_store_sdr1(env, sdr1);
@@ -161,7 +155,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_be32s(f, &env->flags);
qemu_get_sbe32s(f, &env->error_code);
qemu_get_be32s(f, &env->pending_interrupts);
-#if !defined(CONFIG_USER_ONLY)
qemu_get_be32s(f, &env->irq_input_state);
for (i = 0; i < POWERPC_EXCP_NB; i++)
qemu_get_betls(f, &env->excp_vectors[i]);
@@ -170,7 +163,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_betls(f, &env->ivor_mask);
qemu_get_betls(f, &env->ivpr_mask);
qemu_get_betls(f, &env->hreset_vector);
-#endif
qemu_get_betls(f, &env->nip);
qemu_get_betls(f, &env->hflags);
qemu_get_betls(f, &env->hflags_nmsr);
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH 08/36] vmstate: machine.c is only compiled for !CONFIG_USER_ONLY
2012-03-19 22:57 ` [Qemu-devel] [PATCH 08/36] vmstate: machine.c is only compiled for !CONFIG_USER_ONLY Juan Quintela
@ 2012-03-21 18:09 ` Andreas Färber
2012-03-21 19:20 ` Peter Maydell
1 sibling, 0 replies; 60+ messages in thread
From: Andreas Färber @ 2012-03-21 18:09 UTC (permalink / raw)
To: Juan Quintela; +Cc: qemu-ppc@nongnu.org, qemu-devel, Alexander Graf
Confirmed, in Makefile.target machine.o is confined to ifdef CONFIG_SOFTMMU.
Am 19.03.2012 23:57, schrieb Juan Quintela:
> Signed-off-by: Juan Quintela <quintela@redhat.com>
I verified that the right #endifs were removed and compile-tested it.
Acked-by: Andreas Färber <afaerber@suse.de>
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH 08/36] vmstate: machine.c is only compiled for !CONFIG_USER_ONLY
2012-03-19 22:57 ` [Qemu-devel] [PATCH 08/36] vmstate: machine.c is only compiled for !CONFIG_USER_ONLY Juan Quintela
2012-03-21 18:09 ` Andreas Färber
@ 2012-03-21 19:20 ` Peter Maydell
1 sibling, 0 replies; 60+ messages in thread
From: Peter Maydell @ 2012-03-21 19:20 UTC (permalink / raw)
To: Juan Quintela; +Cc: qemu-devel
On 19 March 2012 22:57, Juan Quintela <quintela@redhat.com> wrote:
> Signed-off-by: Juan Quintela <quintela@redhat.com>
> ---
> target-ppc/machine.c | 8 --------
> 1 files changed, 0 insertions(+), 8 deletions(-)
Could we give this patch a more informative commit message,
please? In particular it doesn't actually say that this is
fixing a ppc-only problem. My suggestion:
===begin===
target-ppc/machine.c: Drop unnecessary ifdefs
machine.c is only compiled for softmmu targets, so checks for
!defined(CONFIG_USER_ONLY) are unnecessary and can be dropped.
===endit===
-- PMM
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH 09/36] vmstate: introduce float32 arrays
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (7 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 08/36] vmstate: machine.c is only compiled for !CONFIG_USER_ONLY Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-20 14:11 ` Peter Maydell
2012-03-19 22:57 ` [Qemu-devel] [PATCH 10/36] vmstate: introduce float64 arrays Juan Quintela
` (27 subsequent siblings)
36 siblings, 1 reply; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
savevm.c | 30 ++++++++++++++++++++++++++++++
vmstate.h | 5 +++++
2 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/savevm.c b/savevm.c
index 12fb209..09a2149 100644
--- a/savevm.c
+++ b/savevm.c
@@ -1082,6 +1082,36 @@ const VMStateInfo vmstate_info_uint16_equal = {
.put = put_uint16,
};
+/* 32 bit float */
+
+typedef union {
+ float32 f;
+ uint32_t i;
+} VMStateFloat32;
+
+static int get_float32(QEMUFile *f, void *pv, size_t size)
+{
+ float32 *v = pv;
+ VMStateFloat32 u;
+ qemu_get_be32s(f, &u.i);
+ *v = u.f;
+ return 0;
+}
+
+static void put_float32(QEMUFile *f, void *pv, size_t size)
+{
+ float32 *v = pv;
+ VMStateFloat32 u;
+ u.f = *v;
+ qemu_put_be32s(f, &u.i);
+}
+
+const VMStateInfo vmstate_info_float32 = {
+ .name = "float32",
+ .get = get_float32,
+ .put = put_float32,
+};
+
/* timers */
static int get_timer(QEMUFile *f, void *pv, size_t size)
diff --git a/vmstate.h b/vmstate.h
index 1a4a60b..135c5aa 100644
--- a/vmstate.h
+++ b/vmstate.h
@@ -130,6 +130,8 @@ extern const VMStateInfo vmstate_info_uint16;
extern const VMStateInfo vmstate_info_uint32;
extern const VMStateInfo vmstate_info_uint64;
+extern const VMStateInfo vmstate_info_float32;
+
extern const VMStateInfo vmstate_info_timer;
extern const VMStateInfo vmstate_info_buffer;
extern const VMStateInfo vmstate_info_unused_buffer;
@@ -559,6 +561,9 @@ extern const VMStateDescription vmstate_cpu;
#define VMSTATE_INT64_ARRAY(_f, _s, _n) \
VMSTATE_INT64_ARRAY_V(_f, _s, _n, 0)
+#define VMSTATE_FLOAT32_ARRAY(_f, _s, _n) \
+ VMSTATE_ARRAY(_f, _s, _n, 0, vmstate_info_float32, float32)
+
#define VMSTATE_BUFFER_V(_f, _s, _v) \
VMSTATE_STATIC_BUFFER(_f, _s, _v, NULL, 0, sizeof(typeof_field(_s, _f)))
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH 09/36] vmstate: introduce float32 arrays
2012-03-19 22:57 ` [Qemu-devel] [PATCH 09/36] vmstate: introduce float32 arrays Juan Quintela
@ 2012-03-20 14:11 ` Peter Maydell
2012-03-20 15:20 ` Juan Quintela
0 siblings, 1 reply; 60+ messages in thread
From: Peter Maydell @ 2012-03-20 14:11 UTC (permalink / raw)
To: Juan Quintela; +Cc: qemu-devel
On 19 March 2012 22:57, Juan Quintela <quintela@redhat.com> wrote:
> +/* 32 bit float */
> +
> +typedef union {
> + float32 f;
> + uint32_t i;
> +} VMStateFloat32;
> +
> +static int get_float32(QEMUFile *f, void *pv, size_t size)
> +{
> + float32 *v = pv;
> + VMStateFloat32 u;
> + qemu_get_be32s(f, &u.i);
> + *v = u.f;
> + return 0;
> +}
> +
> +static void put_float32(QEMUFile *f, void *pv, size_t size)
> +{
> + float32 *v = pv;
> + VMStateFloat32 u;
> + u.f = *v;
> + qemu_put_be32s(f, &u.i);
> +}
This conversion (float32<->uint32_t) should be done via
float32_val() and make_float32().
-- PMM
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH 09/36] vmstate: introduce float32 arrays
2012-03-20 14:11 ` Peter Maydell
@ 2012-03-20 15:20 ` Juan Quintela
0 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-20 15:20 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
Peter Maydell <peter.maydell@linaro.org> wrote:
> On 19 March 2012 22:57, Juan Quintela <quintela@redhat.com> wrote:
>> +/* 32 bit float */
>> +
>> +typedef union {
>> + float32 f;
>> + uint32_t i;
>> +} VMStateFloat32;
>> +
>> +static int get_float32(QEMUFile *f, void *pv, size_t size)
>> +{
>> + float32 *v = pv;
>> + VMStateFloat32 u;
>> + qemu_get_be32s(f, &u.i);
>> + *v = u.f;
>> + return 0;
>> +}
>> +
>> +static void put_float32(QEMUFile *f, void *pv, size_t size)
>> +{
>> + float32 *v = pv;
>> + VMStateFloat32 u;
>> + u.f = *v;
>> + qemu_put_be32s(f, &u.i);
>> +}
>
> This conversion (float32<->uint32_t) should be done via
> float32_val() and make_float32().
you are right. we can even simplify things with this. Thanks.
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH 10/36] vmstate: introduce float64 arrays
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (8 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 09/36] vmstate: introduce float32 arrays Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 11/36] vmstate: introduce CPU_DoubleU arrays Juan Quintela
` (26 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
savevm.c | 30 ++++++++++++++++++++++++++++++
vmstate.h | 4 ++++
2 files changed, 34 insertions(+), 0 deletions(-)
diff --git a/savevm.c b/savevm.c
index 09a2149..822f078 100644
--- a/savevm.c
+++ b/savevm.c
@@ -1112,6 +1112,36 @@ const VMStateInfo vmstate_info_float32 = {
.put = put_float32,
};
+/* 64 bit float */
+
+typedef union {
+ float64 d;
+ uint64_t l;
+} VMStateFloat64;
+
+static int get_float64(QEMUFile *f, void *pv, size_t size)
+{
+ float64 *v = pv;
+ VMStateFloat64 u;
+ qemu_get_be64s(f, &u.l);
+ *v = u.d;
+ return 0;
+}
+
+static void put_float64(QEMUFile *f, void *pv, size_t size)
+{
+ float64 *v = pv;
+ VMStateFloat64 u;
+ u.d = *v;
+ qemu_put_be64s(f, &u.l);
+}
+
+const VMStateInfo vmstate_info_float64 = {
+ .name = "float64",
+ .get = get_float64,
+ .put = put_float64,
+};
+
/* timers */
static int get_timer(QEMUFile *f, void *pv, size_t size)
diff --git a/vmstate.h b/vmstate.h
index 135c5aa..d3fb88c 100644
--- a/vmstate.h
+++ b/vmstate.h
@@ -131,6 +131,7 @@ extern const VMStateInfo vmstate_info_uint32;
extern const VMStateInfo vmstate_info_uint64;
extern const VMStateInfo vmstate_info_float32;
+extern const VMStateInfo vmstate_info_float64;
extern const VMStateInfo vmstate_info_timer;
extern const VMStateInfo vmstate_info_buffer;
@@ -564,6 +565,9 @@ extern const VMStateDescription vmstate_cpu;
#define VMSTATE_FLOAT32_ARRAY(_f, _s, _n) \
VMSTATE_ARRAY(_f, _s, _n, 0, vmstate_info_float32, float32)
+#define VMSTATE_FLOAT64_ARRAY(_f, _s, _n) \
+ VMSTATE_ARRAY(_f, _s, _n, 0, vmstate_info_float64, float64)
+
#define VMSTATE_BUFFER_V(_f, _s, _v) \
VMSTATE_STATIC_BUFFER(_f, _s, _v, NULL, 0, sizeof(typeof_field(_s, _f)))
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 11/36] vmstate: introduce CPU_DoubleU arrays
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (9 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 10/36] vmstate: introduce float64 arrays Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 12/36] vmstate: Introduce VMSTATE_STRUCT_VARRAY_INT32_TEST Juan Quintela
` (25 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
savevm.c | 24 ++++++++++++++++++++++++
vmstate.h | 4 ++++
2 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/savevm.c b/savevm.c
index 822f078..4c42076 100644
--- a/savevm.c
+++ b/savevm.c
@@ -1142,6 +1142,30 @@ const VMStateInfo vmstate_info_float64 = {
.put = put_float64,
};
+/* 64 bit CPUDouble */
+
+static int get_cpudouble(QEMUFile *f, void *pv, size_t size)
+{
+ CPU_DoubleU *v = pv;
+
+ qemu_get_be32s(f, &v->l.upper);
+ qemu_get_be32s(f, &v->l.lower);
+ return 0;
+}
+
+static void put_cpudouble(QEMUFile *f, void *pv, size_t size)
+{
+ CPU_DoubleU *v = pv;
+ qemu_put_be32s(f, &v->l.upper);
+ qemu_put_be32s(f, &v->l.lower);
+}
+
+const VMStateInfo vmstate_info_cpudouble = {
+ .name = "CPU_Double_U",
+ .get = get_cpudouble,
+ .put = put_cpudouble,
+};
+
/* timers */
static int get_timer(QEMUFile *f, void *pv, size_t size)
diff --git a/vmstate.h b/vmstate.h
index d3fb88c..5c56f25 100644
--- a/vmstate.h
+++ b/vmstate.h
@@ -132,6 +132,7 @@ extern const VMStateInfo vmstate_info_uint64;
extern const VMStateInfo vmstate_info_float32;
extern const VMStateInfo vmstate_info_float64;
+extern const VMStateInfo vmstate_info_cpudouble;
extern const VMStateInfo vmstate_info_timer;
extern const VMStateInfo vmstate_info_buffer;
@@ -568,6 +569,9 @@ extern const VMStateDescription vmstate_cpu;
#define VMSTATE_FLOAT64_ARRAY(_f, _s, _n) \
VMSTATE_ARRAY(_f, _s, _n, 0, vmstate_info_float64, float64)
+#define VMSTATE_CPUDOUBLE_ARRAY(_f, _s, _n) \
+ VMSTATE_ARRAY(_f, _s, _n, 0, vmstate_info_cpudouble, CPU_DoubleU)
+
#define VMSTATE_BUFFER_V(_f, _s, _v) \
VMSTATE_STATIC_BUFFER(_f, _s, _v, NULL, 0, sizeof(typeof_field(_s, _f)))
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 12/36] vmstate: Introduce VMSTATE_STRUCT_VARRAY_INT32_TEST
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (10 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 11/36] vmstate: introduce CPU_DoubleU arrays Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-21 20:16 ` Igor Mitsyanko
2012-03-19 22:57 ` [Qemu-devel] [PATCH 13/36] vmstate: port ppc cpu Juan Quintela
` (24 subsequent siblings)
36 siblings, 1 reply; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
We have an array of structs whose size is an int32 in the same struct that
depends on a test value to know if it is there or not.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
vmstate.h | 10 ++++++++++
1 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/vmstate.h b/vmstate.h
index 5c56f25..b8ac2d0 100644
--- a/vmstate.h
+++ b/vmstate.h
@@ -309,6 +309,16 @@ extern const VMStateDescription vmstate_cpu;
.offset = offsetof(_state, _field), \
}
+#define VMSTATE_STRUCT_VARRAY_INT32_TEST(_field, _state, _field_num, _test, _vmsd, _type) { \
+ .name = (stringify(_field)), \
+ .num_offset = vmstate_offset_value(_state, _field_num, int32_t), \
+ .vmsd = &(_vmsd), \
+ .field_exists = (_test), \
+ .size = sizeof(_type), \
+ .flags = VMS_STRUCT|VMS_VARRAY_INT32, \
+ .offset = offsetof(_state, _field), \
+}
+
#define VMSTATE_STRUCT_VARRAY_POINTER_INT32(_field, _state, _field_num, _vmsd, _type) { \
.name = (stringify(_field)), \
.version_id = 0, \
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH 12/36] vmstate: Introduce VMSTATE_STRUCT_VARRAY_INT32_TEST
2012-03-19 22:57 ` [Qemu-devel] [PATCH 12/36] vmstate: Introduce VMSTATE_STRUCT_VARRAY_INT32_TEST Juan Quintela
@ 2012-03-21 20:16 ` Igor Mitsyanko
0 siblings, 0 replies; 60+ messages in thread
From: Igor Mitsyanko @ 2012-03-21 20:16 UTC (permalink / raw)
To: Juan Quintela; +Cc: qemu-devel, d.solodkiy
On 20.03.2012 1:57 AM, Juan Quintela wrote:
> We have an array of structs whose size is an int32 in the same struct that
> depends on a test value to know if it is there or not.
>
> Signed-off-by: Juan Quintela<quintela@redhat.com>
> ---
> vmstate.h | 10 ++++++++++
> 1 files changed, 10 insertions(+), 0 deletions(-)
>
> diff --git a/vmstate.h b/vmstate.h
> index 5c56f25..b8ac2d0 100644
> --- a/vmstate.h
> +++ b/vmstate.h
> @@ -309,6 +309,16 @@ extern const VMStateDescription vmstate_cpu;
> .offset = offsetof(_state, _field), \
> }
>
> +#define VMSTATE_STRUCT_VARRAY_INT32_TEST(_field, _state, _field_num, _test, _vmsd, _type) { \
> + .name = (stringify(_field)), \
> + .num_offset = vmstate_offset_value(_state, _field_num, int32_t), \
> + .vmsd =&(_vmsd), \
> + .field_exists = (_test), \
> + .size = sizeof(_type), \
> + .flags = VMS_STRUCT|VMS_VARRAY_INT32, \
> + .offset = offsetof(_state, _field), \
> +}
> +
> #define VMSTATE_STRUCT_VARRAY_POINTER_INT32(_field, _state, _field_num, _vmsd, _type) { \
> .name = (stringify(_field)), \
> .version_id = 0, \
We already have VMSTATE_STRUCT_VARRAY_INT32, maybe for consistency with
other macro in vmstate.h this should look like this:
#define VMSTATE_STRUCT_VARRAY_INT32_TEST_V(_field, _state, _field_num,
_version, _test, _vmsd, _type) {
.name = (stringify(_field)),
.num_offset = vmstate_offset_value(_state, _field_num, int32_t),
.version_id = (_version),
.vmsd =&(_vmsd),
.field_exists = (_test),
.size = sizeof(_type),
.flags = VMS_STRUCT|VMS_VARRAY_INT32,
.offset = offsetof(_state, _field),
}
#define VMSTATE_STRUCT_VARRAY_INT32_TEST(_field, _state, _field_num,
_test, _vmsd, _type) \
VMSTATE_STRUCT_VARRAY_INT32_TEST_V(_field, _state, _field_num, 0, _test,
_vmsd, _type) {
#define VMSTATE_STRUCT_VARRAY_INT32(_field, _state, _field_num, _vmsd,
_type) \
VMSTATE_STRUCT_VARRAY_INT32_TEST_V(_field, _state, _field_num, 0, NULL,
_vmsd, _type) {
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH 13/36] vmstate: port ppc cpu
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (11 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 12/36] vmstate: Introduce VMSTATE_STRUCT_VARRAY_INT32_TEST Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-21 21:52 ` Michael Roth
2012-03-21 21:56 ` Peter Maydell
2012-03-19 22:57 ` [Qemu-devel] [PATCH 14/36] vmstate: introduce VMSTATE_VARRAY_MULTIPLY Juan Quintela
` (23 subsequent siblings)
36 siblings, 2 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Added sdr1_vmstate because storing the value requires calling ppc_store_sdr1().
The position when the function is called also changes (I think it is save).
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-ppc/cpu.h | 5 +-
target-ppc/machine.c | 245 ++++++++++++++++++--------------------------------
2 files changed, 90 insertions(+), 160 deletions(-)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index ca6f1cb..595ffb1 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1064,6 +1064,9 @@ struct CPUPPCState {
*/
uint8_t fit_period[4];
uint8_t wdt_period[4];
+
+ /* Fields needed as intermediate for vmstate */
+ target_ulong sdr1_vmstate;
};
#define SET_FIT_PERIOD(a_, b_, c_, d_) \
@@ -1219,8 +1222,6 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
#define cpu_signal_handler cpu_ppc_signal_handler
#define cpu_list ppc_cpu_list
-#define CPU_SAVE_VERSION 4
-
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _user
#define MMU_MODE1_SUFFIX _kernel
diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index d6c2ee4..ca60bc0 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -2,172 +2,101 @@
#include "hw/boards.h"
#include "kvm.h"
-void cpu_save(QEMUFile *f, void *opaque)
+static const VMStateDescription vmstate_tlb = {
+ .name = "tlb",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
+ VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
+ VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static bool is_tlb6(void *opaque, int version_id)
{
- CPUPPCState *env = (CPUPPCState *)opaque;
- unsigned int i, j;
+ CPUPPCState *env = opaque;
- for (i = 0; i < 32; i++)
- qemu_put_betls(f, &env->gpr[i]);
-#if !defined(TARGET_PPC64)
- for (i = 0; i < 32; i++)
- qemu_put_betls(f, &env->gprh[i]);
-#endif
- qemu_put_betls(f, &env->lr);
- qemu_put_betls(f, &env->ctr);
- for (i = 0; i < 8; i++)
- qemu_put_be32s(f, &env->crf[i]);
- qemu_put_betls(f, &env->xer);
- qemu_put_betls(f, &env->reserve_addr);
- qemu_put_betls(f, &env->msr);
- for (i = 0; i < 4; i++)
- qemu_put_betls(f, &env->tgpr[i]);
- for (i = 0; i < 32; i++) {
- union {
- float64 d;
- uint64_t l;
- } u;
- u.d = env->fpr[i];
- qemu_put_be64(f, u.l);
- }
- qemu_put_be32s(f, &env->fpscr);
- qemu_put_sbe32s(f, &env->access_type);
-#if defined(TARGET_PPC64)
- qemu_put_betls(f, &env->asr);
- qemu_put_sbe32s(f, &env->slb_nr);
-#endif
- qemu_put_betls(f, &env->spr[SPR_SDR1]);
- for (i = 0; i < 32; i++)
- qemu_put_betls(f, &env->sr[i]);
- for (i = 0; i < 2; i++)
- for (j = 0; j < 8; j++)
- qemu_put_betls(f, &env->DBAT[i][j]);
- for (i = 0; i < 2; i++)
- for (j = 0; j < 8; j++)
- qemu_put_betls(f, &env->IBAT[i][j]);
- qemu_put_sbe32s(f, &env->nb_tlb);
- qemu_put_sbe32s(f, &env->tlb_per_way);
- qemu_put_sbe32s(f, &env->nb_ways);
- qemu_put_sbe32s(f, &env->last_way);
- qemu_put_sbe32s(f, &env->id_tlbs);
- qemu_put_sbe32s(f, &env->nb_pids);
- if (env->tlb.tlb6) {
- // XXX assumes 6xx
- for (i = 0; i < env->nb_tlb; i++) {
- qemu_put_betls(f, &env->tlb.tlb6[i].pte0);
- qemu_put_betls(f, &env->tlb.tlb6[i].pte1);
- qemu_put_betls(f, &env->tlb.tlb6[i].EPN);
- }
- }
- for (i = 0; i < 4; i++)
- qemu_put_betls(f, &env->pb[i]);
- for (i = 0; i < 1024; i++)
- qemu_put_betls(f, &env->spr[i]);
- qemu_put_be32s(f, &env->vscr);
- qemu_put_be64s(f, &env->spe_acc);
- qemu_put_be32s(f, &env->spe_fscr);
- qemu_put_betls(f, &env->msr_mask);
- qemu_put_be32s(f, &env->flags);
- qemu_put_sbe32s(f, &env->error_code);
- qemu_put_be32s(f, &env->pending_interrupts);
- qemu_put_be32s(f, &env->irq_input_state);
- for (i = 0; i < POWERPC_EXCP_NB; i++)
- qemu_put_betls(f, &env->excp_vectors[i]);
- qemu_put_betls(f, &env->excp_prefix);
- qemu_put_betls(f, &env->hreset_excp_prefix);
- qemu_put_betls(f, &env->ivor_mask);
- qemu_put_betls(f, &env->ivpr_mask);
- qemu_put_betls(f, &env->hreset_vector);
- qemu_put_betls(f, &env->nip);
- qemu_put_betls(f, &env->hflags);
- qemu_put_betls(f, &env->hflags_nmsr);
- qemu_put_sbe32s(f, &env->mmu_idx);
- qemu_put_sbe32s(f, &env->power_mode);
+ return (env->tlb.tlb6 != NULL);
}
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
+static void cpu_pre_save(void *opaque)
{
- CPUPPCState *env = (CPUPPCState *)opaque;
- unsigned int i, j;
- target_ulong sdr1;
+ CPUPPCState *env = opaque;
+ env->sdr1_vmstate = env->spr[SPR_SDR1];
+}
- for (i = 0; i < 32; i++)
- qemu_get_betls(f, &env->gpr[i]);
+static int cpu_post_load(void *opaque, int version_id)
+{
+ CPUPPCState *env = opaque;
+ ppc_store_sdr1(env, env->sdr1_vmstate);
+ return 0;
+}
+
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .version_id = 4,
+ .minimum_version_id = 4,
+ .minimum_version_id_old = 4,
+ .pre_save = cpu_pre_save,
+ .post_load = cpu_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL_ARRAY(gpr, CPUPPCState, 32),
#if !defined(TARGET_PPC64)
- for (i = 0; i < 32; i++)
- qemu_get_betls(f, &env->gprh[i]);
+ VMSTATE_UINTTL_ARRAY(gprh, CPUPPCState, 32),
#endif
- qemu_get_betls(f, &env->lr);
- qemu_get_betls(f, &env->ctr);
- for (i = 0; i < 8; i++)
- qemu_get_be32s(f, &env->crf[i]);
- qemu_get_betls(f, &env->xer);
- qemu_get_betls(f, &env->reserve_addr);
- qemu_get_betls(f, &env->msr);
- for (i = 0; i < 4; i++)
- qemu_get_betls(f, &env->tgpr[i]);
- for (i = 0; i < 32; i++) {
- union {
- float64 d;
- uint64_t l;
- } u;
- u.l = qemu_get_be64(f);
- env->fpr[i] = u.d;
- }
- qemu_get_be32s(f, &env->fpscr);
- qemu_get_sbe32s(f, &env->access_type);
+ VMSTATE_UINTTL(lr, CPUPPCState),
+ VMSTATE_UINTTL(ctr, CPUPPCState),
+ VMSTATE_UINT32_ARRAY(crf, CPUPPCState, 8),
+ VMSTATE_UINTTL(xer, CPUPPCState),
+ VMSTATE_UINTTL(reserve_addr, CPUPPCState),
+ VMSTATE_UINTTL(msr, CPUPPCState),
+ VMSTATE_UINTTL_ARRAY(tgpr, CPUPPCState, 4),
+ VMSTATE_FLOAT64_ARRAY(fpr, CPUPPCState, 32),
+ VMSTATE_UINT32(fpscr, CPUPPCState),
+ VMSTATE_INT32(access_type, CPUPPCState),
#if defined(TARGET_PPC64)
- qemu_get_betls(f, &env->asr);
- qemu_get_sbe32s(f, &env->slb_nr);
+ VMSTATE_UINTTL(asr, CPUPPCState),
+ VMSTATE_INT32(slb_nr, CPUPPCState),
#endif
- qemu_get_betls(f, &sdr1);
- for (i = 0; i < 32; i++)
- qemu_get_betls(f, &env->sr[i]);
- for (i = 0; i < 2; i++)
- for (j = 0; j < 8; j++)
- qemu_get_betls(f, &env->DBAT[i][j]);
- for (i = 0; i < 2; i++)
- for (j = 0; j < 8; j++)
- qemu_get_betls(f, &env->IBAT[i][j]);
- qemu_get_sbe32s(f, &env->nb_tlb);
- qemu_get_sbe32s(f, &env->tlb_per_way);
- qemu_get_sbe32s(f, &env->nb_ways);
- qemu_get_sbe32s(f, &env->last_way);
- qemu_get_sbe32s(f, &env->id_tlbs);
- qemu_get_sbe32s(f, &env->nb_pids);
- if (env->tlb.tlb6) {
- // XXX assumes 6xx
- for (i = 0; i < env->nb_tlb; i++) {
- qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
- qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
- qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
- }
- }
- for (i = 0; i < 4; i++)
- qemu_get_betls(f, &env->pb[i]);
- for (i = 0; i < 1024; i++)
- qemu_get_betls(f, &env->spr[i]);
- ppc_store_sdr1(env, sdr1);
- qemu_get_be32s(f, &env->vscr);
- qemu_get_be64s(f, &env->spe_acc);
- qemu_get_be32s(f, &env->spe_fscr);
- qemu_get_betls(f, &env->msr_mask);
- qemu_get_be32s(f, &env->flags);
- qemu_get_sbe32s(f, &env->error_code);
- qemu_get_be32s(f, &env->pending_interrupts);
- qemu_get_be32s(f, &env->irq_input_state);
- for (i = 0; i < POWERPC_EXCP_NB; i++)
- qemu_get_betls(f, &env->excp_vectors[i]);
- qemu_get_betls(f, &env->excp_prefix);
- qemu_get_betls(f, &env->hreset_excp_prefix);
- qemu_get_betls(f, &env->ivor_mask);
- qemu_get_betls(f, &env->ivpr_mask);
- qemu_get_betls(f, &env->hreset_vector);
- qemu_get_betls(f, &env->nip);
- qemu_get_betls(f, &env->hflags);
- qemu_get_betls(f, &env->hflags_nmsr);
- qemu_get_sbe32s(f, &env->mmu_idx);
- qemu_get_sbe32s(f, &env->power_mode);
+ VMSTATE_UINTTL(spr[SPR_SDR1], CPUPPCState),
+ VMSTATE_UINTTL_ARRAY(sr, CPUPPCState, 32),
+ VMSTATE_UINTTL_ARRAY(DBAT[0], CPUPPCState, 8),
+ VMSTATE_UINTTL_ARRAY(DBAT[1], CPUPPCState, 8),
+ VMSTATE_UINTTL_ARRAY(IBAT[0], CPUPPCState, 8),
+ VMSTATE_UINTTL_ARRAY(IBAT[1], CPUPPCState, 8),
+ VMSTATE_INT32(nb_tlb, CPUPPCState),
+ VMSTATE_INT32(tlb_per_way, CPUPPCState),
+ VMSTATE_INT32(nb_ways, CPUPPCState),
+ VMSTATE_INT32(last_way, CPUPPCState),
+ VMSTATE_INT32(id_tlbs, CPUPPCState),
+ VMSTATE_INT32(nb_pids, CPUPPCState),
+ VMSTATE_STRUCT_VARRAY_INT32_TEST(tlb.tlb6, CPUPPCState, nb_tlb,
+ is_tlb6, vmstate_tlb, ppc6xx_tlb_t),
+ VMSTATE_UINTTL_ARRAY(pb, CPUPPCState, 4),
+ VMSTATE_UINTTL_ARRAY(spr, CPUPPCState, 1024),
+ VMSTATE_UINT32(vscr, CPUPPCState),
+ VMSTATE_UINT64(spe_acc, CPUPPCState),
+ VMSTATE_UINT32(spe_fscr, CPUPPCState),
+ VMSTATE_UINTTL(msr_mask, CPUPPCState),
+ VMSTATE_UINT32(flags, CPUPPCState),
+ VMSTATE_INT32(error_code, CPUPPCState),
+ VMSTATE_UINT32(pending_interrupts, CPUPPCState),
+ VMSTATE_UINT32(irq_input_state, CPUPPCState),
+ VMSTATE_UINTTL_ARRAY(excp_vectors, CPUPPCState, POWERPC_EXCP_NB),
+ VMSTATE_UINTTL(excp_prefix, CPUPPCState),
+ VMSTATE_UINTTL(hreset_excp_prefix, CPUPPCState),
+ VMSTATE_UINTTL(ivor_mask, CPUPPCState),
+ VMSTATE_UINTTL(ivpr_mask, CPUPPCState),
+ VMSTATE_UINTTL(hreset_vector, CPUPPCState),
+ VMSTATE_UINTTL(nip, CPUPPCState),
+ VMSTATE_UINTTL(hflags, CPUPPCState),
+ VMSTATE_UINTTL(hflags_nmsr, CPUPPCState),
+ VMSTATE_INT32(mmu_idx, CPUPPCState),
+ VMSTATE_INT32(power_mode, CPUPPCState),
+ VMSTATE_END_OF_LIST()
+ },
+};
- return 0;
-}
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH 13/36] vmstate: port ppc cpu
2012-03-19 22:57 ` [Qemu-devel] [PATCH 13/36] vmstate: port ppc cpu Juan Quintela
@ 2012-03-21 21:52 ` Michael Roth
2012-03-21 21:56 ` Peter Maydell
1 sibling, 0 replies; 60+ messages in thread
From: Michael Roth @ 2012-03-21 21:52 UTC (permalink / raw)
To: Juan Quintela; +Cc: qemu-devel
On Mon, Mar 19, 2012 at 11:57:41PM +0100, Juan Quintela wrote:
> Added sdr1_vmstate because storing the value requires calling ppc_store_sdr1().
> The position when the function is called also changes (I think it is save).
Doesn't side-effect any loads that originally occurred after it, and
same holds for possible call to tlb_flush(), so it seems to safe to move
it to cpu_post_load.
Reviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com>
>
> Signed-off-by: Juan Quintela <quintela@redhat.com>
> ---
> target-ppc/cpu.h | 5 +-
> target-ppc/machine.c | 245 ++++++++++++++++++--------------------------------
> 2 files changed, 90 insertions(+), 160 deletions(-)
>
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index ca6f1cb..595ffb1 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1064,6 +1064,9 @@ struct CPUPPCState {
> */
> uint8_t fit_period[4];
> uint8_t wdt_period[4];
> +
> + /* Fields needed as intermediate for vmstate */
> + target_ulong sdr1_vmstate;
> };
>
> #define SET_FIT_PERIOD(a_, b_, c_, d_) \
> @@ -1219,8 +1222,6 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
> #define cpu_signal_handler cpu_ppc_signal_handler
> #define cpu_list ppc_cpu_list
>
> -#define CPU_SAVE_VERSION 4
> -
> /* MMU modes definitions */
> #define MMU_MODE0_SUFFIX _user
> #define MMU_MODE1_SUFFIX _kernel
> diff --git a/target-ppc/machine.c b/target-ppc/machine.c
> index d6c2ee4..ca60bc0 100644
> --- a/target-ppc/machine.c
> +++ b/target-ppc/machine.c
> @@ -2,172 +2,101 @@
> #include "hw/boards.h"
> #include "kvm.h"
>
> -void cpu_save(QEMUFile *f, void *opaque)
> +static const VMStateDescription vmstate_tlb = {
> + .name = "tlb",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINTTL(pte0, ppc6xx_tlb_t),
> + VMSTATE_UINTTL(pte1, ppc6xx_tlb_t),
> + VMSTATE_UINTTL(EPN, ppc6xx_tlb_t),
> + VMSTATE_END_OF_LIST()
> + }
> +};
> +
> +static bool is_tlb6(void *opaque, int version_id)
> {
> - CPUPPCState *env = (CPUPPCState *)opaque;
> - unsigned int i, j;
> + CPUPPCState *env = opaque;
>
> - for (i = 0; i < 32; i++)
> - qemu_put_betls(f, &env->gpr[i]);
> -#if !defined(TARGET_PPC64)
> - for (i = 0; i < 32; i++)
> - qemu_put_betls(f, &env->gprh[i]);
> -#endif
> - qemu_put_betls(f, &env->lr);
> - qemu_put_betls(f, &env->ctr);
> - for (i = 0; i < 8; i++)
> - qemu_put_be32s(f, &env->crf[i]);
> - qemu_put_betls(f, &env->xer);
> - qemu_put_betls(f, &env->reserve_addr);
> - qemu_put_betls(f, &env->msr);
> - for (i = 0; i < 4; i++)
> - qemu_put_betls(f, &env->tgpr[i]);
> - for (i = 0; i < 32; i++) {
> - union {
> - float64 d;
> - uint64_t l;
> - } u;
> - u.d = env->fpr[i];
> - qemu_put_be64(f, u.l);
> - }
> - qemu_put_be32s(f, &env->fpscr);
> - qemu_put_sbe32s(f, &env->access_type);
> -#if defined(TARGET_PPC64)
> - qemu_put_betls(f, &env->asr);
> - qemu_put_sbe32s(f, &env->slb_nr);
> -#endif
> - qemu_put_betls(f, &env->spr[SPR_SDR1]);
> - for (i = 0; i < 32; i++)
> - qemu_put_betls(f, &env->sr[i]);
> - for (i = 0; i < 2; i++)
> - for (j = 0; j < 8; j++)
> - qemu_put_betls(f, &env->DBAT[i][j]);
> - for (i = 0; i < 2; i++)
> - for (j = 0; j < 8; j++)
> - qemu_put_betls(f, &env->IBAT[i][j]);
> - qemu_put_sbe32s(f, &env->nb_tlb);
> - qemu_put_sbe32s(f, &env->tlb_per_way);
> - qemu_put_sbe32s(f, &env->nb_ways);
> - qemu_put_sbe32s(f, &env->last_way);
> - qemu_put_sbe32s(f, &env->id_tlbs);
> - qemu_put_sbe32s(f, &env->nb_pids);
> - if (env->tlb.tlb6) {
> - // XXX assumes 6xx
> - for (i = 0; i < env->nb_tlb; i++) {
> - qemu_put_betls(f, &env->tlb.tlb6[i].pte0);
> - qemu_put_betls(f, &env->tlb.tlb6[i].pte1);
> - qemu_put_betls(f, &env->tlb.tlb6[i].EPN);
> - }
> - }
> - for (i = 0; i < 4; i++)
> - qemu_put_betls(f, &env->pb[i]);
> - for (i = 0; i < 1024; i++)
> - qemu_put_betls(f, &env->spr[i]);
> - qemu_put_be32s(f, &env->vscr);
> - qemu_put_be64s(f, &env->spe_acc);
> - qemu_put_be32s(f, &env->spe_fscr);
> - qemu_put_betls(f, &env->msr_mask);
> - qemu_put_be32s(f, &env->flags);
> - qemu_put_sbe32s(f, &env->error_code);
> - qemu_put_be32s(f, &env->pending_interrupts);
> - qemu_put_be32s(f, &env->irq_input_state);
> - for (i = 0; i < POWERPC_EXCP_NB; i++)
> - qemu_put_betls(f, &env->excp_vectors[i]);
> - qemu_put_betls(f, &env->excp_prefix);
> - qemu_put_betls(f, &env->hreset_excp_prefix);
> - qemu_put_betls(f, &env->ivor_mask);
> - qemu_put_betls(f, &env->ivpr_mask);
> - qemu_put_betls(f, &env->hreset_vector);
> - qemu_put_betls(f, &env->nip);
> - qemu_put_betls(f, &env->hflags);
> - qemu_put_betls(f, &env->hflags_nmsr);
> - qemu_put_sbe32s(f, &env->mmu_idx);
> - qemu_put_sbe32s(f, &env->power_mode);
> + return (env->tlb.tlb6 != NULL);
> }
>
> -int cpu_load(QEMUFile *f, void *opaque, int version_id)
> +static void cpu_pre_save(void *opaque)
> {
> - CPUPPCState *env = (CPUPPCState *)opaque;
> - unsigned int i, j;
> - target_ulong sdr1;
> + CPUPPCState *env = opaque;
> + env->sdr1_vmstate = env->spr[SPR_SDR1];
> +}
>
> - for (i = 0; i < 32; i++)
> - qemu_get_betls(f, &env->gpr[i]);
> +static int cpu_post_load(void *opaque, int version_id)
> +{
> + CPUPPCState *env = opaque;
> + ppc_store_sdr1(env, env->sdr1_vmstate);
> + return 0;
> +}
> +
> +const VMStateDescription vmstate_cpu = {
> + .name = "cpu",
> + .version_id = 4,
> + .minimum_version_id = 4,
> + .minimum_version_id_old = 4,
> + .pre_save = cpu_pre_save,
> + .post_load = cpu_post_load,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINTTL_ARRAY(gpr, CPUPPCState, 32),
> #if !defined(TARGET_PPC64)
> - for (i = 0; i < 32; i++)
> - qemu_get_betls(f, &env->gprh[i]);
> + VMSTATE_UINTTL_ARRAY(gprh, CPUPPCState, 32),
> #endif
> - qemu_get_betls(f, &env->lr);
> - qemu_get_betls(f, &env->ctr);
> - for (i = 0; i < 8; i++)
> - qemu_get_be32s(f, &env->crf[i]);
> - qemu_get_betls(f, &env->xer);
> - qemu_get_betls(f, &env->reserve_addr);
> - qemu_get_betls(f, &env->msr);
> - for (i = 0; i < 4; i++)
> - qemu_get_betls(f, &env->tgpr[i]);
> - for (i = 0; i < 32; i++) {
> - union {
> - float64 d;
> - uint64_t l;
> - } u;
> - u.l = qemu_get_be64(f);
> - env->fpr[i] = u.d;
> - }
> - qemu_get_be32s(f, &env->fpscr);
> - qemu_get_sbe32s(f, &env->access_type);
> + VMSTATE_UINTTL(lr, CPUPPCState),
> + VMSTATE_UINTTL(ctr, CPUPPCState),
> + VMSTATE_UINT32_ARRAY(crf, CPUPPCState, 8),
> + VMSTATE_UINTTL(xer, CPUPPCState),
> + VMSTATE_UINTTL(reserve_addr, CPUPPCState),
> + VMSTATE_UINTTL(msr, CPUPPCState),
> + VMSTATE_UINTTL_ARRAY(tgpr, CPUPPCState, 4),
> + VMSTATE_FLOAT64_ARRAY(fpr, CPUPPCState, 32),
> + VMSTATE_UINT32(fpscr, CPUPPCState),
> + VMSTATE_INT32(access_type, CPUPPCState),
> #if defined(TARGET_PPC64)
> - qemu_get_betls(f, &env->asr);
> - qemu_get_sbe32s(f, &env->slb_nr);
> + VMSTATE_UINTTL(asr, CPUPPCState),
> + VMSTATE_INT32(slb_nr, CPUPPCState),
> #endif
> - qemu_get_betls(f, &sdr1);
> - for (i = 0; i < 32; i++)
> - qemu_get_betls(f, &env->sr[i]);
> - for (i = 0; i < 2; i++)
> - for (j = 0; j < 8; j++)
> - qemu_get_betls(f, &env->DBAT[i][j]);
> - for (i = 0; i < 2; i++)
> - for (j = 0; j < 8; j++)
> - qemu_get_betls(f, &env->IBAT[i][j]);
> - qemu_get_sbe32s(f, &env->nb_tlb);
> - qemu_get_sbe32s(f, &env->tlb_per_way);
> - qemu_get_sbe32s(f, &env->nb_ways);
> - qemu_get_sbe32s(f, &env->last_way);
> - qemu_get_sbe32s(f, &env->id_tlbs);
> - qemu_get_sbe32s(f, &env->nb_pids);
> - if (env->tlb.tlb6) {
> - // XXX assumes 6xx
> - for (i = 0; i < env->nb_tlb; i++) {
> - qemu_get_betls(f, &env->tlb.tlb6[i].pte0);
> - qemu_get_betls(f, &env->tlb.tlb6[i].pte1);
> - qemu_get_betls(f, &env->tlb.tlb6[i].EPN);
> - }
> - }
> - for (i = 0; i < 4; i++)
> - qemu_get_betls(f, &env->pb[i]);
> - for (i = 0; i < 1024; i++)
> - qemu_get_betls(f, &env->spr[i]);
> - ppc_store_sdr1(env, sdr1);
> - qemu_get_be32s(f, &env->vscr);
> - qemu_get_be64s(f, &env->spe_acc);
> - qemu_get_be32s(f, &env->spe_fscr);
> - qemu_get_betls(f, &env->msr_mask);
> - qemu_get_be32s(f, &env->flags);
> - qemu_get_sbe32s(f, &env->error_code);
> - qemu_get_be32s(f, &env->pending_interrupts);
> - qemu_get_be32s(f, &env->irq_input_state);
> - for (i = 0; i < POWERPC_EXCP_NB; i++)
> - qemu_get_betls(f, &env->excp_vectors[i]);
> - qemu_get_betls(f, &env->excp_prefix);
> - qemu_get_betls(f, &env->hreset_excp_prefix);
> - qemu_get_betls(f, &env->ivor_mask);
> - qemu_get_betls(f, &env->ivpr_mask);
> - qemu_get_betls(f, &env->hreset_vector);
> - qemu_get_betls(f, &env->nip);
> - qemu_get_betls(f, &env->hflags);
> - qemu_get_betls(f, &env->hflags_nmsr);
> - qemu_get_sbe32s(f, &env->mmu_idx);
> - qemu_get_sbe32s(f, &env->power_mode);
> + VMSTATE_UINTTL(spr[SPR_SDR1], CPUPPCState),
> + VMSTATE_UINTTL_ARRAY(sr, CPUPPCState, 32),
> + VMSTATE_UINTTL_ARRAY(DBAT[0], CPUPPCState, 8),
> + VMSTATE_UINTTL_ARRAY(DBAT[1], CPUPPCState, 8),
> + VMSTATE_UINTTL_ARRAY(IBAT[0], CPUPPCState, 8),
> + VMSTATE_UINTTL_ARRAY(IBAT[1], CPUPPCState, 8),
> + VMSTATE_INT32(nb_tlb, CPUPPCState),
> + VMSTATE_INT32(tlb_per_way, CPUPPCState),
> + VMSTATE_INT32(nb_ways, CPUPPCState),
> + VMSTATE_INT32(last_way, CPUPPCState),
> + VMSTATE_INT32(id_tlbs, CPUPPCState),
> + VMSTATE_INT32(nb_pids, CPUPPCState),
> + VMSTATE_STRUCT_VARRAY_INT32_TEST(tlb.tlb6, CPUPPCState, nb_tlb,
> + is_tlb6, vmstate_tlb, ppc6xx_tlb_t),
> + VMSTATE_UINTTL_ARRAY(pb, CPUPPCState, 4),
> + VMSTATE_UINTTL_ARRAY(spr, CPUPPCState, 1024),
> + VMSTATE_UINT32(vscr, CPUPPCState),
> + VMSTATE_UINT64(spe_acc, CPUPPCState),
> + VMSTATE_UINT32(spe_fscr, CPUPPCState),
> + VMSTATE_UINTTL(msr_mask, CPUPPCState),
> + VMSTATE_UINT32(flags, CPUPPCState),
> + VMSTATE_INT32(error_code, CPUPPCState),
> + VMSTATE_UINT32(pending_interrupts, CPUPPCState),
> + VMSTATE_UINT32(irq_input_state, CPUPPCState),
> + VMSTATE_UINTTL_ARRAY(excp_vectors, CPUPPCState, POWERPC_EXCP_NB),
> + VMSTATE_UINTTL(excp_prefix, CPUPPCState),
> + VMSTATE_UINTTL(hreset_excp_prefix, CPUPPCState),
> + VMSTATE_UINTTL(ivor_mask, CPUPPCState),
> + VMSTATE_UINTTL(ivpr_mask, CPUPPCState),
> + VMSTATE_UINTTL(hreset_vector, CPUPPCState),
> + VMSTATE_UINTTL(nip, CPUPPCState),
> + VMSTATE_UINTTL(hflags, CPUPPCState),
> + VMSTATE_UINTTL(hflags_nmsr, CPUPPCState),
> + VMSTATE_INT32(mmu_idx, CPUPPCState),
> + VMSTATE_INT32(power_mode, CPUPPCState),
> + VMSTATE_END_OF_LIST()
> + },
> +};
>
> - return 0;
> -}
> --
> 1.7.7.6
>
>
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH 13/36] vmstate: port ppc cpu
2012-03-19 22:57 ` [Qemu-devel] [PATCH 13/36] vmstate: port ppc cpu Juan Quintela
2012-03-21 21:52 ` Michael Roth
@ 2012-03-21 21:56 ` Peter Maydell
1 sibling, 0 replies; 60+ messages in thread
From: Peter Maydell @ 2012-03-21 21:56 UTC (permalink / raw)
To: Juan Quintela; +Cc: qemu-devel
On 19 March 2012 22:57, Juan Quintela <quintela@redhat.com> wrote:
> + /* Fields needed as intermediate for vmstate */
> + target_ulong sdr1_vmstate;
Personally I prefer how alpha handles this for fpcr rather than
clogging up the CPUState with an intermediate field. (possibly
with some macro assist so it's a little less longwinded)
-- PMM
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH 14/36] vmstate: introduce VMSTATE_VARRAY_MULTIPLY
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (12 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 13/36] vmstate: port ppc cpu Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-21 20:54 ` Igor Mitsyanko
2012-03-19 22:57 ` [Qemu-devel] [PATCH 15/36] vmstate: define vmstate_info_uinttls Juan Quintela
` (22 subsequent siblings)
36 siblings, 1 reply; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
This allows to sent a partial array where the size is another
structure field multiplied by a constant.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
savevm.c | 6 ++++++
vmstate.h | 35 +++++++++++++++++++++++------------
2 files changed, 29 insertions(+), 12 deletions(-)
diff --git a/savevm.c b/savevm.c
index 4c42076..17927f1 100644
--- a/savevm.c
+++ b/savevm.c
@@ -1519,6 +1519,9 @@ int vmstate_load_state(QEMUFile *f, const VMStateDescription *vmsd,
} else if (field->flags & VMS_VARRAY_UINT8) {
n_elems = *(uint8_t *)(opaque+field->num_offset);
}
+ if (field->flags & VMS_MULTIPLY_ELEMENTS) {
+ n_elems *= field->num;
+ }
if (field->flags & VMS_POINTER) {
base_addr = *(void **)base_addr + field->start;
}
@@ -1583,6 +1586,9 @@ void vmstate_save_state(QEMUFile *f, const VMStateDescription *vmsd,
} else if (field->flags & VMS_VARRAY_UINT8) {
n_elems = *(uint8_t *)(opaque+field->num_offset);
}
+ if (field->flags & VMS_MULTIPLY_ELEMENTS) {
+ n_elems *= field->num;
+ }
if (field->flags & VMS_POINTER) {
base_addr = *(void **)base_addr + field->start;
}
diff --git a/vmstate.h b/vmstate.h
index b8ac2d0..b0225e9 100644
--- a/vmstate.h
+++ b/vmstate.h
@@ -64,18 +64,19 @@ struct VMStateInfo {
};
enum VMStateFlags {
- VMS_SINGLE = 0x001,
- VMS_POINTER = 0x002,
- VMS_ARRAY = 0x004,
- VMS_STRUCT = 0x008,
- VMS_VARRAY_INT32 = 0x010, /* Array with size in int32_t field*/
- VMS_BUFFER = 0x020, /* static sized buffer */
- VMS_ARRAY_OF_POINTER = 0x040,
- VMS_VARRAY_UINT16 = 0x080, /* Array with size in uint16_t field */
- VMS_VBUFFER = 0x100, /* Buffer with size in int32_t field */
- VMS_MULTIPLY = 0x200, /* multiply "size" field by field_size */
- VMS_VARRAY_UINT8 = 0x400, /* Array with size in uint8_t field*/
- VMS_VARRAY_UINT32 = 0x800, /* Array with size in uint32_t field*/
+ VMS_SINGLE = 0x001,
+ VMS_POINTER = 0x002,
+ VMS_ARRAY = 0x004,
+ VMS_STRUCT = 0x008,
+ VMS_VARRAY_INT32 = 0x010, /* Array with size in int32_t field*/
+ VMS_BUFFER = 0x020, /* static sized buffer */
+ VMS_ARRAY_OF_POINTER = 0x040,
+ VMS_VARRAY_UINT16 = 0x080, /* Array with size in uint16_t field */
+ VMS_VBUFFER = 0x100, /* Buffer with size in int32_t field */
+ VMS_MULTIPLY = 0x200, /* multiply "size" field by field_size */
+ VMS_VARRAY_UINT8 = 0x400, /* Array with size in uint8_t field*/
+ VMS_VARRAY_UINT32 = 0x800, /* Array with size in uint32_t field*/
+ VMS_MULTIPLY_ELEMENTS = 0x1000, /* multiply "size" field by field_size */
};
typedef struct {
@@ -200,6 +201,16 @@ extern const VMStateDescription vmstate_cpu;
.offset = vmstate_offset_array(_state, _field, _type, _num), \
}
+#define VMSTATE_VARRAY_MULTIPLY(_field, _state, _field_num, _multiply, _info, _type) { \
+ .name = (stringify(_field)), \
+ .num_offset = vmstate_offset_value(_state, _field_num, uint32_t),\
+ .num = (_multiply), \
+ .info = &(_info), \
+ .size = sizeof(_type), \
+ .flags = VMS_VARRAY_UINT32|VMS_MULTIPLY_ELEMENTS, \
+ .offset = offsetof(_state, _field), \
+}
+
#define VMSTATE_ARRAY_TEST(_field, _state, _num, _test, _info, _type) {\
.name = (stringify(_field)), \
.field_exists = (_test), \
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH 14/36] vmstate: introduce VMSTATE_VARRAY_MULTIPLY
2012-03-19 22:57 ` [Qemu-devel] [PATCH 14/36] vmstate: introduce VMSTATE_VARRAY_MULTIPLY Juan Quintela
@ 2012-03-21 20:54 ` Igor Mitsyanko
0 siblings, 0 replies; 60+ messages in thread
From: Igor Mitsyanko @ 2012-03-21 20:54 UTC (permalink / raw)
To: Juan Quintela; +Cc: qemu-devel, d.solodkiy
On 20.03.2012 1:57 AM, Juan Quintela wrote:
> This allows to sent a partial array where the size is another
> structure field multiplied by a constant.
>
> Signed-off-by: Juan Quintela<quintela@redhat.com>
> ---
> savevm.c | 6 ++++++
> vmstate.h | 35 +++++++++++++++++++++++------------
> 2 files changed, 29 insertions(+), 12 deletions(-)
>
> diff --git a/savevm.c b/savevm.c
> index 4c42076..17927f1 100644
> --- a/savevm.c
> +++ b/savevm.c
> @@ -1519,6 +1519,9 @@ int vmstate_load_state(QEMUFile *f, const VMStateDescription *vmsd,
> } else if (field->flags& VMS_VARRAY_UINT8) {
> n_elems = *(uint8_t *)(opaque+field->num_offset);
> }
> + if (field->flags& VMS_MULTIPLY_ELEMENTS) {
> + n_elems *= field->num;
> + }
> if (field->flags& VMS_POINTER) {
> base_addr = *(void **)base_addr + field->start;
> }
> @@ -1583,6 +1586,9 @@ void vmstate_save_state(QEMUFile *f, const VMStateDescription *vmsd,
> } else if (field->flags& VMS_VARRAY_UINT8) {
> n_elems = *(uint8_t *)(opaque+field->num_offset);
> }
> + if (field->flags& VMS_MULTIPLY_ELEMENTS) {
> + n_elems *= field->num;
> + }
> if (field->flags& VMS_POINTER) {
> base_addr = *(void **)base_addr + field->start;
> }
> diff --git a/vmstate.h b/vmstate.h
> index b8ac2d0..b0225e9 100644
> --- a/vmstate.h
> +++ b/vmstate.h
> @@ -64,18 +64,19 @@ struct VMStateInfo {
> };
>
> enum VMStateFlags {
> - VMS_SINGLE = 0x001,
> - VMS_POINTER = 0x002,
> - VMS_ARRAY = 0x004,
> - VMS_STRUCT = 0x008,
> - VMS_VARRAY_INT32 = 0x010, /* Array with size in int32_t field*/
> - VMS_BUFFER = 0x020, /* static sized buffer */
> - VMS_ARRAY_OF_POINTER = 0x040,
> - VMS_VARRAY_UINT16 = 0x080, /* Array with size in uint16_t field */
> - VMS_VBUFFER = 0x100, /* Buffer with size in int32_t field */
> - VMS_MULTIPLY = 0x200, /* multiply "size" field by field_size */
> - VMS_VARRAY_UINT8 = 0x400, /* Array with size in uint8_t field*/
> - VMS_VARRAY_UINT32 = 0x800, /* Array with size in uint32_t field*/
> + VMS_SINGLE = 0x001,
> + VMS_POINTER = 0x002,
> + VMS_ARRAY = 0x004,
> + VMS_STRUCT = 0x008,
> + VMS_VARRAY_INT32 = 0x010, /* Array with size in int32_t field*/
> + VMS_BUFFER = 0x020, /* static sized buffer */
> + VMS_ARRAY_OF_POINTER = 0x040,
> + VMS_VARRAY_UINT16 = 0x080, /* Array with size in uint16_t field */
> + VMS_VBUFFER = 0x100, /* Buffer with size in int32_t field */
> + VMS_MULTIPLY = 0x200, /* multiply "size" field by field_size */
> + VMS_VARRAY_UINT8 = 0x400, /* Array with size in uint8_t field*/
> + VMS_VARRAY_UINT32 = 0x800, /* Array with size in uint32_t field*/
> + VMS_MULTIPLY_ELEMENTS = 0x1000, /* multiply "size" field by field_size */
> };
>
You forgot to change a comment here.
> typedef struct {
> @@ -200,6 +201,16 @@ extern const VMStateDescription vmstate_cpu;
> .offset = vmstate_offset_array(_state, _field, _type, _num), \
> }
>
> +#define VMSTATE_VARRAY_MULTIPLY(_field, _state, _field_num, _multiply, _info, _type) { \
> + .name = (stringify(_field)), \
> + .num_offset = vmstate_offset_value(_state, _field_num, uint32_t),\
> + .num = (_multiply), \
> + .info =&(_info), \
> + .size = sizeof(_type), \
> + .flags = VMS_VARRAY_UINT32|VMS_MULTIPLY_ELEMENTS, \
> + .offset = offsetof(_state, _field), \
> +}
> +
Why just "VMSTATE_VARRAY_MULTIPLY" when you use VMS_VARRAY_UINT32 flag?
Probably should be VMSTATE_VARRAY_UINT32_MULTIPLY
> #define VMSTATE_ARRAY_TEST(_field, _state, _num, _test, _info, _type) {\
> .name = (stringify(_field)), \
> .field_exists = (_test), \
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH 15/36] vmstate: define vmstate_info_uinttls
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (13 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 14/36] vmstate: introduce VMSTATE_VARRAY_MULTIPLY Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 16/36] vmstate: port sparc cpu Juan Quintela
` (21 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
We are going to define arrays of this type, so we need the integer type.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/hw.h | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/hw.h b/hw/hw.h
index e5cb9bf..9dbac88 100644
--- a/hw/hw.h
+++ b/hw/hw.h
@@ -52,11 +52,13 @@ int qemu_boot_set(const char *boot_devices);
VMSTATE_UINT64_V(_f, _s, _v)
#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_UINT64_ARRAY_V(_f, _s, _n, _v)
+#define vmstate_info_uinttls vmstate_info_uint64
#else
#define VMSTATE_UINTTL_V(_f, _s, _v) \
VMSTATE_UINT32_V(_f, _s, _v)
#define VMSTATE_UINTTL_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_UINT32_ARRAY_V(_f, _s, _n, _v)
+#define vmstate_info_uinttls vmstate_info_uint32
#endif
#define VMSTATE_UINTTL(_f, _s) \
VMSTATE_UINTTL_V(_f, _s, 0)
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 16/36] vmstate: port sparc cpu
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (14 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 15/36] vmstate: define vmstate_info_uinttls Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-21 22:46 ` Michael Roth
2012-03-19 22:57 ` [Qemu-devel] [PATCH 17/36] vmstate: make incompatible change for sparc Juan Quintela
` (20 subsequent siblings)
36 siblings, 1 reply; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/sun4u.c | 20 --
target-sparc/cpu.h | 9 +-
target-sparc/machine.c | 474 ++++++++++++++++++++++++++++--------------------
3 files changed, 283 insertions(+), 220 deletions(-)
diff --git a/hw/sun4u.c b/hw/sun4u.c
index 237e20c..c36861c 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -330,26 +330,6 @@ typedef struct ResetData {
uint64_t prom_addr;
} ResetData;
-void cpu_put_timer(QEMUFile *f, CPUTimer *s)
-{
- qemu_put_be32s(f, &s->frequency);
- qemu_put_be32s(f, &s->disabled);
- qemu_put_be64s(f, &s->disabled_mask);
- qemu_put_sbe64s(f, &s->clock_offset);
-
- qemu_put_timer(f, s->qtimer);
-}
-
-void cpu_get_timer(QEMUFile *f, CPUTimer *s)
-{
- qemu_get_be32s(f, &s->frequency);
- qemu_get_be32s(f, &s->disabled);
- qemu_get_be64s(f, &s->disabled_mask);
- qemu_get_sbe64s(f, &s->clock_offset);
-
- qemu_get_timer(f, s->qtimer);
-}
-
static CPUTimer* cpu_timer_create(const char* name, CPUSPARCState *env,
QEMUBHFunc *cb, uint32_t frequency,
uint64_t disabled_mask)
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 1025752..ba9b833 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -374,10 +374,6 @@ struct CPUTimer
typedef struct CPUTimer CPUTimer;
-struct QEMUFile;
-void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
-void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
-
typedef struct CPUSPARCState CPUSPARCState;
struct CPUSPARCState {
@@ -509,6 +505,9 @@ struct CPUSPARCState {
/* Leon3 cache control */
uint32_t cache_control;
+
+ /* Fields needed as intermediate for vmstate */
+ uint32_t psr_vmstate;
};
#ifndef NO_CPU_IO_DEFS
@@ -596,8 +595,6 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
#define cpu_signal_handler cpu_sparc_signal_handler
#define cpu_list sparc_cpu_list
-#define CPU_SAVE_VERSION 7
-
/* MMU modes definitions */
#if defined (TARGET_SPARC64)
#define MMU_USER_IDX 0
diff --git a/target-sparc/machine.c b/target-sparc/machine.c
index eb4d87f..801ec55 100644
--- a/target-sparc/machine.c
+++ b/target-sparc/machine.c
@@ -4,214 +4,300 @@
#include "cpu.h"
-void cpu_save(QEMUFile *f, void *opaque)
-{
- CPUSPARCState *env = opaque;
- int i;
- uint32_t tmp;
-
- // if env->cwp == env->nwindows - 1, this will set the ins of the last
- // window as the outs of the first window
- cpu_set_cwp(env, env->cwp);
+static const VMStateDescription vmstate_cpu_timer = {
+ .name = "cpu_timer",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(frequency, CPUTimer),
+ VMSTATE_UINT32(disabled, CPUTimer),
+ VMSTATE_UINT64(disabled_mask, CPUTimer),
+ VMSTATE_INT64(clock_offset, CPUTimer),
+ VMSTATE_TIMER(qtimer, CPUTimer),
+ VMSTATE_END_OF_LIST()
+ }
+};
- for(i = 0; i < 8; i++)
- qemu_put_betls(f, &env->gregs[i]);
- qemu_put_be32s(f, &env->nwindows);
- for(i = 0; i < env->nwindows * 16; i++)
- qemu_put_betls(f, &env->regbase[i]);
+#define VMSTATE_CPU_TIMER(_f, _s) \
+ VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_timer, CPUTimer *)
- /* FPU */
- for (i = 0; i < TARGET_DPREGS; i++) {
- qemu_put_be32(f, env->fpr[i].l.upper);
- qemu_put_be32(f, env->fpr[i].l.lower);
+#if defined(TARGET_SPARC64)
+static const VMStateDescription vmstate_trap_state = {
+ .name = "trap_state",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(tpc, trap_state),
+ VMSTATE_UINT64(tnpc, trap_state),
+ VMSTATE_UINT64(tstate, trap_state),
+ VMSTATE_UINT32(tt, trap_state),
+ VMSTATE_END_OF_LIST()
}
+};
- qemu_put_betls(f, &env->pc);
- qemu_put_betls(f, &env->npc);
- qemu_put_betls(f, &env->y);
- tmp = cpu_get_psr(env);
- qemu_put_be32(f, tmp);
- qemu_put_betls(f, &env->fsr);
- qemu_put_betls(f, &env->tbr);
- tmp = env->interrupt_index;
- qemu_put_be32(f, tmp);
- qemu_put_be32s(f, &env->pil_in);
-#ifndef TARGET_SPARC64
- qemu_put_be32s(f, &env->wim);
- /* MMU */
- for (i = 0; i < 32; i++)
- qemu_put_be32s(f, &env->mmuregs[i]);
- for (i = 0; i < 4; i++) {
- qemu_put_be64s(f, &env->mxccdata[i]);
- }
- for (i = 0; i < 8; i++) {
- qemu_put_be64s(f, &env->mxccregs[i]);
- }
- qemu_put_be32s(f, &env->mmubpctrv);
- qemu_put_be32s(f, &env->mmubpctrc);
- qemu_put_be32s(f, &env->mmubpctrs);
- qemu_put_be64s(f, &env->mmubpaction);
- for (i = 0; i < 4; i++) {
- qemu_put_be64s(f, &env->mmubpregs[i]);
+static const VMStateDescription vmstate_tlb_entry = {
+ .name = "tlb_entry",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(tag, SparcTLBEntry),
+ VMSTATE_UINT64(tte, SparcTLBEntry),
+ VMSTATE_END_OF_LIST()
}
-#else
- qemu_put_be64s(f, &env->lsu);
- for (i = 0; i < 16; i++) {
- qemu_put_be64s(f, &env->immuregs[i]);
- qemu_put_be64s(f, &env->dmmuregs[i]);
- }
- for (i = 0; i < 64; i++) {
- qemu_put_be64s(f, &env->itlb[i].tag);
- qemu_put_be64s(f, &env->itlb[i].tte);
- qemu_put_be64s(f, &env->dtlb[i].tag);
- qemu_put_be64s(f, &env->dtlb[i].tte);
- }
- qemu_put_be32s(f, &env->mmu_version);
- for (i = 0; i < MAXTL_MAX; i++) {
- qemu_put_be64s(f, &env->ts[i].tpc);
- qemu_put_be64s(f, &env->ts[i].tnpc);
- qemu_put_be64s(f, &env->ts[i].tstate);
- qemu_put_be32s(f, &env->ts[i].tt);
- }
- qemu_put_be32s(f, &env->xcc);
- qemu_put_be32s(f, &env->asi);
- qemu_put_be32s(f, &env->pstate);
- qemu_put_be32s(f, &env->tl);
- qemu_put_be32s(f, &env->cansave);
- qemu_put_be32s(f, &env->canrestore);
- qemu_put_be32s(f, &env->otherwin);
- qemu_put_be32s(f, &env->wstate);
- qemu_put_be32s(f, &env->cleanwin);
- for (i = 0; i < 8; i++)
- qemu_put_be64s(f, &env->agregs[i]);
- for (i = 0; i < 8; i++)
- qemu_put_be64s(f, &env->bgregs[i]);
- for (i = 0; i < 8; i++)
- qemu_put_be64s(f, &env->igregs[i]);
- for (i = 0; i < 8; i++)
- qemu_put_be64s(f, &env->mgregs[i]);
- qemu_put_be64s(f, &env->fprs);
- qemu_put_be64s(f, &env->tick_cmpr);
- qemu_put_be64s(f, &env->stick_cmpr);
- cpu_put_timer(f, env->tick);
- cpu_put_timer(f, env->stick);
- qemu_put_be64s(f, &env->gsr);
- qemu_put_be32s(f, &env->gl);
- qemu_put_be64s(f, &env->hpstate);
- for (i = 0; i < MAXTL_MAX; i++)
- qemu_put_be64s(f, &env->htstate[i]);
- qemu_put_be64s(f, &env->hintp);
- qemu_put_be64s(f, &env->htba);
- qemu_put_be64s(f, &env->hver);
- qemu_put_be64s(f, &env->hstick_cmpr);
- qemu_put_be64s(f, &env->ssr);
- cpu_put_timer(f, env->hstick);
+};
#endif
-}
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
+static void cpu_pre_save(void *opaque)
{
CPUSPARCState *env = opaque;
- int i;
- uint32_t tmp;
- if (version_id < 6)
- return -EINVAL;
- for(i = 0; i < 8; i++)
- qemu_get_betls(f, &env->gregs[i]);
- qemu_get_be32s(f, &env->nwindows);
- for(i = 0; i < env->nwindows * 16; i++)
- qemu_get_betls(f, &env->regbase[i]);
+ /* if env->cwp == env->nwindows - 1, this will set the ins of the last
+ * window as the outs of the first window
+ */
+ cpu_set_cwp(env, env->cwp);
+ env->psr_vmstate = cpu_get_psr(env);
+}
- /* FPU */
- for (i = 0; i < TARGET_DPREGS; i++) {
- env->fpr[i].l.upper = qemu_get_be32(f);
- env->fpr[i].l.lower = qemu_get_be32(f);
- }
+static int cpu_post_load(void *opaque, int version_id)
+{
+ CPUSPARCState *env = opaque;
- qemu_get_betls(f, &env->pc);
- qemu_get_betls(f, &env->npc);
- qemu_get_betls(f, &env->y);
- tmp = qemu_get_be32(f);
env->cwp = 0; /* needed to ensure that the wrapping registers are
correctly updated */
- cpu_put_psr(env, tmp);
- qemu_get_betls(f, &env->fsr);
- qemu_get_betls(f, &env->tbr);
- tmp = qemu_get_be32(f);
- env->interrupt_index = tmp;
- qemu_get_be32s(f, &env->pil_in);
-#ifndef TARGET_SPARC64
- qemu_get_be32s(f, &env->wim);
- /* MMU */
- for (i = 0; i < 32; i++)
- qemu_get_be32s(f, &env->mmuregs[i]);
- for (i = 0; i < 4; i++) {
- qemu_get_be64s(f, &env->mxccdata[i]);
- }
- for (i = 0; i < 8; i++) {
- qemu_get_be64s(f, &env->mxccregs[i]);
- }
- qemu_get_be32s(f, &env->mmubpctrv);
- qemu_get_be32s(f, &env->mmubpctrc);
- qemu_get_be32s(f, &env->mmubpctrs);
- qemu_get_be64s(f, &env->mmubpaction);
- for (i = 0; i < 4; i++) {
- qemu_get_be64s(f, &env->mmubpregs[i]);
- }
-#else
- qemu_get_be64s(f, &env->lsu);
- for (i = 0; i < 16; i++) {
- qemu_get_be64s(f, &env->immuregs[i]);
- qemu_get_be64s(f, &env->dmmuregs[i]);
- }
- for (i = 0; i < 64; i++) {
- qemu_get_be64s(f, &env->itlb[i].tag);
- qemu_get_be64s(f, &env->itlb[i].tte);
- qemu_get_be64s(f, &env->dtlb[i].tag);
- qemu_get_be64s(f, &env->dtlb[i].tte);
- }
- qemu_get_be32s(f, &env->mmu_version);
- for (i = 0; i < MAXTL_MAX; i++) {
- qemu_get_be64s(f, &env->ts[i].tpc);
- qemu_get_be64s(f, &env->ts[i].tnpc);
- qemu_get_be64s(f, &env->ts[i].tstate);
- qemu_get_be32s(f, &env->ts[i].tt);
- }
- qemu_get_be32s(f, &env->xcc);
- qemu_get_be32s(f, &env->asi);
- qemu_get_be32s(f, &env->pstate);
- qemu_get_be32s(f, &env->tl);
- qemu_get_be32s(f, &env->cansave);
- qemu_get_be32s(f, &env->canrestore);
- qemu_get_be32s(f, &env->otherwin);
- qemu_get_be32s(f, &env->wstate);
- qemu_get_be32s(f, &env->cleanwin);
- for (i = 0; i < 8; i++)
- qemu_get_be64s(f, &env->agregs[i]);
- for (i = 0; i < 8; i++)
- qemu_get_be64s(f, &env->bgregs[i]);
- for (i = 0; i < 8; i++)
- qemu_get_be64s(f, &env->igregs[i]);
- for (i = 0; i < 8; i++)
- qemu_get_be64s(f, &env->mgregs[i]);
- qemu_get_be64s(f, &env->fprs);
- qemu_get_be64s(f, &env->tick_cmpr);
- qemu_get_be64s(f, &env->stick_cmpr);
- cpu_get_timer(f, env->tick);
- cpu_get_timer(f, env->stick);
- qemu_get_be64s(f, &env->gsr);
- qemu_get_be32s(f, &env->gl);
- qemu_get_be64s(f, &env->hpstate);
- for (i = 0; i < MAXTL_MAX; i++)
- qemu_get_be64s(f, &env->htstate[i]);
- qemu_get_be64s(f, &env->hintp);
- qemu_get_be64s(f, &env->htba);
- qemu_get_be64s(f, &env->hver);
- qemu_get_be64s(f, &env->hstick_cmpr);
- qemu_get_be64s(f, &env->ssr);
- cpu_get_timer(f, env->hstick);
-#endif
+ cpu_put_psr(env, env->psr_vmstate);
tlb_flush(env, 1);
return 0;
}
+
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .version_id = 7,
+ .minimum_version_id = 7,
+ .minimum_version_id_old = 7,
+ .pre_save = cpu_pre_save,
+ .post_load = cpu_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL_ARRAY(gregs, CPUSPARCState, 8),
+ VMSTATE_UINT32(nwindows, CPUSPARCState),
+ VMSTATE_VARRAY_MULTIPLY(regbase, CPUSPARCState, nwindows, 16,
+ vmstate_info_uinttls, target_ulong),
+ VMSTATE_CPUDOUBLE_ARRAY(fpr, CPUSPARCState, TARGET_DPREGS),
+ VMSTATE_UINTTL(pc, CPUSPARCState),
+ VMSTATE_UINTTL(npc, CPUSPARCState),
+ VMSTATE_UINTTL(y, CPUSPARCState),
+ VMSTATE_UINT32(psr_vmstate, CPUSPARCState),
+ VMSTATE_UINTTL(fsr, CPUSPARCState),
+ VMSTATE_UINTTL(tbr, CPUSPARCState),
+ VMSTATE_INT32(interrupt_index, CPUSPARCState),
+ VMSTATE_UINT32(pil_in, CPUSPARCState),
+#ifndef TARGET_SPARC64
+ /* MMU */
+ VMSTATE_UINT32(wim, CPUSPARCState),
+ VMSTATE_UINT32_ARRAY(mmuregs, CPUSPARCState, 32),
+ VMSTATE_UINT64_ARRAY(mxccdata, CPUSPARCState, 4),
+ VMSTATE_UINT64_ARRAY(mxccregs, CPUSPARCState, 8),
+ VMSTATE_UINT32(mmubpctrv, CPUSPARCState),
+ VMSTATE_UINT32(mmubpctrc, CPUSPARCState),
+ VMSTATE_UINT32(mmubpctrs, CPUSPARCState),
+ VMSTATE_UINT64(mmubpaction, CPUSPARCState),
+ VMSTATE_UINT64_ARRAY(mmubpregs, CPUSPARCState, 4),
+#else
+ VMSTATE_UINT64(lsu, CPUSPARCState),
+ VMSTATE_UINT64(immuregs[0], CPUSPARCState),
+ VMSTATE_UINT64(dmmuregs[0], CPUSPARCState),
+ VMSTATE_UINT64(immuregs[1], CPUSPARCState),
+ VMSTATE_UINT64(dmmuregs[1], CPUSPARCState),
+ VMSTATE_UINT64(immuregs[2], CPUSPARCState),
+ VMSTATE_UINT64(dmmuregs[2], CPUSPARCState),
+ VMSTATE_UINT64(immuregs[3], CPUSPARCState),
+ VMSTATE_UINT64(dmmuregs[3], CPUSPARCState),
+ VMSTATE_UINT64(immuregs[4], CPUSPARCState),
+ VMSTATE_UINT64(dmmuregs[4], CPUSPARCState),
+ VMSTATE_UINT64(immuregs[5], CPUSPARCState),
+ VMSTATE_UINT64(dmmuregs[5], CPUSPARCState),
+ VMSTATE_UINT64(immuregs[6], CPUSPARCState),
+ VMSTATE_UINT64(dmmuregs[6], CPUSPARCState),
+ VMSTATE_UINT64(immuregs[7], CPUSPARCState),
+ VMSTATE_UINT64(dmmuregs[7], CPUSPARCState),
+ VMSTATE_UINT64(immuregs[8], CPUSPARCState),
+ VMSTATE_UINT64(dmmuregs[8], CPUSPARCState),
+ VMSTATE_UINT64(immuregs[9], CPUSPARCState),
+ VMSTATE_UINT64(dmmuregs[9], CPUSPARCState),
+ VMSTATE_UINT64(immuregs[10], CPUSPARCState),
+ VMSTATE_UINT64(dmmuregs[10], CPUSPARCState),
+ VMSTATE_UINT64(immuregs[11], CPUSPARCState),
+ VMSTATE_UINT64(dmmuregs[11], CPUSPARCState),
+ VMSTATE_UINT64(immuregs[12], CPUSPARCState),
+ VMSTATE_UINT64(dmmuregs[12], CPUSPARCState),
+ VMSTATE_UINT64(immuregs[13], CPUSPARCState),
+ VMSTATE_UINT64(dmmuregs[13], CPUSPARCState),
+ VMSTATE_UINT64(immuregs[14], CPUSPARCState),
+ VMSTATE_UINT64(dmmuregs[14], CPUSPARCState),
+ VMSTATE_UINT64(immuregs[15], CPUSPARCState),
+ VMSTATE_UINT64(dmmuregs[15], CPUSPARCState),
+ VMSTATE_STRUCT(itlb[0], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[0], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[1], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[1], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[2], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[2], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[3], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[3], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[4], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[4], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[5], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[5], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[6], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[6], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[7], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[7], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[8], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[8], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[9], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[9], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[10], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[10], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[11], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[11], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[12], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[12], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[13], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[13], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[14], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[14], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[15], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[15], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[16], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[16], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[17], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[17], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[18], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[18], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[19], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[19], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[20], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[20], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[21], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[21], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[22], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[22], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[23], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[23], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[24], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[24], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[25], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[25], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[26], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[26], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[27], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[27], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[28], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[28], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[29], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[29], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[30], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[30], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[31], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[31], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[32], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[32], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[33], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[33], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[34], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[34], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[35], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[35], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[36], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[36], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[37], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[37], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[38], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[38], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[39], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[39], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[40], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[40], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[41], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[41], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[42], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[42], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[43], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[43], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[44], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[44], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[45], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[45], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[46], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[46], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[47], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[47], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[48], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[48], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[49], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[49], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[50], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[50], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[51], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[51], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[52], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[52], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[53], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[53], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[54], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[54], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[55], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[55], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[56], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[56], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[57], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[57], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[58], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[58], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[59], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[59], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[60], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[60], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[61], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[61], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[62], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[62], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(itlb[63], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT(dtlb[63], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_UINT32(mmu_version, CPUSPARCState),
+ VMSTATE_STRUCT_ARRAY(ts, CPUSPARCState, MAXTL_MAX, 0,
+ vmstate_trap_state, trap_state),
+ VMSTATE_UINT32(xcc, CPUSPARCState),
+ VMSTATE_UINT32(asi, CPUSPARCState),
+ VMSTATE_UINT32(pstate, CPUSPARCState),
+ VMSTATE_UINT32(tl, CPUSPARCState),
+ VMSTATE_UINT32(cansave, CPUSPARCState),
+ VMSTATE_UINT32(canrestore, CPUSPARCState),
+ VMSTATE_UINT32(otherwin, CPUSPARCState),
+ VMSTATE_UINT32(wstate, CPUSPARCState),
+ VMSTATE_UINT32(cleanwin, CPUSPARCState),
+ VMSTATE_UINT64_ARRAY(agregs, CPUSPARCState, 8),
+ VMSTATE_UINT64_ARRAY(bgregs, CPUSPARCState, 8),
+ VMSTATE_UINT64_ARRAY(igregs, CPUSPARCState, 8),
+ VMSTATE_UINT64_ARRAY(mgregs, CPUSPARCState, 8),
+ VMSTATE_UINT64(fprs, CPUSPARCState),
+ VMSTATE_UINT64(tick_cmpr, CPUSPARCState),
+ VMSTATE_UINT64(stick_cmpr, CPUSPARCState),
+ VMSTATE_CPU_TIMER(tick, CPUSPARCState),
+ VMSTATE_CPU_TIMER(stick, CPUSPARCState),
+ VMSTATE_UINT64(gsr, CPUSPARCState),
+ VMSTATE_UINT32(gl, CPUSPARCState),
+ VMSTATE_UINT64(hpstate, CPUSPARCState),
+ VMSTATE_UINT64_ARRAY(htstate, CPUSPARCState, MAXTL_MAX),
+ VMSTATE_UINT64(hintp, CPUSPARCState),
+ VMSTATE_UINT64(htba, CPUSPARCState),
+ VMSTATE_UINT64(hver, CPUSPARCState),
+ VMSTATE_UINT64(hstick_cmpr, CPUSPARCState),
+ VMSTATE_UINT64(ssr, CPUSPARCState),
+ VMSTATE_CPU_TIMER(hstick, CPUSPARCState),
+#endif
+ VMSTATE_END_OF_LIST()
+ },
+};
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH 16/36] vmstate: port sparc cpu
2012-03-19 22:57 ` [Qemu-devel] [PATCH 16/36] vmstate: port sparc cpu Juan Quintela
@ 2012-03-21 22:46 ` Michael Roth
2012-03-24 12:32 ` Blue Swirl
0 siblings, 1 reply; 60+ messages in thread
From: Michael Roth @ 2012-03-21 22:46 UTC (permalink / raw)
To: Juan Quintela; +Cc: qemu-devel
On Mon, Mar 19, 2012 at 11:57:44PM +0100, Juan Quintela wrote:
> Signed-off-by: Juan Quintela <quintela@redhat.com>
> ---
> hw/sun4u.c | 20 --
> target-sparc/cpu.h | 9 +-
> target-sparc/machine.c | 474 ++++++++++++++++++++++++++++--------------------
> 3 files changed, 283 insertions(+), 220 deletions(-)
>
> diff --git a/hw/sun4u.c b/hw/sun4u.c
> index 237e20c..c36861c 100644
> --- a/hw/sun4u.c
> +++ b/hw/sun4u.c
> @@ -330,26 +330,6 @@ typedef struct ResetData {
> uint64_t prom_addr;
> } ResetData;
>
> -void cpu_put_timer(QEMUFile *f, CPUTimer *s)
> -{
> - qemu_put_be32s(f, &s->frequency);
> - qemu_put_be32s(f, &s->disabled);
> - qemu_put_be64s(f, &s->disabled_mask);
> - qemu_put_sbe64s(f, &s->clock_offset);
> -
> - qemu_put_timer(f, s->qtimer);
> -}
> -
> -void cpu_get_timer(QEMUFile *f, CPUTimer *s)
> -{
> - qemu_get_be32s(f, &s->frequency);
> - qemu_get_be32s(f, &s->disabled);
> - qemu_get_be64s(f, &s->disabled_mask);
> - qemu_get_sbe64s(f, &s->clock_offset);
> -
> - qemu_get_timer(f, s->qtimer);
> -}
> -
> static CPUTimer* cpu_timer_create(const char* name, CPUSPARCState *env,
> QEMUBHFunc *cb, uint32_t frequency,
> uint64_t disabled_mask)
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index 1025752..ba9b833 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -374,10 +374,6 @@ struct CPUTimer
>
> typedef struct CPUTimer CPUTimer;
>
> -struct QEMUFile;
> -void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
> -void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
> -
> typedef struct CPUSPARCState CPUSPARCState;
>
> struct CPUSPARCState {
> @@ -509,6 +505,9 @@ struct CPUSPARCState {
>
> /* Leon3 cache control */
> uint32_t cache_control;
> +
> + /* Fields needed as intermediate for vmstate */
> + uint32_t psr_vmstate;
> };
>
> #ifndef NO_CPU_IO_DEFS
> @@ -596,8 +595,6 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
> #define cpu_signal_handler cpu_sparc_signal_handler
> #define cpu_list sparc_cpu_list
>
> -#define CPU_SAVE_VERSION 7
> -
> /* MMU modes definitions */
> #if defined (TARGET_SPARC64)
> #define MMU_USER_IDX 0
> diff --git a/target-sparc/machine.c b/target-sparc/machine.c
> index eb4d87f..801ec55 100644
> --- a/target-sparc/machine.c
> +++ b/target-sparc/machine.c
> @@ -4,214 +4,300 @@
>
> #include "cpu.h"
>
> -void cpu_save(QEMUFile *f, void *opaque)
> -{
> - CPUSPARCState *env = opaque;
> - int i;
> - uint32_t tmp;
> -
> - // if env->cwp == env->nwindows - 1, this will set the ins of the last
> - // window as the outs of the first window
> - cpu_set_cwp(env, env->cwp);
> +static const VMStateDescription vmstate_cpu_timer = {
> + .name = "cpu_timer",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT32(frequency, CPUTimer),
> + VMSTATE_UINT32(disabled, CPUTimer),
> + VMSTATE_UINT64(disabled_mask, CPUTimer),
> + VMSTATE_INT64(clock_offset, CPUTimer),
> + VMSTATE_TIMER(qtimer, CPUTimer),
> + VMSTATE_END_OF_LIST()
> + }
> +};
>
> - for(i = 0; i < 8; i++)
> - qemu_put_betls(f, &env->gregs[i]);
> - qemu_put_be32s(f, &env->nwindows);
> - for(i = 0; i < env->nwindows * 16; i++)
> - qemu_put_betls(f, &env->regbase[i]);
> +#define VMSTATE_CPU_TIMER(_f, _s) \
> + VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_timer, CPUTimer *)
>
> - /* FPU */
> - for (i = 0; i < TARGET_DPREGS; i++) {
> - qemu_put_be32(f, env->fpr[i].l.upper);
> - qemu_put_be32(f, env->fpr[i].l.lower);
> +#if defined(TARGET_SPARC64)
> +static const VMStateDescription vmstate_trap_state = {
> + .name = "trap_state",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT64(tpc, trap_state),
> + VMSTATE_UINT64(tnpc, trap_state),
> + VMSTATE_UINT64(tstate, trap_state),
> + VMSTATE_UINT32(tt, trap_state),
> + VMSTATE_END_OF_LIST()
> }
> +};
>
> - qemu_put_betls(f, &env->pc);
> - qemu_put_betls(f, &env->npc);
> - qemu_put_betls(f, &env->y);
> - tmp = cpu_get_psr(env);
> - qemu_put_be32(f, tmp);
> - qemu_put_betls(f, &env->fsr);
> - qemu_put_betls(f, &env->tbr);
> - tmp = env->interrupt_index;
> - qemu_put_be32(f, tmp);
> - qemu_put_be32s(f, &env->pil_in);
> -#ifndef TARGET_SPARC64
> - qemu_put_be32s(f, &env->wim);
> - /* MMU */
> - for (i = 0; i < 32; i++)
> - qemu_put_be32s(f, &env->mmuregs[i]);
> - for (i = 0; i < 4; i++) {
> - qemu_put_be64s(f, &env->mxccdata[i]);
> - }
> - for (i = 0; i < 8; i++) {
> - qemu_put_be64s(f, &env->mxccregs[i]);
> - }
> - qemu_put_be32s(f, &env->mmubpctrv);
> - qemu_put_be32s(f, &env->mmubpctrc);
> - qemu_put_be32s(f, &env->mmubpctrs);
> - qemu_put_be64s(f, &env->mmubpaction);
> - for (i = 0; i < 4; i++) {
> - qemu_put_be64s(f, &env->mmubpregs[i]);
> +static const VMStateDescription vmstate_tlb_entry = {
> + .name = "tlb_entry",
> + .version_id = 1,
> + .minimum_version_id = 1,
> + .minimum_version_id_old = 1,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINT64(tag, SparcTLBEntry),
> + VMSTATE_UINT64(tte, SparcTLBEntry),
> + VMSTATE_END_OF_LIST()
> }
> -#else
> - qemu_put_be64s(f, &env->lsu);
> - for (i = 0; i < 16; i++) {
> - qemu_put_be64s(f, &env->immuregs[i]);
> - qemu_put_be64s(f, &env->dmmuregs[i]);
> - }
> - for (i = 0; i < 64; i++) {
> - qemu_put_be64s(f, &env->itlb[i].tag);
> - qemu_put_be64s(f, &env->itlb[i].tte);
> - qemu_put_be64s(f, &env->dtlb[i].tag);
> - qemu_put_be64s(f, &env->dtlb[i].tte);
> - }
> - qemu_put_be32s(f, &env->mmu_version);
> - for (i = 0; i < MAXTL_MAX; i++) {
> - qemu_put_be64s(f, &env->ts[i].tpc);
> - qemu_put_be64s(f, &env->ts[i].tnpc);
> - qemu_put_be64s(f, &env->ts[i].tstate);
> - qemu_put_be32s(f, &env->ts[i].tt);
> - }
> - qemu_put_be32s(f, &env->xcc);
> - qemu_put_be32s(f, &env->asi);
> - qemu_put_be32s(f, &env->pstate);
> - qemu_put_be32s(f, &env->tl);
> - qemu_put_be32s(f, &env->cansave);
> - qemu_put_be32s(f, &env->canrestore);
> - qemu_put_be32s(f, &env->otherwin);
> - qemu_put_be32s(f, &env->wstate);
> - qemu_put_be32s(f, &env->cleanwin);
> - for (i = 0; i < 8; i++)
> - qemu_put_be64s(f, &env->agregs[i]);
> - for (i = 0; i < 8; i++)
> - qemu_put_be64s(f, &env->bgregs[i]);
> - for (i = 0; i < 8; i++)
> - qemu_put_be64s(f, &env->igregs[i]);
> - for (i = 0; i < 8; i++)
> - qemu_put_be64s(f, &env->mgregs[i]);
> - qemu_put_be64s(f, &env->fprs);
> - qemu_put_be64s(f, &env->tick_cmpr);
> - qemu_put_be64s(f, &env->stick_cmpr);
> - cpu_put_timer(f, env->tick);
> - cpu_put_timer(f, env->stick);
> - qemu_put_be64s(f, &env->gsr);
> - qemu_put_be32s(f, &env->gl);
> - qemu_put_be64s(f, &env->hpstate);
> - for (i = 0; i < MAXTL_MAX; i++)
> - qemu_put_be64s(f, &env->htstate[i]);
> - qemu_put_be64s(f, &env->hintp);
> - qemu_put_be64s(f, &env->htba);
> - qemu_put_be64s(f, &env->hver);
> - qemu_put_be64s(f, &env->hstick_cmpr);
> - qemu_put_be64s(f, &env->ssr);
> - cpu_put_timer(f, env->hstick);
> +};
> #endif
> -}
>
> -int cpu_load(QEMUFile *f, void *opaque, int version_id)
> +static void cpu_pre_save(void *opaque)
> {
> CPUSPARCState *env = opaque;
> - int i;
> - uint32_t tmp;
>
> - if (version_id < 6)
> - return -EINVAL;
> - for(i = 0; i < 8; i++)
> - qemu_get_betls(f, &env->gregs[i]);
> - qemu_get_be32s(f, &env->nwindows);
> - for(i = 0; i < env->nwindows * 16; i++)
> - qemu_get_betls(f, &env->regbase[i]);
> + /* if env->cwp == env->nwindows - 1, this will set the ins of the last
> + * window as the outs of the first window
> + */
> + cpu_set_cwp(env, env->cwp);
> + env->psr_vmstate = cpu_get_psr(env);
> +}
>
> - /* FPU */
> - for (i = 0; i < TARGET_DPREGS; i++) {
> - env->fpr[i].l.upper = qemu_get_be32(f);
> - env->fpr[i].l.lower = qemu_get_be32(f);
> - }
> +static int cpu_post_load(void *opaque, int version_id)
> +{
> + CPUSPARCState *env = opaque;
>
> - qemu_get_betls(f, &env->pc);
> - qemu_get_betls(f, &env->npc);
> - qemu_get_betls(f, &env->y);
> - tmp = qemu_get_be32(f);
> env->cwp = 0; /* needed to ensure that the wrapping registers are
> correctly updated */
> - cpu_put_psr(env, tmp);
> - qemu_get_betls(f, &env->fsr);
> - qemu_get_betls(f, &env->tbr);
> - tmp = qemu_get_be32(f);
> - env->interrupt_index = tmp;
> - qemu_get_be32s(f, &env->pil_in);
> -#ifndef TARGET_SPARC64
> - qemu_get_be32s(f, &env->wim);
> - /* MMU */
> - for (i = 0; i < 32; i++)
> - qemu_get_be32s(f, &env->mmuregs[i]);
> - for (i = 0; i < 4; i++) {
> - qemu_get_be64s(f, &env->mxccdata[i]);
> - }
> - for (i = 0; i < 8; i++) {
> - qemu_get_be64s(f, &env->mxccregs[i]);
> - }
> - qemu_get_be32s(f, &env->mmubpctrv);
> - qemu_get_be32s(f, &env->mmubpctrc);
> - qemu_get_be32s(f, &env->mmubpctrs);
> - qemu_get_be64s(f, &env->mmubpaction);
> - for (i = 0; i < 4; i++) {
> - qemu_get_be64s(f, &env->mmubpregs[i]);
> - }
> -#else
> - qemu_get_be64s(f, &env->lsu);
> - for (i = 0; i < 16; i++) {
> - qemu_get_be64s(f, &env->immuregs[i]);
> - qemu_get_be64s(f, &env->dmmuregs[i]);
> - }
> - for (i = 0; i < 64; i++) {
> - qemu_get_be64s(f, &env->itlb[i].tag);
> - qemu_get_be64s(f, &env->itlb[i].tte);
> - qemu_get_be64s(f, &env->dtlb[i].tag);
> - qemu_get_be64s(f, &env->dtlb[i].tte);
> - }
> - qemu_get_be32s(f, &env->mmu_version);
> - for (i = 0; i < MAXTL_MAX; i++) {
> - qemu_get_be64s(f, &env->ts[i].tpc);
> - qemu_get_be64s(f, &env->ts[i].tnpc);
> - qemu_get_be64s(f, &env->ts[i].tstate);
> - qemu_get_be32s(f, &env->ts[i].tt);
> - }
> - qemu_get_be32s(f, &env->xcc);
> - qemu_get_be32s(f, &env->asi);
> - qemu_get_be32s(f, &env->pstate);
> - qemu_get_be32s(f, &env->tl);
> - qemu_get_be32s(f, &env->cansave);
> - qemu_get_be32s(f, &env->canrestore);
> - qemu_get_be32s(f, &env->otherwin);
> - qemu_get_be32s(f, &env->wstate);
> - qemu_get_be32s(f, &env->cleanwin);
> - for (i = 0; i < 8; i++)
> - qemu_get_be64s(f, &env->agregs[i]);
> - for (i = 0; i < 8; i++)
> - qemu_get_be64s(f, &env->bgregs[i]);
> - for (i = 0; i < 8; i++)
> - qemu_get_be64s(f, &env->igregs[i]);
> - for (i = 0; i < 8; i++)
> - qemu_get_be64s(f, &env->mgregs[i]);
> - qemu_get_be64s(f, &env->fprs);
> - qemu_get_be64s(f, &env->tick_cmpr);
> - qemu_get_be64s(f, &env->stick_cmpr);
> - cpu_get_timer(f, env->tick);
> - cpu_get_timer(f, env->stick);
> - qemu_get_be64s(f, &env->gsr);
> - qemu_get_be32s(f, &env->gl);
> - qemu_get_be64s(f, &env->hpstate);
> - for (i = 0; i < MAXTL_MAX; i++)
> - qemu_get_be64s(f, &env->htstate[i]);
> - qemu_get_be64s(f, &env->hintp);
> - qemu_get_be64s(f, &env->htba);
> - qemu_get_be64s(f, &env->hver);
> - qemu_get_be64s(f, &env->hstick_cmpr);
> - qemu_get_be64s(f, &env->ssr);
> - cpu_get_timer(f, env->hstick);
> -#endif
> + cpu_put_psr(env, env->psr_vmstate);
This changes the behavior a bit: cpu_put_psr()->cpu_check_irqs() can
modify env->interrupt_index. I suspect the original behavior was unintended
though, doing this post-load seems to make a lot more sense.
> tlb_flush(env, 1);
> return 0;
> }
> +
> +const VMStateDescription vmstate_cpu = {
> + .name = "cpu",
> + .version_id = 7,
> + .minimum_version_id = 7,
> + .minimum_version_id_old = 7,
> + .pre_save = cpu_pre_save,
> + .post_load = cpu_post_load,
> + .fields = (VMStateField[]) {
> + VMSTATE_UINTTL_ARRAY(gregs, CPUSPARCState, 8),
> + VMSTATE_UINT32(nwindows, CPUSPARCState),
> + VMSTATE_VARRAY_MULTIPLY(regbase, CPUSPARCState, nwindows, 16,
> + vmstate_info_uinttls, target_ulong),
> + VMSTATE_CPUDOUBLE_ARRAY(fpr, CPUSPARCState, TARGET_DPREGS),
> + VMSTATE_UINTTL(pc, CPUSPARCState),
> + VMSTATE_UINTTL(npc, CPUSPARCState),
> + VMSTATE_UINTTL(y, CPUSPARCState),
> + VMSTATE_UINT32(psr_vmstate, CPUSPARCState),
> + VMSTATE_UINTTL(fsr, CPUSPARCState),
> + VMSTATE_UINTTL(tbr, CPUSPARCState),
> + VMSTATE_INT32(interrupt_index, CPUSPARCState),
> + VMSTATE_UINT32(pil_in, CPUSPARCState),
> +#ifndef TARGET_SPARC64
> + /* MMU */
> + VMSTATE_UINT32(wim, CPUSPARCState),
> + VMSTATE_UINT32_ARRAY(mmuregs, CPUSPARCState, 32),
> + VMSTATE_UINT64_ARRAY(mxccdata, CPUSPARCState, 4),
> + VMSTATE_UINT64_ARRAY(mxccregs, CPUSPARCState, 8),
> + VMSTATE_UINT32(mmubpctrv, CPUSPARCState),
> + VMSTATE_UINT32(mmubpctrc, CPUSPARCState),
> + VMSTATE_UINT32(mmubpctrs, CPUSPARCState),
> + VMSTATE_UINT64(mmubpaction, CPUSPARCState),
> + VMSTATE_UINT64_ARRAY(mmubpregs, CPUSPARCState, 4),
> +#else
> + VMSTATE_UINT64(lsu, CPUSPARCState),
> + VMSTATE_UINT64(immuregs[0], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[0], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[1], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[1], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[2], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[2], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[3], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[3], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[4], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[4], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[5], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[5], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[6], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[6], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[7], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[7], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[8], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[8], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[9], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[9], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[10], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[10], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[11], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[11], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[12], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[12], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[13], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[13], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[14], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[14], CPUSPARCState),
> + VMSTATE_UINT64(immuregs[15], CPUSPARCState),
> + VMSTATE_UINT64(dmmuregs[15], CPUSPARCState),
> + VMSTATE_STRUCT(itlb[0], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[0], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[1], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[1], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[2], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[2], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[3], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[3], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[4], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[4], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[5], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[5], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[6], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[6], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[7], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[7], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[8], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[8], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[9], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[9], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[10], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[10], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[11], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[11], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[12], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[12], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[13], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[13], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[14], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[14], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[15], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[15], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[16], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[16], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[17], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[17], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[18], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[18], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[19], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[19], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[20], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[20], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[21], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[21], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[22], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[22], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[23], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[23], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[24], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[24], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[25], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[25], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[26], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[26], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[27], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[27], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[28], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[28], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[29], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[29], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[30], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[30], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[31], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[31], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[32], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[32], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[33], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[33], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[34], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[34], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[35], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[35], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[36], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[36], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[37], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[37], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[38], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[38], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[39], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[39], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[40], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[40], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[41], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[41], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[42], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[42], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[43], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[43], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[44], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[44], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[45], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[45], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[46], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[46], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[47], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[47], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[48], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[48], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[49], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[49], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[50], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[50], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[51], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[51], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[52], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[52], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[53], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[53], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[54], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[54], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[55], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[55], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[56], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[56], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[57], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[57], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[58], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[58], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[59], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[59], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[60], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[60], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[61], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[61], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[62], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[62], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(itlb[63], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_STRUCT(dtlb[63], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
> + VMSTATE_UINT32(mmu_version, CPUSPARCState),
> + VMSTATE_STRUCT_ARRAY(ts, CPUSPARCState, MAXTL_MAX, 0,
> + vmstate_trap_state, trap_state),
> + VMSTATE_UINT32(xcc, CPUSPARCState),
> + VMSTATE_UINT32(asi, CPUSPARCState),
> + VMSTATE_UINT32(pstate, CPUSPARCState),
> + VMSTATE_UINT32(tl, CPUSPARCState),
> + VMSTATE_UINT32(cansave, CPUSPARCState),
> + VMSTATE_UINT32(canrestore, CPUSPARCState),
> + VMSTATE_UINT32(otherwin, CPUSPARCState),
> + VMSTATE_UINT32(wstate, CPUSPARCState),
> + VMSTATE_UINT32(cleanwin, CPUSPARCState),
> + VMSTATE_UINT64_ARRAY(agregs, CPUSPARCState, 8),
> + VMSTATE_UINT64_ARRAY(bgregs, CPUSPARCState, 8),
> + VMSTATE_UINT64_ARRAY(igregs, CPUSPARCState, 8),
> + VMSTATE_UINT64_ARRAY(mgregs, CPUSPARCState, 8),
> + VMSTATE_UINT64(fprs, CPUSPARCState),
> + VMSTATE_UINT64(tick_cmpr, CPUSPARCState),
> + VMSTATE_UINT64(stick_cmpr, CPUSPARCState),
> + VMSTATE_CPU_TIMER(tick, CPUSPARCState),
> + VMSTATE_CPU_TIMER(stick, CPUSPARCState),
> + VMSTATE_UINT64(gsr, CPUSPARCState),
> + VMSTATE_UINT32(gl, CPUSPARCState),
> + VMSTATE_UINT64(hpstate, CPUSPARCState),
> + VMSTATE_UINT64_ARRAY(htstate, CPUSPARCState, MAXTL_MAX),
> + VMSTATE_UINT64(hintp, CPUSPARCState),
> + VMSTATE_UINT64(htba, CPUSPARCState),
> + VMSTATE_UINT64(hver, CPUSPARCState),
> + VMSTATE_UINT64(hstick_cmpr, CPUSPARCState),
> + VMSTATE_UINT64(ssr, CPUSPARCState),
> + VMSTATE_CPU_TIMER(hstick, CPUSPARCState),
> +#endif
> + VMSTATE_END_OF_LIST()
> + },
> +};
> --
> 1.7.7.6
>
>
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH 16/36] vmstate: port sparc cpu
2012-03-21 22:46 ` Michael Roth
@ 2012-03-24 12:32 ` Blue Swirl
0 siblings, 0 replies; 60+ messages in thread
From: Blue Swirl @ 2012-03-24 12:32 UTC (permalink / raw)
To: Michael Roth; +Cc: qemu-devel, Juan Quintela
On Wed, Mar 21, 2012 at 22:46, Michael Roth <mdroth@linux.vnet.ibm.com> wrote:
> On Mon, Mar 19, 2012 at 11:57:44PM +0100, Juan Quintela wrote:
>> Signed-off-by: Juan Quintela <quintela@redhat.com>
>> ---
>> hw/sun4u.c | 20 --
>> target-sparc/cpu.h | 9 +-
>> target-sparc/machine.c | 474 ++++++++++++++++++++++++++++--------------------
>> 3 files changed, 283 insertions(+), 220 deletions(-)
>>
>> diff --git a/hw/sun4u.c b/hw/sun4u.c
>> index 237e20c..c36861c 100644
>> --- a/hw/sun4u.c
>> +++ b/hw/sun4u.c
>> @@ -330,26 +330,6 @@ typedef struct ResetData {
>> uint64_t prom_addr;
>> } ResetData;
>>
>> -void cpu_put_timer(QEMUFile *f, CPUTimer *s)
>> -{
>> - qemu_put_be32s(f, &s->frequency);
>> - qemu_put_be32s(f, &s->disabled);
>> - qemu_put_be64s(f, &s->disabled_mask);
>> - qemu_put_sbe64s(f, &s->clock_offset);
>> -
>> - qemu_put_timer(f, s->qtimer);
>> -}
>> -
>> -void cpu_get_timer(QEMUFile *f, CPUTimer *s)
>> -{
>> - qemu_get_be32s(f, &s->frequency);
>> - qemu_get_be32s(f, &s->disabled);
>> - qemu_get_be64s(f, &s->disabled_mask);
>> - qemu_get_sbe64s(f, &s->clock_offset);
>> -
>> - qemu_get_timer(f, s->qtimer);
>> -}
>> -
>> static CPUTimer* cpu_timer_create(const char* name, CPUSPARCState *env,
>> QEMUBHFunc *cb, uint32_t frequency,
>> uint64_t disabled_mask)
>> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
>> index 1025752..ba9b833 100644
>> --- a/target-sparc/cpu.h
>> +++ b/target-sparc/cpu.h
>> @@ -374,10 +374,6 @@ struct CPUTimer
>>
>> typedef struct CPUTimer CPUTimer;
>>
>> -struct QEMUFile;
>> -void cpu_put_timer(struct QEMUFile *f, CPUTimer *s);
>> -void cpu_get_timer(struct QEMUFile *f, CPUTimer *s);
>> -
>> typedef struct CPUSPARCState CPUSPARCState;
>>
>> struct CPUSPARCState {
>> @@ -509,6 +505,9 @@ struct CPUSPARCState {
>>
>> /* Leon3 cache control */
>> uint32_t cache_control;
>> +
>> + /* Fields needed as intermediate for vmstate */
>> + uint32_t psr_vmstate;
>> };
>>
>> #ifndef NO_CPU_IO_DEFS
>> @@ -596,8 +595,6 @@ int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
>> #define cpu_signal_handler cpu_sparc_signal_handler
>> #define cpu_list sparc_cpu_list
>>
>> -#define CPU_SAVE_VERSION 7
>> -
>> /* MMU modes definitions */
>> #if defined (TARGET_SPARC64)
>> #define MMU_USER_IDX 0
>> diff --git a/target-sparc/machine.c b/target-sparc/machine.c
>> index eb4d87f..801ec55 100644
>> --- a/target-sparc/machine.c
>> +++ b/target-sparc/machine.c
>> @@ -4,214 +4,300 @@
>>
>> #include "cpu.h"
>>
>> -void cpu_save(QEMUFile *f, void *opaque)
>> -{
>> - CPUSPARCState *env = opaque;
>> - int i;
>> - uint32_t tmp;
>> -
>> - // if env->cwp == env->nwindows - 1, this will set the ins of the last
>> - // window as the outs of the first window
>> - cpu_set_cwp(env, env->cwp);
>> +static const VMStateDescription vmstate_cpu_timer = {
>> + .name = "cpu_timer",
>> + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .minimum_version_id_old = 1,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_UINT32(frequency, CPUTimer),
>> + VMSTATE_UINT32(disabled, CPUTimer),
>> + VMSTATE_UINT64(disabled_mask, CPUTimer),
>> + VMSTATE_INT64(clock_offset, CPUTimer),
>> + VMSTATE_TIMER(qtimer, CPUTimer),
>> + VMSTATE_END_OF_LIST()
>> + }
>> +};
>>
>> - for(i = 0; i < 8; i++)
>> - qemu_put_betls(f, &env->gregs[i]);
>> - qemu_put_be32s(f, &env->nwindows);
>> - for(i = 0; i < env->nwindows * 16; i++)
>> - qemu_put_betls(f, &env->regbase[i]);
>> +#define VMSTATE_CPU_TIMER(_f, _s) \
>> + VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_timer, CPUTimer *)
>>
>> - /* FPU */
>> - for (i = 0; i < TARGET_DPREGS; i++) {
>> - qemu_put_be32(f, env->fpr[i].l.upper);
>> - qemu_put_be32(f, env->fpr[i].l.lower);
>> +#if defined(TARGET_SPARC64)
>> +static const VMStateDescription vmstate_trap_state = {
>> + .name = "trap_state",
>> + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .minimum_version_id_old = 1,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_UINT64(tpc, trap_state),
>> + VMSTATE_UINT64(tnpc, trap_state),
>> + VMSTATE_UINT64(tstate, trap_state),
>> + VMSTATE_UINT32(tt, trap_state),
>> + VMSTATE_END_OF_LIST()
>> }
>> +};
>>
>> - qemu_put_betls(f, &env->pc);
>> - qemu_put_betls(f, &env->npc);
>> - qemu_put_betls(f, &env->y);
>> - tmp = cpu_get_psr(env);
>> - qemu_put_be32(f, tmp);
>> - qemu_put_betls(f, &env->fsr);
>> - qemu_put_betls(f, &env->tbr);
>> - tmp = env->interrupt_index;
>> - qemu_put_be32(f, tmp);
>> - qemu_put_be32s(f, &env->pil_in);
>> -#ifndef TARGET_SPARC64
>> - qemu_put_be32s(f, &env->wim);
>> - /* MMU */
>> - for (i = 0; i < 32; i++)
>> - qemu_put_be32s(f, &env->mmuregs[i]);
>> - for (i = 0; i < 4; i++) {
>> - qemu_put_be64s(f, &env->mxccdata[i]);
>> - }
>> - for (i = 0; i < 8; i++) {
>> - qemu_put_be64s(f, &env->mxccregs[i]);
>> - }
>> - qemu_put_be32s(f, &env->mmubpctrv);
>> - qemu_put_be32s(f, &env->mmubpctrc);
>> - qemu_put_be32s(f, &env->mmubpctrs);
>> - qemu_put_be64s(f, &env->mmubpaction);
>> - for (i = 0; i < 4; i++) {
>> - qemu_put_be64s(f, &env->mmubpregs[i]);
>> +static const VMStateDescription vmstate_tlb_entry = {
>> + .name = "tlb_entry",
>> + .version_id = 1,
>> + .minimum_version_id = 1,
>> + .minimum_version_id_old = 1,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_UINT64(tag, SparcTLBEntry),
>> + VMSTATE_UINT64(tte, SparcTLBEntry),
>> + VMSTATE_END_OF_LIST()
>> }
>> -#else
>> - qemu_put_be64s(f, &env->lsu);
>> - for (i = 0; i < 16; i++) {
>> - qemu_put_be64s(f, &env->immuregs[i]);
>> - qemu_put_be64s(f, &env->dmmuregs[i]);
>> - }
>> - for (i = 0; i < 64; i++) {
>> - qemu_put_be64s(f, &env->itlb[i].tag);
>> - qemu_put_be64s(f, &env->itlb[i].tte);
>> - qemu_put_be64s(f, &env->dtlb[i].tag);
>> - qemu_put_be64s(f, &env->dtlb[i].tte);
>> - }
>> - qemu_put_be32s(f, &env->mmu_version);
>> - for (i = 0; i < MAXTL_MAX; i++) {
>> - qemu_put_be64s(f, &env->ts[i].tpc);
>> - qemu_put_be64s(f, &env->ts[i].tnpc);
>> - qemu_put_be64s(f, &env->ts[i].tstate);
>> - qemu_put_be32s(f, &env->ts[i].tt);
>> - }
>> - qemu_put_be32s(f, &env->xcc);
>> - qemu_put_be32s(f, &env->asi);
>> - qemu_put_be32s(f, &env->pstate);
>> - qemu_put_be32s(f, &env->tl);
>> - qemu_put_be32s(f, &env->cansave);
>> - qemu_put_be32s(f, &env->canrestore);
>> - qemu_put_be32s(f, &env->otherwin);
>> - qemu_put_be32s(f, &env->wstate);
>> - qemu_put_be32s(f, &env->cleanwin);
>> - for (i = 0; i < 8; i++)
>> - qemu_put_be64s(f, &env->agregs[i]);
>> - for (i = 0; i < 8; i++)
>> - qemu_put_be64s(f, &env->bgregs[i]);
>> - for (i = 0; i < 8; i++)
>> - qemu_put_be64s(f, &env->igregs[i]);
>> - for (i = 0; i < 8; i++)
>> - qemu_put_be64s(f, &env->mgregs[i]);
>> - qemu_put_be64s(f, &env->fprs);
>> - qemu_put_be64s(f, &env->tick_cmpr);
>> - qemu_put_be64s(f, &env->stick_cmpr);
>> - cpu_put_timer(f, env->tick);
>> - cpu_put_timer(f, env->stick);
>> - qemu_put_be64s(f, &env->gsr);
>> - qemu_put_be32s(f, &env->gl);
>> - qemu_put_be64s(f, &env->hpstate);
>> - for (i = 0; i < MAXTL_MAX; i++)
>> - qemu_put_be64s(f, &env->htstate[i]);
>> - qemu_put_be64s(f, &env->hintp);
>> - qemu_put_be64s(f, &env->htba);
>> - qemu_put_be64s(f, &env->hver);
>> - qemu_put_be64s(f, &env->hstick_cmpr);
>> - qemu_put_be64s(f, &env->ssr);
>> - cpu_put_timer(f, env->hstick);
>> +};
>> #endif
>> -}
>>
>> -int cpu_load(QEMUFile *f, void *opaque, int version_id)
>> +static void cpu_pre_save(void *opaque)
>> {
>> CPUSPARCState *env = opaque;
>> - int i;
>> - uint32_t tmp;
>>
>> - if (version_id < 6)
>> - return -EINVAL;
>> - for(i = 0; i < 8; i++)
>> - qemu_get_betls(f, &env->gregs[i]);
>> - qemu_get_be32s(f, &env->nwindows);
>> - for(i = 0; i < env->nwindows * 16; i++)
>> - qemu_get_betls(f, &env->regbase[i]);
>> + /* if env->cwp == env->nwindows - 1, this will set the ins of the last
>> + * window as the outs of the first window
>> + */
>> + cpu_set_cwp(env, env->cwp);
>> + env->psr_vmstate = cpu_get_psr(env);
>> +}
>>
>> - /* FPU */
>> - for (i = 0; i < TARGET_DPREGS; i++) {
>> - env->fpr[i].l.upper = qemu_get_be32(f);
>> - env->fpr[i].l.lower = qemu_get_be32(f);
>> - }
>> +static int cpu_post_load(void *opaque, int version_id)
>> +{
>> + CPUSPARCState *env = opaque;
>>
>> - qemu_get_betls(f, &env->pc);
>> - qemu_get_betls(f, &env->npc);
>> - qemu_get_betls(f, &env->y);
>> - tmp = qemu_get_be32(f);
>> env->cwp = 0; /* needed to ensure that the wrapping registers are
>> correctly updated */
>> - cpu_put_psr(env, tmp);
>> - qemu_get_betls(f, &env->fsr);
>> - qemu_get_betls(f, &env->tbr);
>> - tmp = qemu_get_be32(f);
>> - env->interrupt_index = tmp;
>> - qemu_get_be32s(f, &env->pil_in);
>> -#ifndef TARGET_SPARC64
>> - qemu_get_be32s(f, &env->wim);
>> - /* MMU */
>> - for (i = 0; i < 32; i++)
>> - qemu_get_be32s(f, &env->mmuregs[i]);
>> - for (i = 0; i < 4; i++) {
>> - qemu_get_be64s(f, &env->mxccdata[i]);
>> - }
>> - for (i = 0; i < 8; i++) {
>> - qemu_get_be64s(f, &env->mxccregs[i]);
>> - }
>> - qemu_get_be32s(f, &env->mmubpctrv);
>> - qemu_get_be32s(f, &env->mmubpctrc);
>> - qemu_get_be32s(f, &env->mmubpctrs);
>> - qemu_get_be64s(f, &env->mmubpaction);
>> - for (i = 0; i < 4; i++) {
>> - qemu_get_be64s(f, &env->mmubpregs[i]);
>> - }
>> -#else
>> - qemu_get_be64s(f, &env->lsu);
>> - for (i = 0; i < 16; i++) {
>> - qemu_get_be64s(f, &env->immuregs[i]);
>> - qemu_get_be64s(f, &env->dmmuregs[i]);
>> - }
>> - for (i = 0; i < 64; i++) {
>> - qemu_get_be64s(f, &env->itlb[i].tag);
>> - qemu_get_be64s(f, &env->itlb[i].tte);
>> - qemu_get_be64s(f, &env->dtlb[i].tag);
>> - qemu_get_be64s(f, &env->dtlb[i].tte);
>> - }
>> - qemu_get_be32s(f, &env->mmu_version);
>> - for (i = 0; i < MAXTL_MAX; i++) {
>> - qemu_get_be64s(f, &env->ts[i].tpc);
>> - qemu_get_be64s(f, &env->ts[i].tnpc);
>> - qemu_get_be64s(f, &env->ts[i].tstate);
>> - qemu_get_be32s(f, &env->ts[i].tt);
>> - }
>> - qemu_get_be32s(f, &env->xcc);
>> - qemu_get_be32s(f, &env->asi);
>> - qemu_get_be32s(f, &env->pstate);
>> - qemu_get_be32s(f, &env->tl);
>> - qemu_get_be32s(f, &env->cansave);
>> - qemu_get_be32s(f, &env->canrestore);
>> - qemu_get_be32s(f, &env->otherwin);
>> - qemu_get_be32s(f, &env->wstate);
>> - qemu_get_be32s(f, &env->cleanwin);
>> - for (i = 0; i < 8; i++)
>> - qemu_get_be64s(f, &env->agregs[i]);
>> - for (i = 0; i < 8; i++)
>> - qemu_get_be64s(f, &env->bgregs[i]);
>> - for (i = 0; i < 8; i++)
>> - qemu_get_be64s(f, &env->igregs[i]);
>> - for (i = 0; i < 8; i++)
>> - qemu_get_be64s(f, &env->mgregs[i]);
>> - qemu_get_be64s(f, &env->fprs);
>> - qemu_get_be64s(f, &env->tick_cmpr);
>> - qemu_get_be64s(f, &env->stick_cmpr);
>> - cpu_get_timer(f, env->tick);
>> - cpu_get_timer(f, env->stick);
>> - qemu_get_be64s(f, &env->gsr);
>> - qemu_get_be32s(f, &env->gl);
>> - qemu_get_be64s(f, &env->hpstate);
>> - for (i = 0; i < MAXTL_MAX; i++)
>> - qemu_get_be64s(f, &env->htstate[i]);
>> - qemu_get_be64s(f, &env->hintp);
>> - qemu_get_be64s(f, &env->htba);
>> - qemu_get_be64s(f, &env->hver);
>> - qemu_get_be64s(f, &env->hstick_cmpr);
>> - qemu_get_be64s(f, &env->ssr);
>> - cpu_get_timer(f, env->hstick);
>> -#endif
>> + cpu_put_psr(env, env->psr_vmstate);
>
> This changes the behavior a bit: cpu_put_psr()->cpu_check_irqs() can
> modify env->interrupt_index. I suspect the original behavior was unintended
> though, doing this post-load seems to make a lot more sense.
Nice catch, it's unintended. Migration, save or load should use the
current env->interrupt index (which in theory could be stale) so that
there would not be any guest visible changes. This could be solved by
splitting cpu_put_psr into two functions without side effects.
>> tlb_flush(env, 1);
>> return 0;
>> }
>> +
>> +const VMStateDescription vmstate_cpu = {
>> + .name = "cpu",
>> + .version_id = 7,
>> + .minimum_version_id = 7,
>> + .minimum_version_id_old = 7,
>> + .pre_save = cpu_pre_save,
>> + .post_load = cpu_post_load,
>> + .fields = (VMStateField[]) {
>> + VMSTATE_UINTTL_ARRAY(gregs, CPUSPARCState, 8),
>> + VMSTATE_UINT32(nwindows, CPUSPARCState),
>> + VMSTATE_VARRAY_MULTIPLY(regbase, CPUSPARCState, nwindows, 16,
>> + vmstate_info_uinttls, target_ulong),
>> + VMSTATE_CPUDOUBLE_ARRAY(fpr, CPUSPARCState, TARGET_DPREGS),
>> + VMSTATE_UINTTL(pc, CPUSPARCState),
>> + VMSTATE_UINTTL(npc, CPUSPARCState),
>> + VMSTATE_UINTTL(y, CPUSPARCState),
>> + VMSTATE_UINT32(psr_vmstate, CPUSPARCState),
>> + VMSTATE_UINTTL(fsr, CPUSPARCState),
>> + VMSTATE_UINTTL(tbr, CPUSPARCState),
>> + VMSTATE_INT32(interrupt_index, CPUSPARCState),
>> + VMSTATE_UINT32(pil_in, CPUSPARCState),
>> +#ifndef TARGET_SPARC64
>> + /* MMU */
>> + VMSTATE_UINT32(wim, CPUSPARCState),
>> + VMSTATE_UINT32_ARRAY(mmuregs, CPUSPARCState, 32),
>> + VMSTATE_UINT64_ARRAY(mxccdata, CPUSPARCState, 4),
>> + VMSTATE_UINT64_ARRAY(mxccregs, CPUSPARCState, 8),
>> + VMSTATE_UINT32(mmubpctrv, CPUSPARCState),
>> + VMSTATE_UINT32(mmubpctrc, CPUSPARCState),
>> + VMSTATE_UINT32(mmubpctrs, CPUSPARCState),
>> + VMSTATE_UINT64(mmubpaction, CPUSPARCState),
>> + VMSTATE_UINT64_ARRAY(mmubpregs, CPUSPARCState, 4),
>> +#else
>> + VMSTATE_UINT64(lsu, CPUSPARCState),
>> + VMSTATE_UINT64(immuregs[0], CPUSPARCState),
>> + VMSTATE_UINT64(dmmuregs[0], CPUSPARCState),
>> + VMSTATE_UINT64(immuregs[1], CPUSPARCState),
>> + VMSTATE_UINT64(dmmuregs[1], CPUSPARCState),
>> + VMSTATE_UINT64(immuregs[2], CPUSPARCState),
>> + VMSTATE_UINT64(dmmuregs[2], CPUSPARCState),
>> + VMSTATE_UINT64(immuregs[3], CPUSPARCState),
>> + VMSTATE_UINT64(dmmuregs[3], CPUSPARCState),
>> + VMSTATE_UINT64(immuregs[4], CPUSPARCState),
>> + VMSTATE_UINT64(dmmuregs[4], CPUSPARCState),
>> + VMSTATE_UINT64(immuregs[5], CPUSPARCState),
>> + VMSTATE_UINT64(dmmuregs[5], CPUSPARCState),
>> + VMSTATE_UINT64(immuregs[6], CPUSPARCState),
>> + VMSTATE_UINT64(dmmuregs[6], CPUSPARCState),
>> + VMSTATE_UINT64(immuregs[7], CPUSPARCState),
>> + VMSTATE_UINT64(dmmuregs[7], CPUSPARCState),
>> + VMSTATE_UINT64(immuregs[8], CPUSPARCState),
>> + VMSTATE_UINT64(dmmuregs[8], CPUSPARCState),
>> + VMSTATE_UINT64(immuregs[9], CPUSPARCState),
>> + VMSTATE_UINT64(dmmuregs[9], CPUSPARCState),
>> + VMSTATE_UINT64(immuregs[10], CPUSPARCState),
>> + VMSTATE_UINT64(dmmuregs[10], CPUSPARCState),
>> + VMSTATE_UINT64(immuregs[11], CPUSPARCState),
>> + VMSTATE_UINT64(dmmuregs[11], CPUSPARCState),
>> + VMSTATE_UINT64(immuregs[12], CPUSPARCState),
>> + VMSTATE_UINT64(dmmuregs[12], CPUSPARCState),
>> + VMSTATE_UINT64(immuregs[13], CPUSPARCState),
>> + VMSTATE_UINT64(dmmuregs[13], CPUSPARCState),
>> + VMSTATE_UINT64(immuregs[14], CPUSPARCState),
>> + VMSTATE_UINT64(dmmuregs[14], CPUSPARCState),
>> + VMSTATE_UINT64(immuregs[15], CPUSPARCState),
>> + VMSTATE_UINT64(dmmuregs[15], CPUSPARCState),
>> + VMSTATE_STRUCT(itlb[0], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[0], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[1], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[1], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>
>> + VMSTATE_STRUCT(itlb[2], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[2], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[3], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[3], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[4], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[4], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[5], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[5], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[6], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[6], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[7], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[7], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[8], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[8], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[9], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[9], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[10], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[10], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[11], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[11], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[12], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[12], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[13], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[13], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[14], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[14], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[15], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[15], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[16], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[16], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[17], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[17], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[18], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[18], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[19], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[19], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[20], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[20], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[21], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[21], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[22], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[22], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[23], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[23], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[24], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[24], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[25], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[25], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[26], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[26], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[27], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[27], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[28], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[28], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[29], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[29], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[30], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[30], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[31], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[31], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[32], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[32], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[33], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[33], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[34], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[34], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[35], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[35], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[36], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[36], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[37], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[37], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[38], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[38], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[39], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[39], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[40], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[40], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[41], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[41], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[42], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[42], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[43], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[43], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[44], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[44], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[45], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[45], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[46], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[46], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[47], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[47], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[48], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[48], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[49], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[49], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[50], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[50], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[51], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[51], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[52], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[52], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[53], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[53], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[54], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[54], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[55], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[55], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[56], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[56], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[57], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[57], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[58], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[58], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[59], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[59], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[60], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[60], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[61], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[61], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[62], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[62], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(itlb[63], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_STRUCT(dtlb[63], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
>> + VMSTATE_UINT32(mmu_version, CPUSPARCState),
>> + VMSTATE_STRUCT_ARRAY(ts, CPUSPARCState, MAXTL_MAX, 0,
>> + vmstate_trap_state, trap_state),
>> + VMSTATE_UINT32(xcc, CPUSPARCState),
>> + VMSTATE_UINT32(asi, CPUSPARCState),
>> + VMSTATE_UINT32(pstate, CPUSPARCState),
>> + VMSTATE_UINT32(tl, CPUSPARCState),
>> + VMSTATE_UINT32(cansave, CPUSPARCState),
>> + VMSTATE_UINT32(canrestore, CPUSPARCState),
>> + VMSTATE_UINT32(otherwin, CPUSPARCState),
>> + VMSTATE_UINT32(wstate, CPUSPARCState),
>> + VMSTATE_UINT32(cleanwin, CPUSPARCState),
>> + VMSTATE_UINT64_ARRAY(agregs, CPUSPARCState, 8),
>> + VMSTATE_UINT64_ARRAY(bgregs, CPUSPARCState, 8),
>> + VMSTATE_UINT64_ARRAY(igregs, CPUSPARCState, 8),
>> + VMSTATE_UINT64_ARRAY(mgregs, CPUSPARCState, 8),
>> + VMSTATE_UINT64(fprs, CPUSPARCState),
>> + VMSTATE_UINT64(tick_cmpr, CPUSPARCState),
>> + VMSTATE_UINT64(stick_cmpr, CPUSPARCState),
>> + VMSTATE_CPU_TIMER(tick, CPUSPARCState),
>> + VMSTATE_CPU_TIMER(stick, CPUSPARCState),
>> + VMSTATE_UINT64(gsr, CPUSPARCState),
>> + VMSTATE_UINT32(gl, CPUSPARCState),
>> + VMSTATE_UINT64(hpstate, CPUSPARCState),
>> + VMSTATE_UINT64_ARRAY(htstate, CPUSPARCState, MAXTL_MAX),
>> + VMSTATE_UINT64(hintp, CPUSPARCState),
>> + VMSTATE_UINT64(htba, CPUSPARCState),
>> + VMSTATE_UINT64(hver, CPUSPARCState),
>> + VMSTATE_UINT64(hstick_cmpr, CPUSPARCState),
>> + VMSTATE_UINT64(ssr, CPUSPARCState),
>> + VMSTATE_CPU_TIMER(hstick, CPUSPARCState),
>> +#endif
>> + VMSTATE_END_OF_LIST()
>> + },
>> +};
>> --
>> 1.7.7.6
>>
>>
>
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH 17/36] vmstate: make incompatible change for sparc
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (15 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 16/36] vmstate: port sparc cpu Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 18/36] mips_fulong2e: cpu vmstate already registered in cpu_exec_init Juan Quintela
` (19 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
With this change, we sent arrays as arrays, making state description
much simpler. The change is incompatible, but as far as I know, sparc
don't care about migration compatibility beteween versions.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-sparc/machine.c | 172 +++---------------------------------------------
1 files changed, 9 insertions(+), 163 deletions(-)
diff --git a/target-sparc/machine.c b/target-sparc/machine.c
index 801ec55..818b11c 100644
--- a/target-sparc/machine.c
+++ b/target-sparc/machine.c
@@ -74,9 +74,9 @@ static int cpu_post_load(void *opaque, int version_id)
const VMStateDescription vmstate_cpu = {
.name = "cpu",
- .version_id = 7,
- .minimum_version_id = 7,
- .minimum_version_id_old = 7,
+ .version_id = 8,
+ .minimum_version_id = 8,
+ .minimum_version_id_old = 8,
.pre_save = cpu_pre_save,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
@@ -106,166 +106,12 @@ const VMStateDescription vmstate_cpu = {
VMSTATE_UINT64_ARRAY(mmubpregs, CPUSPARCState, 4),
#else
VMSTATE_UINT64(lsu, CPUSPARCState),
- VMSTATE_UINT64(immuregs[0], CPUSPARCState),
- VMSTATE_UINT64(dmmuregs[0], CPUSPARCState),
- VMSTATE_UINT64(immuregs[1], CPUSPARCState),
- VMSTATE_UINT64(dmmuregs[1], CPUSPARCState),
- VMSTATE_UINT64(immuregs[2], CPUSPARCState),
- VMSTATE_UINT64(dmmuregs[2], CPUSPARCState),
- VMSTATE_UINT64(immuregs[3], CPUSPARCState),
- VMSTATE_UINT64(dmmuregs[3], CPUSPARCState),
- VMSTATE_UINT64(immuregs[4], CPUSPARCState),
- VMSTATE_UINT64(dmmuregs[4], CPUSPARCState),
- VMSTATE_UINT64(immuregs[5], CPUSPARCState),
- VMSTATE_UINT64(dmmuregs[5], CPUSPARCState),
- VMSTATE_UINT64(immuregs[6], CPUSPARCState),
- VMSTATE_UINT64(dmmuregs[6], CPUSPARCState),
- VMSTATE_UINT64(immuregs[7], CPUSPARCState),
- VMSTATE_UINT64(dmmuregs[7], CPUSPARCState),
- VMSTATE_UINT64(immuregs[8], CPUSPARCState),
- VMSTATE_UINT64(dmmuregs[8], CPUSPARCState),
- VMSTATE_UINT64(immuregs[9], CPUSPARCState),
- VMSTATE_UINT64(dmmuregs[9], CPUSPARCState),
- VMSTATE_UINT64(immuregs[10], CPUSPARCState),
- VMSTATE_UINT64(dmmuregs[10], CPUSPARCState),
- VMSTATE_UINT64(immuregs[11], CPUSPARCState),
- VMSTATE_UINT64(dmmuregs[11], CPUSPARCState),
- VMSTATE_UINT64(immuregs[12], CPUSPARCState),
- VMSTATE_UINT64(dmmuregs[12], CPUSPARCState),
- VMSTATE_UINT64(immuregs[13], CPUSPARCState),
- VMSTATE_UINT64(dmmuregs[13], CPUSPARCState),
- VMSTATE_UINT64(immuregs[14], CPUSPARCState),
- VMSTATE_UINT64(dmmuregs[14], CPUSPARCState),
- VMSTATE_UINT64(immuregs[15], CPUSPARCState),
- VMSTATE_UINT64(dmmuregs[15], CPUSPARCState),
- VMSTATE_STRUCT(itlb[0], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[0], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[1], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[1], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[2], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[2], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[3], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[3], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[4], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[4], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[5], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[5], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[6], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[6], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[7], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[7], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[8], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[8], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[9], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[9], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[10], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[10], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[11], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[11], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[12], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[12], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[13], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[13], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[14], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[14], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[15], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[15], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[16], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[16], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[17], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[17], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[18], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[18], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[19], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[19], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[20], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[20], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[21], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[21], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[22], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[22], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[23], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[23], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[24], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[24], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[25], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[25], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[26], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[26], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[27], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[27], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[28], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[28], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[29], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[29], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[30], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[30], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[31], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[31], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[32], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[32], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[33], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[33], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[34], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[34], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[35], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[35], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[36], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[36], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[37], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[37], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[38], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[38], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[39], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[39], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[40], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[40], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[41], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[41], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[42], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[42], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[43], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[43], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[44], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[44], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[45], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[45], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[46], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[46], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[47], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[47], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[48], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[48], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[49], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[49], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[50], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[50], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[51], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[51], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[52], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[52], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[53], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[53], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[54], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[54], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[55], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[55], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[56], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[56], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[57], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[57], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[58], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[58], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[59], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[59], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[60], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[60], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[61], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[61], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[62], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[62], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(itlb[63], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
- VMSTATE_STRUCT(dtlb[63], CPUSPARCState, 0, vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_UINT64_ARRAY(immuregs, CPUSPARCState, 16),
+ VMSTATE_UINT64_ARRAY(dmmuregs, CPUSPARCState, 16),
+ VMSTATE_STRUCT_ARRAY(itlb, CPUSPARCState, 64, 0,
+ vmstate_tlb_entry, SparcTLBEntry),
+ VMSTATE_STRUCT_ARRAY(dtlb, CPUSPARCState, 64, 0,
+ vmstate_tlb_entry, SparcTLBEntry),
VMSTATE_UINT32(mmu_version, CPUSPARCState),
VMSTATE_STRUCT_ARRAY(ts, CPUSPARCState, MAXTL_MAX, 0,
vmstate_trap_state, trap_state),
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 18/36] mips_fulong2e: cpu vmstate already registered in cpu_exec_init
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (16 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 17/36] vmstate: make incompatible change for sparc Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 19/36] mips: make mvp an embedded struct instead of a pointer Juan Quintela
` (18 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
This is the second place that register cpu migration code, it is done
in general in cpu_exec_init(), just remove this call.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/mips_fulong2e.c | 1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/hw/mips_fulong2e.c b/hw/mips_fulong2e.c
index 37dc711..1a8df10 100644
--- a/hw/mips_fulong2e.c
+++ b/hw/mips_fulong2e.c
@@ -284,7 +284,6 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
exit(1);
}
- register_savevm(NULL, "cpu", 0, 3, cpu_save, cpu_load, env);
qemu_register_reset(main_cpu_reset, env);
/* fulong 2e has 256M ram. */
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 19/36] mips: make mvp an embedded struct instead of a pointer
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (17 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 18/36] mips_fulong2e: cpu vmstate already registered in cpu_exec_init Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 20/36] mips: make tlb " Juan Quintela
` (17 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Adjust all callers.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/mips_malta.c | 4 ++--
target-mips/cpu.h | 4 ++--
target-mips/machine.c | 12 ++++++------
target-mips/op_helper.c | 30 +++++++++++++++++-------------
target-mips/translate.c | 6 +++---
target-mips/translate_init.c | 14 ++++++--------
6 files changed, 36 insertions(+), 34 deletions(-)
diff --git a/hw/mips_malta.c b/hw/mips_malta.c
index 4752bb2..a1cdab5 100644
--- a/hw/mips_malta.c
+++ b/hw/mips_malta.c
@@ -745,8 +745,8 @@ static int64_t load_kernel (void)
static void malta_mips_config(CPUMIPSState *env)
{
- env->mvp->CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
- ((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC);
+ env->mvp.CP0_MVPConf0 |= ((smp_cpus - 1) << CP0MVPC0_PVPE) |
+ ((smp_cpus * env->nr_threads - 1) << CP0MVPC0_PTC);
}
static void main_cpu_reset(void *opaque)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 7430aa5..9450f0c 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -473,7 +473,7 @@ struct CPUMIPSState {
CPU_COMMON
- CPUMIPSMVPContext *mvp;
+ CPUMIPSMVPContext mvp;
#if !defined(CONFIG_USER_ONLY)
CPUMIPSTLBContext *tlb;
#endif
@@ -675,7 +675,7 @@ static inline int mips_vpe_active(CPUMIPSState *env)
int active = 1;
/* Check that the VPE is enabled. */
- if (!(env->mvp->CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
+ if (!(env->mvp.CP0_MVPControl & (1 << CP0MVPCo_EVP))) {
active = 0;
}
/* Check that the VPE is activated. */
diff --git a/target-mips/machine.c b/target-mips/machine.c
index 23504ba..d5d8865 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -52,9 +52,9 @@ void cpu_save(QEMUFile *f, void *opaque)
save_fpu(f, &env->active_fpu);
/* Save MVP */
- qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl);
- qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0);
- qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1);
+ qemu_put_sbe32s(f, &env->mvp.CP0_MVPControl);
+ qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf0);
+ qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf1);
/* Save TLB */
qemu_put_be32s(f, &env->tlb->nb_tlb);
@@ -203,9 +203,9 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
load_fpu(f, &env->active_fpu);
/* Load MVP */
- qemu_get_sbe32s(f, &env->mvp->CP0_MVPControl);
- qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf0);
- qemu_get_sbe32s(f, &env->mvp->CP0_MVPConf1);
+ qemu_get_sbe32s(f, &env->mvp.CP0_MVPControl);
+ qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf0);
+ qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf1);
/* Load TLB */
qemu_get_be32s(f, &env->tlb->nb_tlb);
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 3a20731..860b275 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -909,17 +909,17 @@ static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
/* CP0 helpers */
target_ulong helper_mfc0_mvpcontrol (void)
{
- return env->mvp->CP0_MVPControl;
+ return env->mvp.CP0_MVPControl;
}
target_ulong helper_mfc0_mvpconf0 (void)
{
- return env->mvp->CP0_MVPConf0;
+ return env->mvp.CP0_MVPConf0;
}
target_ulong helper_mfc0_mvpconf1 (void)
{
- return env->mvp->CP0_MVPConf1;
+ return env->mvp.CP0_MVPConf1;
}
target_ulong helper_mfc0_random (void)
@@ -1172,13 +1172,14 @@ void helper_mtc0_mvpcontrol (target_ulong arg1)
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
(1 << CP0MVPCo_EVP);
- if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (1 << CP0MVPCo_STLB);
- newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
+ }
+ newval = (env->mvp.CP0_MVPControl & ~mask) | (arg1 & mask);
// TODO: Enable/disable shared TLB, enable/disable VPEs.
- env->mvp->CP0_MVPControl = newval;
+ env->mvp.CP0_MVPControl = newval;
}
void helper_mtc0_vpecontrol (target_ulong arg1)
@@ -1266,9 +1267,10 @@ void helper_mtc0_vpeconf1 (target_ulong arg1)
uint32_t mask = 0;
uint32_t newval;
- if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
(0xff << CP0VPEC1_NCP1);
+ }
newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
/* UDI not implemented. */
@@ -1325,8 +1327,9 @@ void helper_mtc0_tcbind (target_ulong arg1)
uint32_t mask = (1 << CP0TCBd_TBE);
uint32_t newval;
- if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ if (env->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (1 << CP0TCBd_CurVPE);
+ }
newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
env->active_tc.CP0_TCBind = newval;
}
@@ -1338,8 +1341,9 @@ void helper_mttc0_tcbind (target_ulong arg1)
uint32_t newval;
CPUMIPSState *other = mips_cpu_map_tc(&other_tc);
- if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ if (other->mvp.CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (1 << CP0TCBd_CurVPE);
+ }
if (other_tc == other->current_tc) {
newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
other->active_tc.CP0_TCBind = newval;
@@ -1910,12 +1914,12 @@ target_ulong helper_emt(void)
target_ulong helper_dvpe(void)
{
CPUMIPSState *other_cpu = first_cpu;
- target_ulong prev = env->mvp->CP0_MVPControl;
+ target_ulong prev = env->mvp.CP0_MVPControl;
do {
/* Turn off all VPEs except the one executing the dvpe. */
if (other_cpu != env) {
- other_cpu->mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
+ other_cpu->mvp.CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
mips_vpe_sleep(other_cpu);
}
other_cpu = other_cpu->next_cpu;
@@ -1926,14 +1930,14 @@ target_ulong helper_dvpe(void)
target_ulong helper_evpe(void)
{
CPUMIPSState *other_cpu = first_cpu;
- target_ulong prev = env->mvp->CP0_MVPControl;
+ target_ulong prev = env->mvp.CP0_MVPControl;
do {
if (other_cpu != env
/* If the VPE is WFI, don't disturb its sleep. */
&& !mips_vpe_is_wfi(other_cpu)) {
/* Enable the VPE. */
- other_cpu->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+ other_cpu->mvp.CP0_MVPControl |= (1 << CP0MVPCo_EVP);
mips_vpe_wake(other_cpu); /* And wake it up. */
}
other_cpu = other_cpu->next_cpu;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index a663b74..6afa923 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -5526,7 +5526,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd,
(env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
tcg_gen_movi_tl(t0, -1);
else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
- (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
+ (env->mvp.CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
tcg_gen_movi_tl(t0, -1);
else if (u == 0) {
switch (rt) {
@@ -5744,7 +5744,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt,
(env->active_tc.CP0_TCBind & (0xf << CP0TCBd_CurVPE))))
/* NOP */ ;
else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) >
- (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
+ (env->mvp.CP0_MVPConf0 & (0xff << CP0MVPC0_PTC)))
/* NOP */ ;
else if (u == 0) {
switch (rd) {
@@ -12820,7 +12820,7 @@ void cpu_state_reset(CPUMIPSState *env)
if (!env->cpu_index) {
/* VPE0 starts up enabled. */
- env->mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
+ env->mvp.CP0_MVPControl |= (1 << CP0MVPCo_EVP);
env->CP0_VPEConf0 |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
/* TC0 starts up unhalted. */
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c39138f..54fd1eb 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -568,27 +568,25 @@ static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
{
- env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
-
/* MVPConf1 implemented, TLB sharable, no gating storage support,
programmable cache partitioning implemented, number of allocatable
and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
implemented, 5 TCs implemented. */
- env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
- (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
+ env->mvp.CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
+ (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
// TODO: actually do 2 VPEs.
// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
// (0x04 << CP0MVPC0_PTC);
- (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
- (0x00 << CP0MVPC0_PTC);
+ (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
+ (0x00 << CP0MVPC0_PTC);
#if !defined(CONFIG_USER_ONLY)
/* Usermode has no TLB support */
- env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
+ env->mvp.CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
#endif
/* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
- env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
+ env->mvp.CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
(0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
(0x1 << CP0MVPC1_PCP1);
}
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 20/36] mips: make tlb an embedded struct instead of a pointer
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (18 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 19/36] mips: make mvp an embedded struct instead of a pointer Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 21/36] mips: bump migration version to 4 Juan Quintela
` (16 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Adjust all callers.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
hw/mips_timer.c | 2 +-
target-mips/cpu.h | 2 +-
target-mips/helper.c | 30 +++++++++++++---------
target-mips/machine.c | 56 +++++++++++++++++++++---------------------
target-mips/op_helper.c | 40 +++++++++++++++---------------
target-mips/translate.c | 16 +++++++----
target-mips/translate_init.c | 24 ++++++++---------
7 files changed, 89 insertions(+), 81 deletions(-)
diff --git a/hw/mips_timer.c b/hw/mips_timer.c
index 7aa9004..33e4021 100644
--- a/hw/mips_timer.c
+++ b/hw/mips_timer.c
@@ -35,7 +35,7 @@ uint32_t cpu_mips_get_random (CPUMIPSState *env)
/* Don't return same value twice, so get another value */
do {
lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u);
- idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
+ idx = lfsr % (env->tlb.nb_tlb - env->CP0_Wired) + env->CP0_Wired;
} while (idx == prev_idx);
prev_idx = idx;
return idx;
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 9450f0c..074882e 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -475,7 +475,7 @@ struct CPUMIPSState {
CPUMIPSMVPContext mvp;
#if !defined(CONFIG_USER_ONLY)
- CPUMIPSTLBContext *tlb;
+ CPUMIPSTLBContext tlb;
#endif
const mips_def_t *cpu_model;
diff --git a/target-mips/helper.c b/target-mips/helper.c
index ddf9cb7..b2f2658 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -69,8 +69,8 @@ int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
uint8_t ASID = env->CP0_EntryHi & 0xFF;
int i;
- for (i = 0; i < env->tlb->tlb_in_use; i++) {
- r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
+ for (i = 0; i < env->tlb.tlb_in_use; i++) {
+ r4k_tlb_t *tlb = &env->tlb.mmu.r4k.tlb[i];
/* 1k pages are not supported. */
target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
target_ulong tag = address & ~mask;
@@ -124,13 +124,15 @@ static int get_physical_address (CPUMIPSState *env, target_phys_addr_t *physical
*physical = address & 0xFFFFFFFF;
*prot = PAGE_READ | PAGE_WRITE;
} else {
- ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ ret = env->tlb.map_address(env, physical, prot, address, rw,
+ access_type);
}
#if defined(TARGET_MIPS64)
} else if (address < 0x4000000000000000ULL) {
/* xuseg */
if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
- ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ ret = env->tlb.map_address(env, physical, prot, address, rw,
+ access_type);
} else {
ret = TLBRET_BADADDR;
}
@@ -138,7 +140,8 @@ static int get_physical_address (CPUMIPSState *env, target_phys_addr_t *physical
/* xsseg */
if ((supervisor_mode || kernel_mode) &&
SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
- ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ ret = env->tlb.map_address(env, physical, prot, address, rw,
+ access_type);
} else {
ret = TLBRET_BADADDR;
}
@@ -155,7 +158,8 @@ static int get_physical_address (CPUMIPSState *env, target_phys_addr_t *physical
/* xkseg */
if (kernel_mode && KX &&
address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
- ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ ret = env->tlb.map_address(env, physical, prot, address, rw,
+ access_type);
} else {
ret = TLBRET_BADADDR;
}
@@ -179,7 +183,8 @@ static int get_physical_address (CPUMIPSState *env, target_phys_addr_t *physical
} else if (address < (int32_t)0xE0000000UL) {
/* sseg (kseg2) */
if (supervisor_mode || kernel_mode) {
- ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ ret = env->tlb.map_address(env, physical, prot, address, rw,
+ access_type);
} else {
ret = TLBRET_BADADDR;
}
@@ -187,7 +192,8 @@ static int get_physical_address (CPUMIPSState *env, target_phys_addr_t *physical
/* kseg3 */
/* XXX: debug segment is not emulated */
if (kernel_mode) {
- ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
+ ret = env->tlb.map_address(env, physical, prot, address, rw,
+ access_type);
} else {
ret = TLBRET_BADADDR;
}
@@ -645,19 +651,19 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
uint8_t ASID = env->CP0_EntryHi & 0xFF;
target_ulong mask;
- tlb = &env->tlb->mmu.r4k.tlb[idx];
+ tlb = &env->tlb.mmu.r4k.tlb[idx];
/* The qemu TLB is flushed when the ASID changes, so no need to
flush these entries again. */
if (tlb->G == 0 && tlb->ASID != ASID) {
return;
}
- if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
+ if (use_extra && env->tlb.tlb_in_use < MIPS_TLB_MAX) {
/* For tlbwr, we can shadow the discarded entry into
a new (fake) TLB entry, as long as the guest can not
tell that it's there. */
- env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
- env->tlb->tlb_in_use++;
+ env->tlb.mmu.r4k.tlb[env->tlb.tlb_in_use] = *tlb;
+ env->tlb.tlb_in_use++;
return;
}
diff --git a/target-mips/machine.c b/target-mips/machine.c
index d5d8865..4a1d2d8 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -57,25 +57,25 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf1);
/* Save TLB */
- qemu_put_be32s(f, &env->tlb->nb_tlb);
- qemu_put_be32s(f, &env->tlb->tlb_in_use);
+ qemu_put_be32s(f, &env->tlb.nb_tlb);
+ qemu_put_be32s(f, &env->tlb.tlb_in_use);
for(i = 0; i < MIPS_TLB_MAX; i++) {
- uint16_t flags = ((env->tlb->mmu.r4k.tlb[i].G << 10) |
- (env->tlb->mmu.r4k.tlb[i].C0 << 7) |
- (env->tlb->mmu.r4k.tlb[i].C1 << 4) |
- (env->tlb->mmu.r4k.tlb[i].V0 << 3) |
- (env->tlb->mmu.r4k.tlb[i].V1 << 2) |
- (env->tlb->mmu.r4k.tlb[i].D0 << 1) |
- (env->tlb->mmu.r4k.tlb[i].D1 << 0));
+ uint16_t flags = ((env->tlb.mmu.r4k.tlb[i].G << 10) |
+ (env->tlb.mmu.r4k.tlb[i].C0 << 7) |
+ (env->tlb.mmu.r4k.tlb[i].C1 << 4) |
+ (env->tlb.mmu.r4k.tlb[i].V0 << 3) |
+ (env->tlb.mmu.r4k.tlb[i].V1 << 2) |
+ (env->tlb.mmu.r4k.tlb[i].D0 << 1) |
+ (env->tlb.mmu.r4k.tlb[i].D1 << 0));
uint8_t asid;
- qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
- qemu_put_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
- asid = env->tlb->mmu.r4k.tlb[i].ASID;
+ qemu_put_betls(f, &env->tlb.mmu.r4k.tlb[i].VPN);
+ qemu_put_be32s(f, &env->tlb.mmu.r4k.tlb[i].PageMask);
+ asid = env->tlb.mmu.r4k.tlb[i].ASID;
qemu_put_8s(f, &asid);
qemu_put_be16s(f, &flags);
- qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
- qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
+ qemu_put_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[0]);
+ qemu_put_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[1]);
}
/* Save CPU metastate */
@@ -208,26 +208,26 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf1);
/* Load TLB */
- qemu_get_be32s(f, &env->tlb->nb_tlb);
- qemu_get_be32s(f, &env->tlb->tlb_in_use);
+ qemu_get_be32s(f, &env->tlb.nb_tlb);
+ qemu_get_be32s(f, &env->tlb.tlb_in_use);
for(i = 0; i < MIPS_TLB_MAX; i++) {
uint16_t flags;
uint8_t asid;
- qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
- qemu_get_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
+ qemu_get_betls(f, &env->tlb.mmu.r4k.tlb[i].VPN);
+ qemu_get_be32s(f, &env->tlb.mmu.r4k.tlb[i].PageMask);
qemu_get_8s(f, &asid);
- env->tlb->mmu.r4k.tlb[i].ASID = asid;
+ env->tlb.mmu.r4k.tlb[i].ASID = asid;
qemu_get_be16s(f, &flags);
- env->tlb->mmu.r4k.tlb[i].G = (flags >> 10) & 1;
- env->tlb->mmu.r4k.tlb[i].C0 = (flags >> 7) & 3;
- env->tlb->mmu.r4k.tlb[i].C1 = (flags >> 4) & 3;
- env->tlb->mmu.r4k.tlb[i].V0 = (flags >> 3) & 1;
- env->tlb->mmu.r4k.tlb[i].V1 = (flags >> 2) & 1;
- env->tlb->mmu.r4k.tlb[i].D0 = (flags >> 1) & 1;
- env->tlb->mmu.r4k.tlb[i].D1 = (flags >> 0) & 1;
- qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
- qemu_get_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
+ env->tlb.mmu.r4k.tlb[i].G = (flags >> 10) & 1;
+ env->tlb.mmu.r4k.tlb[i].C0 = (flags >> 7) & 3;
+ env->tlb.mmu.r4k.tlb[i].C1 = (flags >> 4) & 3;
+ env->tlb.mmu.r4k.tlb[i].V0 = (flags >> 3) & 1;
+ env->tlb.mmu.r4k.tlb[i].V1 = (flags >> 2) & 1;
+ env->tlb.mmu.r4k.tlb[i].D0 = (flags >> 1) & 1;
+ env->tlb.mmu.r4k.tlb[i].D1 = (flags >> 0) & 1;
+ qemu_get_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[0]);
+ qemu_get_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[1]);
}
/* Load CPU metastate */
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 860b275..19d09fa 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1155,7 +1155,7 @@ target_ulong helper_dmfc0_watchlo (uint32_t sel)
void helper_mtc0_index (target_ulong arg1)
{
int num = 1;
- unsigned int tmp = env->tlb->nb_tlb;
+ unsigned int tmp = env->tlb.nb_tlb;
do {
tmp >>= 1;
@@ -1486,7 +1486,7 @@ void helper_mtc0_pagegrain (target_ulong arg1)
void helper_mtc0_wired (target_ulong arg1)
{
- env->CP0_Wired = arg1 % env->tlb->nb_tlb;
+ env->CP0_Wired = arg1 % env->tlb.nb_tlb;
}
void helper_mtc0_srsconf0 (target_ulong arg1)
@@ -1989,14 +1989,14 @@ static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
{
/* Flush qemu's TLB and discard all shadowed entries. */
tlb_flush (env, flush_global);
- env->tlb->tlb_in_use = env->tlb->nb_tlb;
+ env->tlb.tlb_in_use = env->tlb.nb_tlb;
}
static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
{
/* Discard entries from env->tlb[first] onwards. */
- while (env->tlb->tlb_in_use > first) {
- r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
+ while (env->tlb.tlb_in_use > first) {
+ r4k_invalidate_tlb(env, --env->tlb.tlb_in_use, 0);
}
}
@@ -2005,7 +2005,7 @@ static void r4k_fill_tlb (int idx)
r4k_tlb_t *tlb;
/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
- tlb = &env->tlb->mmu.r4k.tlb[idx];
+ tlb = &env->tlb.mmu.r4k.tlb[idx];
tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
#if defined(TARGET_MIPS64)
tlb->VPN &= env->SEGMask;
@@ -2027,12 +2027,12 @@ void r4k_helper_tlbwi (void)
{
int idx;
- idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
+ idx = (env->CP0_Index & ~0x80000000) % env->tlb.nb_tlb;
/* Discard cached TLB entries. We could avoid doing this if the
tlbwi is just upgrading access permissions on the current entry;
that might be a further win. */
- r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb);
+ r4k_mips_tlb_flush_extra(env, env->tlb.nb_tlb);
r4k_invalidate_tlb(env, idx, 0);
r4k_fill_tlb(idx);
@@ -2056,8 +2056,8 @@ void r4k_helper_tlbp (void)
int i;
ASID = env->CP0_EntryHi & 0xFF;
- for (i = 0; i < env->tlb->nb_tlb; i++) {
- tlb = &env->tlb->mmu.r4k.tlb[i];
+ for (i = 0; i < env->tlb.nb_tlb; i++) {
+ tlb = &env->tlb.mmu.r4k.tlb[i];
/* 1k pages are not supported. */
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
tag = env->CP0_EntryHi & ~mask;
@@ -2069,10 +2069,10 @@ void r4k_helper_tlbp (void)
break;
}
}
- if (i == env->tlb->nb_tlb) {
+ if (i == env->tlb.nb_tlb) {
/* No match. Discard any shadow entries, if any of them match. */
- for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
- tlb = &env->tlb->mmu.r4k.tlb[i];
+ for (i = env->tlb.nb_tlb; i < env->tlb.tlb_in_use; i++) {
+ tlb = &env->tlb.mmu.r4k.tlb[i];
/* 1k pages are not supported. */
mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
tag = env->CP0_EntryHi & ~mask;
@@ -2095,14 +2095,14 @@ void r4k_helper_tlbr (void)
int idx;
ASID = env->CP0_EntryHi & 0xFF;
- idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
- tlb = &env->tlb->mmu.r4k.tlb[idx];
+ idx = (env->CP0_Index & ~0x80000000) % env->tlb.nb_tlb;
+ tlb = &env->tlb.mmu.r4k.tlb[idx];
/* If this will change the current ASID, flush qemu's TLB. */
if (ASID != tlb->ASID)
cpu_mips_tlb_flush (env, 1);
- r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
+ r4k_mips_tlb_flush_extra(env, env->tlb.nb_tlb);
env->CP0_EntryHi = tlb->VPN | tlb->ASID;
env->CP0_PageMask = tlb->PageMask;
@@ -2114,22 +2114,22 @@ void r4k_helper_tlbr (void)
void helper_tlbwi(void)
{
- env->tlb->helper_tlbwi();
+ env->tlb.helper_tlbwi();
}
void helper_tlbwr(void)
{
- env->tlb->helper_tlbwr();
+ env->tlb.helper_tlbwr();
}
void helper_tlbp(void)
{
- env->tlb->helper_tlbp();
+ env->tlb.helper_tlbp();
}
void helper_tlbr(void)
{
- env->tlb->helper_tlbr();
+ env->tlb.helper_tlbr();
}
/* Specials */
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 6afa923..9157794 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -5992,26 +5992,30 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt,
break;
case OPC_TLBWI:
opn = "tlbwi";
- if (!env->tlb->helper_tlbwi)
+ if (!env->tlb.helper_tlbwi) {
goto die;
+ }
gen_helper_tlbwi();
break;
case OPC_TLBWR:
opn = "tlbwr";
- if (!env->tlb->helper_tlbwr)
+ if (!env->tlb.helper_tlbwr) {
goto die;
+ }
gen_helper_tlbwr();
break;
case OPC_TLBP:
opn = "tlbp";
- if (!env->tlb->helper_tlbp)
+ if (!env->tlb.helper_tlbp) {
goto die;
+ }
gen_helper_tlbp();
break;
case OPC_TLBR:
opn = "tlbr";
- if (!env->tlb->helper_tlbr)
+ if (!env->tlb.helper_tlbr) {
goto die;
+ }
gen_helper_tlbr();
break;
case OPC_ERET:
@@ -12785,8 +12789,8 @@ void cpu_state_reset(CPUMIPSState *env)
env->CP0_ErrorEPC = env->active_tc.PC;
}
env->active_tc.PC = (int32_t)0xBFC00000;
- env->CP0_Random = env->tlb->nb_tlb - 1;
- env->tlb->tlb_in_use = env->tlb->nb_tlb;
+ env->CP0_Random = env->tlb.nb_tlb - 1;
+ env->tlb.tlb_in_use = env->tlb.nb_tlb;
env->CP0_Wired = 0;
env->CP0_EBase = 0x80000000 | (env->cpu_index & 0x3FF);
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 54fd1eb..0adb304 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -513,30 +513,28 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
#ifndef CONFIG_USER_ONLY
static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
{
- env->tlb->nb_tlb = 1;
- env->tlb->map_address = &no_mmu_map_address;
+ env->tlb.nb_tlb = 1;
+ env->tlb.map_address = &no_mmu_map_address;
}
static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
{
- env->tlb->nb_tlb = 1;
- env->tlb->map_address = &fixed_mmu_map_address;
+ env->tlb.nb_tlb = 1;
+ env->tlb.map_address = &fixed_mmu_map_address;
}
static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
{
- env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
- env->tlb->map_address = &r4k_map_address;
- env->tlb->helper_tlbwi = r4k_helper_tlbwi;
- env->tlb->helper_tlbwr = r4k_helper_tlbwr;
- env->tlb->helper_tlbp = r4k_helper_tlbp;
- env->tlb->helper_tlbr = r4k_helper_tlbr;
+ env->tlb.nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
+ env->tlb.map_address = &r4k_map_address;
+ env->tlb.helper_tlbwi = r4k_helper_tlbwi;
+ env->tlb.helper_tlbwr = r4k_helper_tlbwr;
+ env->tlb.helper_tlbp = r4k_helper_tlbp;
+ env->tlb.helper_tlbr = r4k_helper_tlbr;
}
static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
{
- env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
-
switch (def->mmu_type) {
case MMU_TYPE_NONE:
no_mmu_init(env, def);
@@ -581,7 +579,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
(0x00 << CP0MVPC0_PTC);
#if !defined(CONFIG_USER_ONLY)
/* Usermode has no TLB support */
- env->mvp.CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
+ env->mvp.CP0_MVPConf0 |= (env->tlb.nb_tlb << CP0MVPC0_PTLBE);
#endif
/* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 21/36] mips: bump migration version to 4
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (19 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 20/36] mips: make tlb " Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 22/36] vmstate: port mips cpu Juan Quintela
` (15 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
bcond state was stored as int32, but it is target_ulong. Change migration state
to reflect that.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-mips/cpu.h | 2 +-
target-mips/machine.c | 10 ++++------
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 074882e..d2773d6 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -507,7 +507,7 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
#define cpu_signal_handler cpu_mips_signal_handler
#define cpu_list mips_cpu_list
-#define CPU_SAVE_VERSION 3
+#define CPU_SAVE_VERSION 4
/* MMU modes definitions. We carefully match the indices with our
hflags layout. */
diff --git a/target-mips/machine.c b/target-mips/machine.c
index 4a1d2d8..8b9c0fb 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -84,8 +84,7 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_sbe32s(f, &env->error_code);
qemu_put_be32s(f, &env->hflags);
qemu_put_betls(f, &env->btarget);
- i = env->bcond;
- qemu_put_sbe32s(f, &i);
+ qemu_put_betls(f, &env->bcond);
/* Save remaining CP1 registers */
qemu_put_sbe32s(f, &env->CP0_Index);
@@ -193,9 +192,9 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
CPUMIPSState *env = opaque;
int i;
- if (version_id != 3)
+ if (version_id != 4) {
return -EINVAL;
-
+ }
/* Load active TC */
load_tc(f, &env->active_tc);
@@ -236,8 +235,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_sbe32s(f, &env->error_code);
qemu_get_be32s(f, &env->hflags);
qemu_get_betls(f, &env->btarget);
- qemu_get_sbe32s(f, &i);
- env->bcond = i;
+ qemu_get_betls(f, &env->bcond);
/* Load remaining CP1 registers */
qemu_get_sbe32s(f, &env->CP0_Index);
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 22/36] vmstate: port mips cpu
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (20 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 21/36] mips: bump migration version to 4 Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 23/36] arm: save always 32 fpu registers Juan Quintela
` (14 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-mips/cpu.h | 5 +-
target-mips/machine.c | 465 +++++++++++++++++++------------------------------
2 files changed, 182 insertions(+), 288 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index d2773d6..2475d32 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -37,6 +37,9 @@ struct r4k_tlb_t {
uint_fast16_t D0:1;
uint_fast16_t D1:1;
target_ulong PFN[2];
+ /* Fields needed as intermediate for vmstate */
+ uint8_t asid_vmstate;
+ uint16_t flags_vmstate;
};
#if !defined(CONFIG_USER_ONLY)
@@ -507,8 +510,6 @@ void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
#define cpu_signal_handler cpu_mips_signal_handler
#define cpu_list mips_cpu_list
-#define CPU_SAVE_VERSION 4
-
/* MMU modes definitions. We carefully match the indices with our
hflags layout. */
#define MMU_MODE0_SUFFIX _kernel
diff --git a/target-mips/machine.c b/target-mips/machine.c
index 8b9c0fb..8951748 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -3,304 +3,197 @@
#include "cpu.h"
-static void save_tc(QEMUFile *f, TCState *tc)
-{
- int i;
-
- /* Save active TC */
- for(i = 0; i < 32; i++)
- qemu_put_betls(f, &tc->gpr[i]);
- qemu_put_betls(f, &tc->PC);
- for(i = 0; i < MIPS_DSP_ACC; i++)
- qemu_put_betls(f, &tc->HI[i]);
- for(i = 0; i < MIPS_DSP_ACC; i++)
- qemu_put_betls(f, &tc->LO[i]);
- for(i = 0; i < MIPS_DSP_ACC; i++)
- qemu_put_betls(f, &tc->ACX[i]);
- qemu_put_betls(f, &tc->DSPControl);
- qemu_put_sbe32s(f, &tc->CP0_TCStatus);
- qemu_put_sbe32s(f, &tc->CP0_TCBind);
- qemu_put_betls(f, &tc->CP0_TCHalt);
- qemu_put_betls(f, &tc->CP0_TCContext);
- qemu_put_betls(f, &tc->CP0_TCSchedule);
- qemu_put_betls(f, &tc->CP0_TCScheFBack);
- qemu_put_sbe32s(f, &tc->CP0_Debug_tcstatus);
-}
-
-static void save_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
-{
- int i;
-
- for(i = 0; i < 32; i++)
- qemu_put_be64s(f, &fpu->fpr[i].d);
- qemu_put_s8s(f, &fpu->fp_status.float_detect_tininess);
- qemu_put_s8s(f, &fpu->fp_status.float_rounding_mode);
- qemu_put_s8s(f, &fpu->fp_status.float_exception_flags);
- qemu_put_be32s(f, &fpu->fcr0);
- qemu_put_be32s(f, &fpu->fcr31);
-}
-
-void cpu_save(QEMUFile *f, void *opaque)
-{
- CPUMIPSState *env = opaque;
- int i;
-
- /* Save active TC */
- save_tc(f, &env->active_tc);
-
- /* Save active FPU */
- save_fpu(f, &env->active_fpu);
-
- /* Save MVP */
- qemu_put_sbe32s(f, &env->mvp.CP0_MVPControl);
- qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf0);
- qemu_put_sbe32s(f, &env->mvp.CP0_MVPConf1);
-
- /* Save TLB */
- qemu_put_be32s(f, &env->tlb.nb_tlb);
- qemu_put_be32s(f, &env->tlb.tlb_in_use);
- for(i = 0; i < MIPS_TLB_MAX; i++) {
- uint16_t flags = ((env->tlb.mmu.r4k.tlb[i].G << 10) |
- (env->tlb.mmu.r4k.tlb[i].C0 << 7) |
- (env->tlb.mmu.r4k.tlb[i].C1 << 4) |
- (env->tlb.mmu.r4k.tlb[i].V0 << 3) |
- (env->tlb.mmu.r4k.tlb[i].V1 << 2) |
- (env->tlb.mmu.r4k.tlb[i].D0 << 1) |
- (env->tlb.mmu.r4k.tlb[i].D1 << 0));
- uint8_t asid;
-
- qemu_put_betls(f, &env->tlb.mmu.r4k.tlb[i].VPN);
- qemu_put_be32s(f, &env->tlb.mmu.r4k.tlb[i].PageMask);
- asid = env->tlb.mmu.r4k.tlb[i].ASID;
- qemu_put_8s(f, &asid);
- qemu_put_be16s(f, &flags);
- qemu_put_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[0]);
- qemu_put_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[1]);
+static const VMStateDescription vmstate_tc = {
+ .name = "tc",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL_ARRAY(gpr, TCState, 32),
+ VMSTATE_UINTTL(PC, TCState),
+ VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC),
+ VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC),
+ VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC),
+ VMSTATE_UINTTL(DSPControl, TCState),
+ VMSTATE_INT32(CP0_TCStatus, TCState),
+ VMSTATE_INT32(CP0_TCBind, TCState),
+ VMSTATE_UINTTL(CP0_TCHalt, TCState),
+ VMSTATE_UINTTL(CP0_TCContext, TCState),
+ VMSTATE_UINTTL(CP0_TCSchedule, TCState),
+ VMSTATE_UINTTL(CP0_TCScheFBack, TCState),
+ VMSTATE_INT32(CP0_Debug_tcstatus, TCState),
+ VMSTATE_END_OF_LIST()
}
+};
+
+static const VMStateDescription vmstate_fpu_reg = {
+ .name = "fpu_reg",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(d, fpr_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_fpu_context = {
+ .name = "fpu_context",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT_ARRAY(fpr, CPUMIPSFPUContext, 32, 0,
+ vmstate_fpu_reg, fpr_t),
+ VMSTATE_INT8(fp_status.float_detect_tininess, CPUMIPSFPUContext),
+ VMSTATE_INT8(fp_status.float_rounding_mode, CPUMIPSFPUContext),
+ VMSTATE_INT8(fp_status.float_exception_flags, CPUMIPSFPUContext),
+ VMSTATE_UINT32(fcr0, CPUMIPSFPUContext),
+ VMSTATE_UINT32(fcr31, CPUMIPSFPUContext),
+ VMSTATE_END_OF_LIST()
+ }
+};
- /* Save CPU metastate */
- qemu_put_be32s(f, &env->current_tc);
- qemu_put_be32s(f, &env->current_fpu);
- qemu_put_sbe32s(f, &env->error_code);
- qemu_put_be32s(f, &env->hflags);
- qemu_put_betls(f, &env->btarget);
- qemu_put_betls(f, &env->bcond);
-
- /* Save remaining CP1 registers */
- qemu_put_sbe32s(f, &env->CP0_Index);
- qemu_put_sbe32s(f, &env->CP0_Random);
- qemu_put_sbe32s(f, &env->CP0_VPEControl);
- qemu_put_sbe32s(f, &env->CP0_VPEConf0);
- qemu_put_sbe32s(f, &env->CP0_VPEConf1);
- qemu_put_betls(f, &env->CP0_YQMask);
- qemu_put_betls(f, &env->CP0_VPESchedule);
- qemu_put_betls(f, &env->CP0_VPEScheFBack);
- qemu_put_sbe32s(f, &env->CP0_VPEOpt);
- qemu_put_betls(f, &env->CP0_EntryLo0);
- qemu_put_betls(f, &env->CP0_EntryLo1);
- qemu_put_betls(f, &env->CP0_Context);
- qemu_put_sbe32s(f, &env->CP0_PageMask);
- qemu_put_sbe32s(f, &env->CP0_PageGrain);
- qemu_put_sbe32s(f, &env->CP0_Wired);
- qemu_put_sbe32s(f, &env->CP0_SRSConf0);
- qemu_put_sbe32s(f, &env->CP0_SRSConf1);
- qemu_put_sbe32s(f, &env->CP0_SRSConf2);
- qemu_put_sbe32s(f, &env->CP0_SRSConf3);
- qemu_put_sbe32s(f, &env->CP0_SRSConf4);
- qemu_put_sbe32s(f, &env->CP0_HWREna);
- qemu_put_betls(f, &env->CP0_BadVAddr);
- qemu_put_sbe32s(f, &env->CP0_Count);
- qemu_put_betls(f, &env->CP0_EntryHi);
- qemu_put_sbe32s(f, &env->CP0_Compare);
- qemu_put_sbe32s(f, &env->CP0_Status);
- qemu_put_sbe32s(f, &env->CP0_IntCtl);
- qemu_put_sbe32s(f, &env->CP0_SRSCtl);
- qemu_put_sbe32s(f, &env->CP0_SRSMap);
- qemu_put_sbe32s(f, &env->CP0_Cause);
- qemu_put_betls(f, &env->CP0_EPC);
- qemu_put_sbe32s(f, &env->CP0_PRid);
- qemu_put_sbe32s(f, &env->CP0_EBase);
- qemu_put_sbe32s(f, &env->CP0_Config0);
- qemu_put_sbe32s(f, &env->CP0_Config1);
- qemu_put_sbe32s(f, &env->CP0_Config2);
- qemu_put_sbe32s(f, &env->CP0_Config3);
- qemu_put_sbe32s(f, &env->CP0_Config6);
- qemu_put_sbe32s(f, &env->CP0_Config7);
- qemu_put_betls(f, &env->lladdr);
- for(i = 0; i < 8; i++)
- qemu_put_betls(f, &env->CP0_WatchLo[i]);
- for(i = 0; i < 8; i++)
- qemu_put_sbe32s(f, &env->CP0_WatchHi[i]);
- qemu_put_betls(f, &env->CP0_XContext);
- qemu_put_sbe32s(f, &env->CP0_Framemask);
- qemu_put_sbe32s(f, &env->CP0_Debug);
- qemu_put_betls(f, &env->CP0_DEPC);
- qemu_put_sbe32s(f, &env->CP0_Performance0);
- qemu_put_sbe32s(f, &env->CP0_TagLo);
- qemu_put_sbe32s(f, &env->CP0_DataLo);
- qemu_put_sbe32s(f, &env->CP0_TagHi);
- qemu_put_sbe32s(f, &env->CP0_DataHi);
- qemu_put_betls(f, &env->CP0_ErrorEPC);
- qemu_put_sbe32s(f, &env->CP0_DESAVE);
-
- /* Save inactive TC state */
- for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)
- save_tc(f, &env->tcs[i]);
- for (i = 0; i < MIPS_FPU_MAX; i++)
- save_fpu(f, &env->fpus[i]);
-}
-
-static void load_tc(QEMUFile *f, TCState *tc)
+static void tlb_pre_save(void *opaque)
{
- int i;
-
- /* Save active TC */
- for(i = 0; i < 32; i++)
- qemu_get_betls(f, &tc->gpr[i]);
- qemu_get_betls(f, &tc->PC);
- for(i = 0; i < MIPS_DSP_ACC; i++)
- qemu_get_betls(f, &tc->HI[i]);
- for(i = 0; i < MIPS_DSP_ACC; i++)
- qemu_get_betls(f, &tc->LO[i]);
- for(i = 0; i < MIPS_DSP_ACC; i++)
- qemu_get_betls(f, &tc->ACX[i]);
- qemu_get_betls(f, &tc->DSPControl);
- qemu_get_sbe32s(f, &tc->CP0_TCStatus);
- qemu_get_sbe32s(f, &tc->CP0_TCBind);
- qemu_get_betls(f, &tc->CP0_TCHalt);
- qemu_get_betls(f, &tc->CP0_TCContext);
- qemu_get_betls(f, &tc->CP0_TCSchedule);
- qemu_get_betls(f, &tc->CP0_TCScheFBack);
- qemu_get_sbe32s(f, &tc->CP0_Debug_tcstatus);
+ r4k_tlb_t *tlb = opaque;
+
+ tlb->asid_vmstate = tlb->ASID;
+ tlb->flags_vmstate = ((tlb->G << 10) |
+ (tlb->C0 << 7) |
+ (tlb->C1 << 4) |
+ (tlb->V0 << 3) |
+ (tlb->V1 << 2) |
+ (tlb->D0 << 1) |
+ (tlb->D1 << 0));
}
-static void load_fpu(QEMUFile *f, CPUMIPSFPUContext *fpu)
+static int tlb_post_load(void *opaque, int version_id)
{
- int i;
-
- for(i = 0; i < 32; i++)
- qemu_get_be64s(f, &fpu->fpr[i].d);
- qemu_get_s8s(f, &fpu->fp_status.float_detect_tininess);
- qemu_get_s8s(f, &fpu->fp_status.float_rounding_mode);
- qemu_get_s8s(f, &fpu->fp_status.float_exception_flags);
- qemu_get_be32s(f, &fpu->fcr0);
- qemu_get_be32s(f, &fpu->fcr31);
+ r4k_tlb_t *tlb = opaque;
+
+ tlb->ASID = tlb->asid_vmstate;
+ tlb->G = (tlb->flags_vmstate >> 10) & 1;
+ tlb->C0 = (tlb->flags_vmstate >> 7) & 3;
+ tlb->C1 = (tlb->flags_vmstate >> 4) & 3;
+ tlb->V0 = (tlb->flags_vmstate >> 3) & 1;
+ tlb->V1 = (tlb->flags_vmstate >> 2) & 1;
+ tlb->D0 = (tlb->flags_vmstate >> 1) & 1;
+ tlb->D1 = (tlb->flags_vmstate >> 0) & 1;
+ return 0;
}
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
-{
- CPUMIPSState *env = opaque;
- int i;
-
- if (version_id != 4) {
- return -EINVAL;
- }
- /* Load active TC */
- load_tc(f, &env->active_tc);
-
- /* Load active FPU */
- load_fpu(f, &env->active_fpu);
-
- /* Load MVP */
- qemu_get_sbe32s(f, &env->mvp.CP0_MVPControl);
- qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf0);
- qemu_get_sbe32s(f, &env->mvp.CP0_MVPConf1);
-
- /* Load TLB */
- qemu_get_be32s(f, &env->tlb.nb_tlb);
- qemu_get_be32s(f, &env->tlb.tlb_in_use);
- for(i = 0; i < MIPS_TLB_MAX; i++) {
- uint16_t flags;
- uint8_t asid;
-
- qemu_get_betls(f, &env->tlb.mmu.r4k.tlb[i].VPN);
- qemu_get_be32s(f, &env->tlb.mmu.r4k.tlb[i].PageMask);
- qemu_get_8s(f, &asid);
- env->tlb.mmu.r4k.tlb[i].ASID = asid;
- qemu_get_be16s(f, &flags);
- env->tlb.mmu.r4k.tlb[i].G = (flags >> 10) & 1;
- env->tlb.mmu.r4k.tlb[i].C0 = (flags >> 7) & 3;
- env->tlb.mmu.r4k.tlb[i].C1 = (flags >> 4) & 3;
- env->tlb.mmu.r4k.tlb[i].V0 = (flags >> 3) & 1;
- env->tlb.mmu.r4k.tlb[i].V1 = (flags >> 2) & 1;
- env->tlb.mmu.r4k.tlb[i].D0 = (flags >> 1) & 1;
- env->tlb.mmu.r4k.tlb[i].D1 = (flags >> 0) & 1;
- qemu_get_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[0]);
- qemu_get_betls(f, &env->tlb.mmu.r4k.tlb[i].PFN[1]);
+static const VMStateDescription vmstate_tlb = {
+ .name = "tlb",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .pre_save = tlb_pre_save,
+ .post_load = tlb_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(VPN, r4k_tlb_t),
+ VMSTATE_UINT32(PageMask, r4k_tlb_t),
+ VMSTATE_UINT8(asid_vmstate, r4k_tlb_t),
+ VMSTATE_UINT16(flags_vmstate, r4k_tlb_t),
+ VMSTATE_UINTTL_ARRAY(PFN, r4k_tlb_t, 2),
+ VMSTATE_END_OF_LIST()
}
+};
- /* Load CPU metastate */
- qemu_get_be32s(f, &env->current_tc);
- qemu_get_be32s(f, &env->current_fpu);
- qemu_get_sbe32s(f, &env->error_code);
- qemu_get_be32s(f, &env->hflags);
- qemu_get_betls(f, &env->btarget);
- qemu_get_betls(f, &env->bcond);
-
- /* Load remaining CP1 registers */
- qemu_get_sbe32s(f, &env->CP0_Index);
- qemu_get_sbe32s(f, &env->CP0_Random);
- qemu_get_sbe32s(f, &env->CP0_VPEControl);
- qemu_get_sbe32s(f, &env->CP0_VPEConf0);
- qemu_get_sbe32s(f, &env->CP0_VPEConf1);
- qemu_get_betls(f, &env->CP0_YQMask);
- qemu_get_betls(f, &env->CP0_VPESchedule);
- qemu_get_betls(f, &env->CP0_VPEScheFBack);
- qemu_get_sbe32s(f, &env->CP0_VPEOpt);
- qemu_get_betls(f, &env->CP0_EntryLo0);
- qemu_get_betls(f, &env->CP0_EntryLo1);
- qemu_get_betls(f, &env->CP0_Context);
- qemu_get_sbe32s(f, &env->CP0_PageMask);
- qemu_get_sbe32s(f, &env->CP0_PageGrain);
- qemu_get_sbe32s(f, &env->CP0_Wired);
- qemu_get_sbe32s(f, &env->CP0_SRSConf0);
- qemu_get_sbe32s(f, &env->CP0_SRSConf1);
- qemu_get_sbe32s(f, &env->CP0_SRSConf2);
- qemu_get_sbe32s(f, &env->CP0_SRSConf3);
- qemu_get_sbe32s(f, &env->CP0_SRSConf4);
- qemu_get_sbe32s(f, &env->CP0_HWREna);
- qemu_get_betls(f, &env->CP0_BadVAddr);
- qemu_get_sbe32s(f, &env->CP0_Count);
- qemu_get_betls(f, &env->CP0_EntryHi);
- qemu_get_sbe32s(f, &env->CP0_Compare);
- qemu_get_sbe32s(f, &env->CP0_Status);
- qemu_get_sbe32s(f, &env->CP0_IntCtl);
- qemu_get_sbe32s(f, &env->CP0_SRSCtl);
- qemu_get_sbe32s(f, &env->CP0_SRSMap);
- qemu_get_sbe32s(f, &env->CP0_Cause);
- qemu_get_betls(f, &env->CP0_EPC);
- qemu_get_sbe32s(f, &env->CP0_PRid);
- qemu_get_sbe32s(f, &env->CP0_EBase);
- qemu_get_sbe32s(f, &env->CP0_Config0);
- qemu_get_sbe32s(f, &env->CP0_Config1);
- qemu_get_sbe32s(f, &env->CP0_Config2);
- qemu_get_sbe32s(f, &env->CP0_Config3);
- qemu_get_sbe32s(f, &env->CP0_Config6);
- qemu_get_sbe32s(f, &env->CP0_Config7);
- qemu_get_betls(f, &env->lladdr);
- for(i = 0; i < 8; i++)
- qemu_get_betls(f, &env->CP0_WatchLo[i]);
- for(i = 0; i < 8; i++)
- qemu_get_sbe32s(f, &env->CP0_WatchHi[i]);
- qemu_get_betls(f, &env->CP0_XContext);
- qemu_get_sbe32s(f, &env->CP0_Framemask);
- qemu_get_sbe32s(f, &env->CP0_Debug);
- qemu_get_betls(f, &env->CP0_DEPC);
- qemu_get_sbe32s(f, &env->CP0_Performance0);
- qemu_get_sbe32s(f, &env->CP0_TagLo);
- qemu_get_sbe32s(f, &env->CP0_DataLo);
- qemu_get_sbe32s(f, &env->CP0_TagHi);
- qemu_get_sbe32s(f, &env->CP0_DataHi);
- qemu_get_betls(f, &env->CP0_ErrorEPC);
- qemu_get_sbe32s(f, &env->CP0_DESAVE);
-
- /* Load inactive TC state */
- for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)
- load_tc(f, &env->tcs[i]);
- for (i = 0; i < MIPS_FPU_MAX; i++)
- load_fpu(f, &env->fpus[i]);
+static int cpu_post_load(void *opaque, int version_id)
+{
+ CPUMIPSState *env = opaque;
/* XXX: ensure compatibility for halted bit ? */
tlb_flush(env, 1);
return 0;
}
+
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .version_id = 4,
+ .minimum_version_id = 4,
+ .minimum_version_id_old = 4,
+ .post_load = cpu_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_STRUCT(active_tc, CPUMIPSState, 0, vmstate_tc, TCState),
+ VMSTATE_STRUCT(active_fpu, CPUMIPSState, 0, vmstate_fpu_context,
+ CPUMIPSFPUContext),
+ /* Save MVP */
+ VMSTATE_INT32(mvp.CP0_MVPControl, CPUMIPSState),
+ VMSTATE_INT32(mvp.CP0_MVPConf0, CPUMIPSState),
+ VMSTATE_INT32(mvp.CP0_MVPConf1, CPUMIPSState),
+ /* Save TLB */
+ VMSTATE_UINT32(tlb.nb_tlb, CPUMIPSState),
+ VMSTATE_UINT32(tlb.tlb_in_use, CPUMIPSState),
+ VMSTATE_STRUCT_ARRAY(tlb.mmu.r4k.tlb, CPUMIPSState, MIPS_TLB_MAX, 0,
+ vmstate_tlb, r4k_tlb_t),
+ /* Save CPU metastate */
+ VMSTATE_UINT32(current_tc, CPUMIPSState),
+ VMSTATE_UINT32(current_fpu, CPUMIPSState),
+ VMSTATE_INT32(error_code, CPUMIPSState),
+ VMSTATE_UINT32(hflags, CPUMIPSState),
+ VMSTATE_UINTTL(btarget, CPUMIPSState),
+ VMSTATE_UINTTL(bcond, CPUMIPSState),
+ /* Save remaining CP1 registers */
+ VMSTATE_INT32(CP0_Index, CPUMIPSState),
+ VMSTATE_INT32(CP0_Random, CPUMIPSState),
+ VMSTATE_INT32(CP0_VPEControl, CPUMIPSState),
+ VMSTATE_INT32(CP0_VPEConf0, CPUMIPSState),
+ VMSTATE_INT32(CP0_VPEConf1, CPUMIPSState),
+ VMSTATE_UINTTL(CP0_YQMask, CPUMIPSState),
+ VMSTATE_UINTTL(CP0_VPESchedule, CPUMIPSState),
+ VMSTATE_UINTTL(CP0_VPEScheFBack, CPUMIPSState),
+ VMSTATE_INT32(CP0_VPEOpt, CPUMIPSState),
+ VMSTATE_UINTTL(CP0_EntryLo0, CPUMIPSState),
+ VMSTATE_UINTTL(CP0_EntryLo1, CPUMIPSState),
+ VMSTATE_UINTTL(CP0_Context, CPUMIPSState),
+ VMSTATE_INT32(CP0_PageMask, CPUMIPSState),
+ VMSTATE_INT32(CP0_PageGrain, CPUMIPSState),
+ VMSTATE_INT32(CP0_Wired, CPUMIPSState),
+ VMSTATE_INT32(CP0_SRSConf0, CPUMIPSState),
+ VMSTATE_INT32(CP0_SRSConf1, CPUMIPSState),
+ VMSTATE_INT32(CP0_SRSConf2, CPUMIPSState),
+ VMSTATE_INT32(CP0_SRSConf3, CPUMIPSState),
+ VMSTATE_INT32(CP0_SRSConf4, CPUMIPSState),
+ VMSTATE_INT32(CP0_HWREna, CPUMIPSState),
+ VMSTATE_UINTTL(CP0_BadVAddr, CPUMIPSState),
+ VMSTATE_INT32(CP0_Count, CPUMIPSState),
+ VMSTATE_UINTTL(CP0_EntryHi, CPUMIPSState),
+ VMSTATE_INT32(CP0_Compare, CPUMIPSState),
+ VMSTATE_INT32(CP0_Status, CPUMIPSState),
+ VMSTATE_INT32(CP0_IntCtl, CPUMIPSState),
+ VMSTATE_INT32(CP0_SRSCtl, CPUMIPSState),
+ VMSTATE_INT32(CP0_SRSMap, CPUMIPSState),
+ VMSTATE_INT32(CP0_Cause, CPUMIPSState),
+ VMSTATE_UINTTL(CP0_EPC, CPUMIPSState),
+ VMSTATE_INT32(CP0_PRid, CPUMIPSState),
+ VMSTATE_INT32(CP0_EBase, CPUMIPSState),
+ VMSTATE_INT32(CP0_Config0, CPUMIPSState),
+ VMSTATE_INT32(CP0_Config1, CPUMIPSState),
+ VMSTATE_INT32(CP0_Config2, CPUMIPSState),
+ VMSTATE_INT32(CP0_Config3, CPUMIPSState),
+ VMSTATE_INT32(CP0_Config6, CPUMIPSState),
+ VMSTATE_INT32(CP0_Config7, CPUMIPSState),
+ VMSTATE_UINTTL(lladdr, CPUMIPSState),
+ VMSTATE_UINTTL_ARRAY(CP0_WatchLo, CPUMIPSState, 8),
+ VMSTATE_INT32_ARRAY(CP0_WatchHi, CPUMIPSState, 8),
+ VMSTATE_UINTTL(CP0_XContext, CPUMIPSState),
+ VMSTATE_INT32(CP0_Framemask, CPUMIPSState),
+ VMSTATE_INT32(CP0_Debug, CPUMIPSState),
+ VMSTATE_UINTTL(CP0_DEPC, CPUMIPSState),
+ VMSTATE_INT32(CP0_Performance0, CPUMIPSState),
+ VMSTATE_INT32(CP0_TagLo, CPUMIPSState),
+ VMSTATE_INT32(CP0_DataLo, CPUMIPSState),
+ VMSTATE_INT32(CP0_TagHi, CPUMIPSState),
+ VMSTATE_INT32(CP0_DataHi, CPUMIPSState),
+ VMSTATE_UINTTL(CP0_ErrorEPC, CPUMIPSState),
+ VMSTATE_INT32(CP0_DESAVE, CPUMIPSState),
+ /* Save inactive TC state */
+ VMSTATE_STRUCT_ARRAY(tcs, CPUMIPSState, MIPS_SHADOW_SET_MAX, 0,
+ vmstate_tc, TCState),
+ VMSTATE_STRUCT_ARRAY(fpus, CPUMIPSState, MIPS_FPU_MAX, 0,
+ vmstate_fpu_context, CPUMIPSFPUContext),
+ VMSTATE_END_OF_LIST()
+ },
+};
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 23/36] arm: save always 32 fpu registers
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (21 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 22/36] vmstate: port mips cpu Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-20 11:54 ` Peter Maydell
2012-03-19 22:57 ` [Qemu-devel] [PATCH 24/36] vmstate: port arm cpu Juan Quintela
` (13 subsequent siblings)
36 siblings, 1 reply; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
This way, we fix a bug (we were overwritten the 16 first registers on
load), and we don't need to check for ARM_FEATUR_VPF3, we always send
the 32 registers.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-arm/cpu.h | 2 +-
target-arm/machine.c | 22 ++--------------------
2 files changed, 3 insertions(+), 21 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 26c114b..a6e8c7e 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -455,7 +455,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list
-#define CPU_SAVE_VERSION 6
+#define CPU_SAVE_VERSION 7
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
diff --git a/target-arm/machine.c b/target-arm/machine.c
index f66b8df..9c0f773 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -64,7 +64,7 @@ void cpu_save(QEMUFile *f, void *opaque)
qemu_put_be32(f, env->features);
if (arm_feature(env, ARM_FEATURE_VFP)) {
- for (i = 0; i < 16; i++) {
+ for (i = 0; i < 32; i++) {
CPU_DoubleU u;
u.d = env->vfp.regs[i];
qemu_put_be32(f, u.l.upper);
@@ -77,15 +77,6 @@ void cpu_save(QEMUFile *f, void *opaque)
/* TODO: Should use proper FPSCR access functions. */
qemu_put_be32(f, env->vfp.vec_len);
qemu_put_be32(f, env->vfp.vec_stride);
-
- if (arm_feature(env, ARM_FEATURE_VFP3)) {
- for (i = 16; i < 32; i++) {
- CPU_DoubleU u;
- u.d = env->vfp.regs[i];
- qemu_put_be32(f, u.l.upper);
- qemu_put_be32(f, u.l.lower);
- }
- }
}
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
@@ -182,7 +173,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
env->features = qemu_get_be32(f);
if (arm_feature(env, ARM_FEATURE_VFP)) {
- for (i = 0; i < 16; i++) {
+ for (i = 0; i < 32; i++) {
CPU_DoubleU u;
u.l.upper = qemu_get_be32(f);
u.l.lower = qemu_get_be32(f);
@@ -195,15 +186,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id)
/* TODO: Should use proper FPSCR access functions. */
env->vfp.vec_len = qemu_get_be32(f);
env->vfp.vec_stride = qemu_get_be32(f);
-
- if (arm_feature(env, ARM_FEATURE_VFP3)) {
- for (i = 16; i < 32; i++) {
- CPU_DoubleU u;
- u.l.upper = qemu_get_be32(f);
- u.l.lower = qemu_get_be32(f);
- env->vfp.regs[i] = u.d;
- }
- }
}
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH 23/36] arm: save always 32 fpu registers
2012-03-19 22:57 ` [Qemu-devel] [PATCH 23/36] arm: save always 32 fpu registers Juan Quintela
@ 2012-03-20 11:54 ` Peter Maydell
2012-03-20 12:27 ` Juan Quintela
0 siblings, 1 reply; 60+ messages in thread
From: Peter Maydell @ 2012-03-20 11:54 UTC (permalink / raw)
To: Juan Quintela; +Cc: qemu-devel
On 19 March 2012 22:57, Juan Quintela <quintela@redhat.com> wrote:
> This way, we fix a bug (we were overwritten the 16 first registers on
> load), and we don't need to check for ARM_FEATUR_VPF3, we always send
> the 32 registers.
This commit message is out of date -- the overwriting bug was
fixed in commit 15180256 last year. Possibly the patch should
be dropped from your series? (If not, "ARM_FEATURE_VFP3".)
-- PMM
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH 23/36] arm: save always 32 fpu registers
2012-03-20 11:54 ` Peter Maydell
@ 2012-03-20 12:27 ` Juan Quintela
2012-03-20 13:48 ` Peter Maydell
0 siblings, 1 reply; 60+ messages in thread
From: Juan Quintela @ 2012-03-20 12:27 UTC (permalink / raw)
To: Peter Maydell; +Cc: qemu-devel
Peter Maydell <peter.maydell@linaro.org> wrote:
> On 19 March 2012 22:57, Juan Quintela <quintela@redhat.com> wrote:
>> This way, we fix a bug (we were overwritten the 16 first registers on
>> load), and we don't need to check for ARM_FEATUR_VPF3, we always send
>> the 32 registers.
>
> This commit message is out of date -- the overwriting bug was
> fixed in commit 15180256 last year. Possibly the patch should
> be dropped from your series? (If not, "ARM_FEATURE_VFP3".)
Reason for the change is not to have to write partial arrays.
Current code is doing
if ARM_FEATURE_VFP
send first 16 registers
if (ARM_FEATURE_VFP3
send second 16 registers
I change it to:
if ARM_FEATURE_VFP
send 32 registers
Notice that:
a- there is always 32 registers
b- makes the migration format the same for VFP and VFP3
c- we are already incompatible with previous versions, so this is not a
problem.
Normally, the less different options that we have on the migration
format, the easy to make sense of it. It was not related to the bug
that we used to have in this area.
Later, Juan.
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH 23/36] arm: save always 32 fpu registers
2012-03-20 12:27 ` Juan Quintela
@ 2012-03-20 13:48 ` Peter Maydell
0 siblings, 0 replies; 60+ messages in thread
From: Peter Maydell @ 2012-03-20 13:48 UTC (permalink / raw)
To: quintela; +Cc: qemu-devel
On 20 March 2012 12:27, Juan Quintela <quintela@redhat.com> wrote:
> Peter Maydell <peter.maydell@linaro.org> wrote:
>> This commit message is out of date -- the overwriting bug was
>> fixed in commit 15180256 last year. Possibly the patch should
>> be dropped from your series? (If not, "ARM_FEATURE_VFP3".)
>
> Reason for the change is not to have to write partial arrays.
> Normally, the less different options that we have on the migration
> format, the easy to make sense of it. It was not related to the bug
> that we used to have in this area.
OK, so you just need to fix the commit message.
thanks
-- PMM
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH 24/36] vmstate: port arm cpu
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (22 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 23/36] arm: save always 32 fpu registers Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-21 16:29 ` Andreas Färber
2012-03-19 22:57 ` [Qemu-devel] [PATCH 25/36] vmstate: all cpus converted Juan Quintela
` (12 subsequent siblings)
36 siblings, 1 reply; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Use one subsection for each feature. This means that we don't need to
bump the version field each time that a new feature gets introduced.
Introduce cpsr_vmstate field, as I am not sure if I can "use"
uncached_cpsr for saving state.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-arm/cpu.h | 5 +-
target-arm/machine.c | 344 ++++++++++++++++++++++----------------------------
2 files changed, 156 insertions(+), 193 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index a6e8c7e..aafb4a7 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -233,6 +233,9 @@ typedef struct CPUARMState {
} cp[15];
void *nvic;
const struct arm_boot_info *boot_info;
+
+ /* Fields needed as intermediate for vmstate */
+ uint32_t cpsr_vmstate;
} CPUARMState;
CPUARMState *cpu_arm_init(const char *cpu_model);
@@ -455,8 +458,6 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define cpu_signal_handler cpu_arm_signal_handler
#define cpu_list arm_cpu_list
-#define CPU_SAVE_VERSION 7
-
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 9c0f773..31e49ac 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -1,215 +1,177 @@
#include "hw/hw.h"
#include "hw/boards.h"
-void cpu_save(QEMUFile *f, void *opaque)
+static bool feature_vfp_needed(void *opaque)
{
- int i;
- CPUARMState *env = (CPUARMState *)opaque;
+ CPUARMState *env = opaque;
- for (i = 0; i < 16; i++) {
- qemu_put_be32(f, env->regs[i]);
- }
- qemu_put_be32(f, cpsr_read(env));
- qemu_put_be32(f, env->spsr);
- for (i = 0; i < 6; i++) {
- qemu_put_be32(f, env->banked_spsr[i]);
- qemu_put_be32(f, env->banked_r13[i]);
- qemu_put_be32(f, env->banked_r14[i]);
- }
- for (i = 0; i < 5; i++) {
- qemu_put_be32(f, env->usr_regs[i]);
- qemu_put_be32(f, env->fiq_regs[i]);
- }
- qemu_put_be32(f, env->cp15.c0_cpuid);
- qemu_put_be32(f, env->cp15.c0_cachetype);
- qemu_put_be32(f, env->cp15.c0_cssel);
- qemu_put_be32(f, env->cp15.c1_sys);
- qemu_put_be32(f, env->cp15.c1_coproc);
- qemu_put_be32(f, env->cp15.c1_xscaleauxcr);
- qemu_put_be32(f, env->cp15.c1_scr);
- qemu_put_be32(f, env->cp15.c2_base0);
- qemu_put_be32(f, env->cp15.c2_base1);
- qemu_put_be32(f, env->cp15.c2_control);
- qemu_put_be32(f, env->cp15.c2_mask);
- qemu_put_be32(f, env->cp15.c2_base_mask);
- qemu_put_be32(f, env->cp15.c2_data);
- qemu_put_be32(f, env->cp15.c2_insn);
- qemu_put_be32(f, env->cp15.c3);
- qemu_put_be32(f, env->cp15.c5_insn);
- qemu_put_be32(f, env->cp15.c5_data);
- for (i = 0; i < 8; i++) {
- qemu_put_be32(f, env->cp15.c6_region[i]);
- }
- qemu_put_be32(f, env->cp15.c6_insn);
- qemu_put_be32(f, env->cp15.c6_data);
- qemu_put_be32(f, env->cp15.c7_par);
- qemu_put_be32(f, env->cp15.c9_insn);
- qemu_put_be32(f, env->cp15.c9_data);
- qemu_put_be32(f, env->cp15.c9_pmcr);
- qemu_put_be32(f, env->cp15.c9_pmcnten);
- qemu_put_be32(f, env->cp15.c9_pmovsr);
- qemu_put_be32(f, env->cp15.c9_pmxevtyper);
- qemu_put_be32(f, env->cp15.c9_pmuserenr);
- qemu_put_be32(f, env->cp15.c9_pminten);
- qemu_put_be32(f, env->cp15.c13_fcse);
- qemu_put_be32(f, env->cp15.c13_context);
- qemu_put_be32(f, env->cp15.c13_tls1);
- qemu_put_be32(f, env->cp15.c13_tls2);
- qemu_put_be32(f, env->cp15.c13_tls3);
- qemu_put_be32(f, env->cp15.c15_cpar);
- qemu_put_be32(f, env->cp15.c15_power_control);
- qemu_put_be32(f, env->cp15.c15_diagnostic);
- qemu_put_be32(f, env->cp15.c15_power_diagnostic);
-
- qemu_put_be32(f, env->features);
-
- if (arm_feature(env, ARM_FEATURE_VFP)) {
- for (i = 0; i < 32; i++) {
- CPU_DoubleU u;
- u.d = env->vfp.regs[i];
- qemu_put_be32(f, u.l.upper);
- qemu_put_be32(f, u.l.lower);
- }
- for (i = 0; i < 16; i++) {
- qemu_put_be32(f, env->vfp.xregs[i]);
- }
+ return arm_feature(env, ARM_FEATURE_VFP);
+}
+static const VMStateDescription vmstate_feature_vfp = {
+ .name = "feature_vfp",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_FLOAT64_ARRAY(vfp.regs, CPUARMState, 32),
+ VMSTATE_UINT32_ARRAY(vfp.xregs, CPUARMState, 16),
/* TODO: Should use proper FPSCR access functions. */
- qemu_put_be32(f, env->vfp.vec_len);
- qemu_put_be32(f, env->vfp.vec_stride);
+ VMSTATE_INT32(vfp.vec_len, CPUARMState),
+ VMSTATE_INT32(vfp.vec_stride, CPUARMState),
+ VMSTATE_END_OF_LIST()
}
+};
- if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
- for (i = 0; i < 16; i++) {
- qemu_put_be64(f, env->iwmmxt.regs[i]);
- }
- for (i = 0; i < 16; i++) {
- qemu_put_be32(f, env->iwmmxt.cregs[i]);
- }
- }
+static bool feature_iwmmxt_needed(void *opaque)
+{
+ CPUARMState *env = opaque;
- if (arm_feature(env, ARM_FEATURE_M)) {
- qemu_put_be32(f, env->v7m.other_sp);
- qemu_put_be32(f, env->v7m.vecbase);
- qemu_put_be32(f, env->v7m.basepri);
- qemu_put_be32(f, env->v7m.control);
- qemu_put_be32(f, env->v7m.current_sp);
- qemu_put_be32(f, env->v7m.exception);
- }
+ return arm_feature(env, ARM_FEATURE_IWMMXT);
+}
- if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
- qemu_put_be32(f, env->teecr);
- qemu_put_be32(f, env->teehbr);
+static const VMStateDescription vmstate_feature_iwmmxt = {
+ .name = "feature_iwmmxt",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64_ARRAY(iwmmxt.regs, CPUARMState, 16),
+ VMSTATE_UINT32_ARRAY(iwmmxt.cregs, CPUARMState, 16),
+ VMSTATE_END_OF_LIST()
}
-}
+};
-int cpu_load(QEMUFile *f, void *opaque, int version_id)
+static bool feature_m_needed(void *opaque)
{
- CPUARMState *env = (CPUARMState *)opaque;
- int i;
- uint32_t val;
+ CPUARMState *env = opaque;
- if (version_id != CPU_SAVE_VERSION)
- return -EINVAL;
+ return arm_feature(env, ARM_FEATURE_M);
+}
- for (i = 0; i < 16; i++) {
- env->regs[i] = qemu_get_be32(f);
- }
- val = qemu_get_be32(f);
- /* Avoid mode switch when restoring CPSR. */
- env->uncached_cpsr = val & CPSR_M;
- cpsr_write(env, val, 0xffffffff);
- env->spsr = qemu_get_be32(f);
- for (i = 0; i < 6; i++) {
- env->banked_spsr[i] = qemu_get_be32(f);
- env->banked_r13[i] = qemu_get_be32(f);
- env->banked_r14[i] = qemu_get_be32(f);
- }
- for (i = 0; i < 5; i++) {
- env->usr_regs[i] = qemu_get_be32(f);
- env->fiq_regs[i] = qemu_get_be32(f);
- }
- env->cp15.c0_cpuid = qemu_get_be32(f);
- env->cp15.c0_cachetype = qemu_get_be32(f);
- env->cp15.c0_cssel = qemu_get_be32(f);
- env->cp15.c1_sys = qemu_get_be32(f);
- env->cp15.c1_coproc = qemu_get_be32(f);
- env->cp15.c1_xscaleauxcr = qemu_get_be32(f);
- env->cp15.c1_scr = qemu_get_be32(f);
- env->cp15.c2_base0 = qemu_get_be32(f);
- env->cp15.c2_base1 = qemu_get_be32(f);
- env->cp15.c2_control = qemu_get_be32(f);
- env->cp15.c2_mask = qemu_get_be32(f);
- env->cp15.c2_base_mask = qemu_get_be32(f);
- env->cp15.c2_data = qemu_get_be32(f);
- env->cp15.c2_insn = qemu_get_be32(f);
- env->cp15.c3 = qemu_get_be32(f);
- env->cp15.c5_insn = qemu_get_be32(f);
- env->cp15.c5_data = qemu_get_be32(f);
- for (i = 0; i < 8; i++) {
- env->cp15.c6_region[i] = qemu_get_be32(f);
- }
- env->cp15.c6_insn = qemu_get_be32(f);
- env->cp15.c6_data = qemu_get_be32(f);
- env->cp15.c7_par = qemu_get_be32(f);
- env->cp15.c9_insn = qemu_get_be32(f);
- env->cp15.c9_data = qemu_get_be32(f);
- env->cp15.c9_pmcr = qemu_get_be32(f);
- env->cp15.c9_pmcnten = qemu_get_be32(f);
- env->cp15.c9_pmovsr = qemu_get_be32(f);
- env->cp15.c9_pmxevtyper = qemu_get_be32(f);
- env->cp15.c9_pmuserenr = qemu_get_be32(f);
- env->cp15.c9_pminten = qemu_get_be32(f);
- env->cp15.c13_fcse = qemu_get_be32(f);
- env->cp15.c13_context = qemu_get_be32(f);
- env->cp15.c13_tls1 = qemu_get_be32(f);
- env->cp15.c13_tls2 = qemu_get_be32(f);
- env->cp15.c13_tls3 = qemu_get_be32(f);
- env->cp15.c15_cpar = qemu_get_be32(f);
- env->cp15.c15_power_control = qemu_get_be32(f);
- env->cp15.c15_diagnostic = qemu_get_be32(f);
- env->cp15.c15_power_diagnostic = qemu_get_be32(f);
-
- env->features = qemu_get_be32(f);
-
- if (arm_feature(env, ARM_FEATURE_VFP)) {
- for (i = 0; i < 32; i++) {
- CPU_DoubleU u;
- u.l.upper = qemu_get_be32(f);
- u.l.lower = qemu_get_be32(f);
- env->vfp.regs[i] = u.d;
- }
- for (i = 0; i < 16; i++) {
- env->vfp.xregs[i] = qemu_get_be32(f);
- }
+static const VMStateDescription vmstate_feature_m = {
+ .name = "feature_m",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(v7m.other_sp, CPUARMState),
+ VMSTATE_UINT32(v7m.vecbase, CPUARMState),
+ VMSTATE_UINT32(v7m.basepri, CPUARMState),
+ VMSTATE_UINT32(v7m.control, CPUARMState),
+ VMSTATE_INT32(v7m.current_sp, CPUARMState),
+ VMSTATE_INT32(v7m.exception, CPUARMState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static bool feature_thumb2ee_needed(void *opaque)
+{
+ CPUARMState *env = opaque;
+ return arm_feature(env, ARM_FEATURE_THUMB2EE);
+}
- /* TODO: Should use proper FPSCR access functions. */
- env->vfp.vec_len = qemu_get_be32(f);
- env->vfp.vec_stride = qemu_get_be32(f);
+static const VMStateDescription vmstate_feature_thumb2ee = {
+ .name = "feature_thumb2ee",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(teecr, CPUARMState),
+ VMSTATE_UINT32(teehbr, CPUARMState),
+ VMSTATE_END_OF_LIST()
}
+};
- if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
- for (i = 0; i < 16; i++) {
- env->iwmmxt.regs[i] = qemu_get_be64(f);
- }
- for (i = 0; i < 16; i++) {
- env->iwmmxt.cregs[i] = qemu_get_be32(f);
- }
- }
+static void cpu_pre_save(void *opaque)
+{
+ CPUARMState *env = opaque;
- if (arm_feature(env, ARM_FEATURE_M)) {
- env->v7m.other_sp = qemu_get_be32(f);
- env->v7m.vecbase = qemu_get_be32(f);
- env->v7m.basepri = qemu_get_be32(f);
- env->v7m.control = qemu_get_be32(f);
- env->v7m.current_sp = qemu_get_be32(f);
- env->v7m.exception = qemu_get_be32(f);
- }
+ env->cpsr_vmstate = cpsr_read(env);
+}
- if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
- env->teecr = qemu_get_be32(f);
- env->teehbr = qemu_get_be32(f);
- }
+static int cpu_post_load(void *opaque, int version_id)
+{
+ CPUARMState *env = opaque;
+ /* Avoid mode switch when restoring CPSR. */
+ env->uncached_cpsr = env->cpsr_vmstate & CPSR_M;
+ cpsr_write(env, env->cpsr_vmstate, 0xffffffff);
return 0;
}
+
+const VMStateDescription vmstate_cpu = {
+ .name = "cpu",
+ .version_id = 7,
+ .minimum_version_id = 7,
+ .minimum_version_id_old = 7,
+ .pre_save = cpu_pre_save,
+ .post_load = cpu_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, CPUARMState, 16),
+ VMSTATE_UINT32(cpsr_vmstate, CPUARMState),
+ VMSTATE_UINT32(spsr, CPUARMState),
+ VMSTATE_UINT32_ARRAY(banked_spsr, CPUARMState, 6),
+ VMSTATE_UINT32_ARRAY(banked_r13, CPUARMState, 6),
+ VMSTATE_UINT32_ARRAY(banked_r14, CPUARMState, 6),
+ VMSTATE_UINT32_ARRAY(usr_regs, CPUARMState, 5),
+ VMSTATE_UINT32_ARRAY(fiq_regs, CPUARMState, 5),
+ VMSTATE_UINT32(cp15.c0_cpuid, CPUARMState),
+ VMSTATE_UINT32(cp15.c0_cachetype, CPUARMState),
+ VMSTATE_UINT32(cp15.c0_cssel, CPUARMState),
+ VMSTATE_UINT32(cp15.c1_sys, CPUARMState),
+ VMSTATE_UINT32(cp15.c1_coproc, CPUARMState),
+ VMSTATE_UINT32(cp15.c1_xscaleauxcr, CPUARMState),
+ VMSTATE_UINT32(cp15.c1_scr, CPUARMState),
+ VMSTATE_UINT32(cp15.c2_base0, CPUARMState),
+ VMSTATE_UINT32(cp15.c2_base1, CPUARMState),
+ VMSTATE_UINT32(cp15.c2_control, CPUARMState),
+ VMSTATE_UINT32(cp15.c2_mask, CPUARMState),
+ VMSTATE_UINT32(cp15.c2_base_mask, CPUARMState),
+ VMSTATE_UINT32(cp15.c2_data, CPUARMState),
+ VMSTATE_UINT32(cp15.c2_insn, CPUARMState),
+ VMSTATE_UINT32(cp15.c3, CPUARMState),
+ VMSTATE_UINT32(cp15.c5_insn, CPUARMState),
+ VMSTATE_UINT32(cp15.c5_data, CPUARMState),
+ VMSTATE_UINT32_ARRAY(cp15.c6_region, CPUARMState, 8),
+ VMSTATE_UINT32(cp15.c6_insn, CPUARMState),
+ VMSTATE_UINT32(cp15.c6_data, CPUARMState),
+ VMSTATE_UINT32(cp15.c7_par, CPUARMState),
+ VMSTATE_UINT32(cp15.c9_insn, CPUARMState),
+ VMSTATE_UINT32(cp15.c9_data, CPUARMState),
+ VMSTATE_UINT32(cp15.c9_pmcr, CPUARMState),
+ VMSTATE_UINT32(cp15.c9_pmcnten, CPUARMState),
+ VMSTATE_UINT32(cp15.c9_pmovsr, CPUARMState),
+ VMSTATE_UINT32(cp15.c9_pmxevtyper, CPUARMState),
+ VMSTATE_UINT32(cp15.c9_pmuserenr, CPUARMState),
+ VMSTATE_UINT32(cp15.c9_pminten, CPUARMState),
+ VMSTATE_UINT32(cp15.c13_fcse, CPUARMState),
+ VMSTATE_UINT32(cp15.c13_context, CPUARMState),
+ VMSTATE_UINT32(cp15.c13_tls1, CPUARMState),
+ VMSTATE_UINT32(cp15.c13_tls2, CPUARMState),
+ VMSTATE_UINT32(cp15.c13_tls3, CPUARMState),
+ VMSTATE_UINT32(cp15.c15_cpar, CPUARMState),
+ VMSTATE_UINT32(cp15.c15_power_control, CPUARMState),
+ VMSTATE_UINT32(cp15.c15_diagnostic, CPUARMState),
+ VMSTATE_UINT32(cp15.c15_power_diagnostic, CPUARMState),
+ VMSTATE_UINT32(features, CPUARMState),
+ VMSTATE_END_OF_LIST()
+ },
+ .subsections = (VMStateSubsection[]) {
+ {
+ .vmsd = &vmstate_feature_vfp,
+ .needed = feature_vfp_needed,
+ } , {
+ .vmsd = &vmstate_feature_iwmmxt,
+ .needed = feature_iwmmxt_needed,
+ } , {
+ .vmsd = &vmstate_feature_m,
+ .needed = feature_m_needed,
+ } , {
+ .vmsd = &vmstate_feature_thumb2ee,
+ .needed = feature_thumb2ee_needed,
+ } , {
+ /* empty */
+ }
+ }
+};
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH 24/36] vmstate: port arm cpu
2012-03-19 22:57 ` [Qemu-devel] [PATCH 24/36] vmstate: port arm cpu Juan Quintela
@ 2012-03-21 16:29 ` Andreas Färber
2012-03-21 16:42 ` Peter Maydell
2012-03-21 17:16 ` Juan Quintela
0 siblings, 2 replies; 60+ messages in thread
From: Andreas Färber @ 2012-03-21 16:29 UTC (permalink / raw)
To: Juan Quintela; +Cc: Peter Maydell, qemu-devel, Paul Brook
Am 19.03.2012 23:57, schrieb Juan Quintela:
> Use one subsection for each feature. This means that we don't need to
> bump the version field each time that a new feature gets introduced.
>
> Introduce cpsr_vmstate field, as I am not sure if I can "use"
> uncached_cpsr for saving state.
>
> Signed-off-by: Juan Quintela <quintela@redhat.com>
As stated previously, I still think we should hold off converting the
ARM CPU to VMState until the cp15 rework by Peter takes on shape.
On another matter, had you prefixed this patch with "target-arm: "
rather than hiding that essential keyword where my mailer cuts it off,
it would be much easier to find in this series than amidst lots of
"vmstate: " patches.
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH 24/36] vmstate: port arm cpu
2012-03-21 16:29 ` Andreas Färber
@ 2012-03-21 16:42 ` Peter Maydell
2012-03-21 17:16 ` Juan Quintela
1 sibling, 0 replies; 60+ messages in thread
From: Peter Maydell @ 2012-03-21 16:42 UTC (permalink / raw)
To: Andreas Färber; +Cc: Paul Brook, qemu-devel, Juan Quintela
On 21 March 2012 16:29, Andreas Färber <afaerber@suse.de> wrote:
> Am 19.03.2012 23:57, schrieb Juan Quintela:
>> Use one subsection for each feature. This means that we don't need to
>> bump the version field each time that a new feature gets introduced.
>>
>> Introduce cpsr_vmstate field, as I am not sure if I can "use"
>> uncached_cpsr for saving state.
You could, I guess, but you'd need a 'post-save' hook to reset the
bits not stored in uncached_cpsr normally, and it's a bit ugly.
On the other hand having a field in CPUARMState just for save
load is also pretty ugly.
VMState should support a way to mark a migration state field as
"not actually stored in a field in the struct, use these functions
to save and load it", and we should use that.
> As stated previously, I still think we should hold off converting the
> ARM CPU to VMState until the cp15 rework by Peter takes on shape.
I don't think this code actually clashes with what I've done so
far, and I think switching to a lot of separate subsections is
probably a step in the right direction even if the details might
not be quite what they'll end up eventually. So I don't think
we need to block it until the cp15 stuff lands. (Plus I know I've
been taking forever on cp15 so I feel bad about blocking other
peoples' patches on it.)
-- PMM
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH 24/36] vmstate: port arm cpu
2012-03-21 16:29 ` Andreas Färber
2012-03-21 16:42 ` Peter Maydell
@ 2012-03-21 17:16 ` Juan Quintela
1 sibling, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-21 17:16 UTC (permalink / raw)
To: Andreas Färber; +Cc: Peter Maydell, qemu-devel, Paul Brook
Andreas Färber <afaerber@suse.de> wrote:
> Am 19.03.2012 23:57, schrieb Juan Quintela:
>> Use one subsection for each feature. This means that we don't need to
>> bump the version field each time that a new feature gets introduced.
>>
>> Introduce cpsr_vmstate field, as I am not sure if I can "use"
>> uncached_cpsr for saving state.
>>
>> Signed-off-by: Juan Quintela <quintela@redhat.com>
>
> As stated previously, I still think we should hold off converting the
> ARM CPU to VMState until the cp15 rework by Peter takes on shape.
This converts all cpus to vmstate. Conversion of cp15 is indiferent of
vmstate. Basically we will need to send something like one array of
pairs: [(register_id, value)], and have some validation before we
receive it.
Notice that something like that is also needed for x86 MSR's, just now
we are sending them ad-hoc, but it would be great to do something like:
- notice what msr's have been read/write by guest
- just send that msr's.
- maintain backwards compatibility is going to be a mess, but that don't
affect arm at this moment.
I guess that cp15 registers have some similar meaning (they are
optional, and not all of them have been touched by the guest). But I
still haven't a good idea on how to handle it.
> On another matter, had you prefixed this patch with "target-arm: "
> rather than hiding that essential keyword where my mailer cuts it off,
> it would be much easier to find in this series than amidst lots of
> "vmstate: " patches.
clearly, we need: keywords in each patch, in the gmail sense. one patch
can be related to several subsystems. general topic here was vmstate,
but I fully agree that if I had used target-foo: as starting it would
have been as good (just for a different definition of good).
Thanks, Juan.
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH 25/36] vmstate: all cpus converted
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (23 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 24/36] vmstate: port arm cpu Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 26/36] vmstate: fix vmstate formating for i386 Juan Quintela
` (11 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
We don't have any more CPU_SAVEVM_VERSION users, neither
cpu_save/load() ones.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
exec.c | 5 -----
qemu-common.h | 4 ----
2 files changed, 0 insertions(+), 9 deletions(-)
diff --git a/exec.c b/exec.c
index c0f9c2e..bb6474c 100644
--- a/exec.c
+++ b/exec.c
@@ -726,13 +726,8 @@ void cpu_exec_init(CPUArchState *env)
#endif
#if !defined(CONFIG_USER_ONLY)
vmstate_register(NULL, cpu_index, &vmstate_cpu_common, env);
-#if defined(CPU_SAVE_VERSION)
- register_savevm(NULL, "cpu", cpu_index, CPU_SAVE_VERSION,
- cpu_save, cpu_load, env);
-#else
vmstate_register(NULL, cpu_index, &vmstate_cpu, env);
#endif
-#endif
}
/* Allocate a new translation block. Flush the translation buffer if
diff --git a/qemu-common.h b/qemu-common.h
index c9e96a8..004b3ab 100644
--- a/qemu-common.h
+++ b/qemu-common.h
@@ -275,10 +275,6 @@ bool tcg_enabled(void);
void cpu_exec_init_all(void);
-/* CPU save/load. */
-void cpu_save(QEMUFile *f, void *opaque);
-int cpu_load(QEMUFile *f, void *opaque, int version_id);
-
/* Unblock cpu */
void qemu_cpu_kick(void *env);
void qemu_cpu_kick_self(void);
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 26/36] vmstate: fix vmstate formating for i386
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (24 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 25/36] vmstate: all cpus converted Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 27/36] vmstate: remove unneeded includes from target-*/machine.c Juan Quintela
` (10 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-i386/machine.c | 16 ++++++++--------
1 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target-i386/machine.c b/target-i386/machine.c
index 127c44f..c2a8872 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -11,7 +11,7 @@ static const VMStateDescription vmstate_segment = {
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
- .fields = (VMStateField []) {
+ .fields = (VMStateField[]) {
VMSTATE_UINT32(selector, SegmentCache),
VMSTATE_UINTTL(base, SegmentCache),
VMSTATE_UINT32(limit, SegmentCache),
@@ -37,7 +37,7 @@ static const VMStateDescription vmstate_xmm_reg = {
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
- .fields = (VMStateField []) {
+ .fields = (VMStateField[]) {
VMSTATE_UINT64(XMM_Q(0), XMMReg),
VMSTATE_UINT64(XMM_Q(1), XMMReg),
VMSTATE_END_OF_LIST()
@@ -53,7 +53,7 @@ static const VMStateDescription vmstate_ymmh_reg = {
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
- .fields = (VMStateField []) {
+ .fields = (VMStateField[]) {
VMSTATE_UINT64(XMM_Q(0), XMMReg),
VMSTATE_UINT64(XMM_Q(1), XMMReg),
VMSTATE_END_OF_LIST()
@@ -68,7 +68,7 @@ static const VMStateDescription vmstate_mtrr_var = {
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
- .fields = (VMStateField []) {
+ .fields = (VMStateField[]) {
VMSTATE_UINT64(base, MTRRVar),
VMSTATE_UINT64(mask, MTRRVar),
VMSTATE_END_OF_LIST()
@@ -284,7 +284,7 @@ static const VMStateDescription vmstate_async_pf_msr = {
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
- .fields = (VMStateField []) {
+ .fields = (VMStateField []) {
VMSTATE_UINT64(async_pf_en_msr, CPUX86State),
VMSTATE_END_OF_LIST()
}
@@ -302,7 +302,7 @@ static const VMStateDescription vmstate_fpop_ip_dp = {
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
- .fields = (VMStateField []) {
+ .fields = (VMStateField []) {
VMSTATE_UINT16(fpop, CPUX86State),
VMSTATE_UINT64(fpip, CPUX86State),
VMSTATE_UINT64(fpdp, CPUX86State),
@@ -353,7 +353,7 @@ const VMStateDescription vmstate_cpu = {
.minimum_version_id_old = 3,
.pre_save = cpu_pre_save,
.post_load = cpu_post_load,
- .fields = (VMStateField []) {
+ .fields = (VMStateField []) {
VMSTATE_UINTTL_ARRAY(regs, CPUX86State, CPU_NB_REGS),
VMSTATE_UINTTL(eip, CPUX86State),
VMSTATE_UINTTL(eflags, CPUX86State),
@@ -449,7 +449,7 @@ const VMStateDescription vmstate_cpu = {
VMSTATE_END_OF_LIST()
/* The above list is not sorted /wrt version numbers, watch out! */
},
- .subsections = (VMStateSubsection []) {
+ .subsections = (VMStateSubsection[]) {
{
.vmsd = &vmstate_async_pf_msr,
.needed = async_pf_msr_needed,
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 27/36] vmstate: remove unneeded includes from target-*/machine.c
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (25 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 26/36] vmstate: fix vmstate formating for i386 Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 28/36] vmstate: rename machine.c to vmstate-cpu.c Juan Quintela
` (9 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-alpha/machine.c | 1 -
target-arm/machine.c | 1 -
target-cris/machine.c | 1 -
target-i386/machine.c | 6 ------
target-lm32/machine.c | 1 -
target-mips/machine.c | 3 ---
target-ppc/machine.c | 2 --
target-sparc/machine.c | 4 ----
8 files changed, 0 insertions(+), 19 deletions(-)
diff --git a/target-alpha/machine.c b/target-alpha/machine.c
index 8b3b42e..22c70f3 100644
--- a/target-alpha/machine.c
+++ b/target-alpha/machine.c
@@ -1,5 +1,4 @@
#include "hw/hw.h"
-#include "hw/boards.h"
static int get_fpcr(QEMUFile *f, void *opaque, size_t size)
{
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 31e49ac..f8ccdd7 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -1,5 +1,4 @@
#include "hw/hw.h"
-#include "hw/boards.h"
static bool feature_vfp_needed(void *opaque)
{
diff --git a/target-cris/machine.c b/target-cris/machine.c
index 1b96265..1dbf8b5 100644
--- a/target-cris/machine.c
+++ b/target-cris/machine.c
@@ -1,5 +1,4 @@
#include "hw/hw.h"
-#include "hw/boards.h"
static const VMStateDescription vmstate_tlbset = {
.name = "cpu/tlbset",
diff --git a/target-i386/machine.c b/target-i386/machine.c
index c2a8872..0ef12ac 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -1,10 +1,4 @@
#include "hw/hw.h"
-#include "hw/boards.h"
-#include "hw/pc.h"
-#include "hw/isa.h"
-
-#include "cpu.h"
-#include "kvm.h"
static const VMStateDescription vmstate_segment = {
.name = "segment",
diff --git a/target-lm32/machine.c b/target-lm32/machine.c
index 24db6c0..132259d 100644
--- a/target-lm32/machine.c
+++ b/target-lm32/machine.c
@@ -1,5 +1,4 @@
#include "hw/hw.h"
-#include "hw/boards.h"
const VMStateDescription vmstate_cpu = {
.name = "cpu",
diff --git a/target-mips/machine.c b/target-mips/machine.c
index 8951748..bbfa2a9 100644
--- a/target-mips/machine.c
+++ b/target-mips/machine.c
@@ -1,7 +1,4 @@
#include "hw/hw.h"
-#include "hw/boards.h"
-
-#include "cpu.h"
static const VMStateDescription vmstate_tc = {
.name = "tc",
diff --git a/target-ppc/machine.c b/target-ppc/machine.c
index ca60bc0..c4547df 100644
--- a/target-ppc/machine.c
+++ b/target-ppc/machine.c
@@ -1,6 +1,4 @@
#include "hw/hw.h"
-#include "hw/boards.h"
-#include "kvm.h"
static const VMStateDescription vmstate_tlb = {
.name = "tlb",
diff --git a/target-sparc/machine.c b/target-sparc/machine.c
index 818b11c..b599ac7 100644
--- a/target-sparc/machine.c
+++ b/target-sparc/machine.c
@@ -1,8 +1,4 @@
#include "hw/hw.h"
-#include "hw/boards.h"
-#include "qemu-timer.h"
-
-#include "cpu.h"
static const VMStateDescription vmstate_cpu_timer = {
.name = "cpu_timer",
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 28/36] vmstate: rename machine.c to vmstate-cpu.c
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (26 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 27/36] vmstate: remove unneeded includes from target-*/machine.c Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-22 12:42 ` Andreas Färber
2012-03-19 22:57 ` [Qemu-devel] [PATCH 29/36] vmstate: Add copyright info for alpha processor Juan Quintela
` (8 subsequent siblings)
36 siblings, 1 reply; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
They only contain vmstate cpu sections nowadays. Change name to reflect the case.
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
Makefile.target | 3 ++-
target-alpha/{machine.c => vmstate-cpu.c} | 0
target-arm/{machine.c => vmstate-cpu.c} | 0
target-cris/{machine.c => vmstate-cpu.c} | 0
target-i386/{machine.c => vmstate-cpu.c} | 0
target-lm32/{machine.c => vmstate-cpu.c} | 0
target-m68k/{machine.c => vmstate-cpu.c} | 0
target-microblaze/{machine.c => vmstate-cpu.c} | 0
target-mips/{machine.c => vmstate-cpu.c} | 0
target-ppc/{machine.c => vmstate-cpu.c} | 0
target-s390x/{machine.c => vmstate-cpu.c} | 0
target-sh4/{machine.c => vmstate-cpu.c} | 0
target-sparc/{machine.c => vmstate-cpu.c} | 0
target-xtensa/{machine.c => vmstate-cpu.c} | 0
14 files changed, 2 insertions(+), 1 deletions(-)
rename target-alpha/{machine.c => vmstate-cpu.c} (100%)
rename target-arm/{machine.c => vmstate-cpu.c} (100%)
rename target-cris/{machine.c => vmstate-cpu.c} (100%)
rename target-i386/{machine.c => vmstate-cpu.c} (100%)
rename target-lm32/{machine.c => vmstate-cpu.c} (100%)
rename target-m68k/{machine.c => vmstate-cpu.c} (100%)
rename target-microblaze/{machine.c => vmstate-cpu.c} (100%)
rename target-mips/{machine.c => vmstate-cpu.c} (100%)
rename target-ppc/{machine.c => vmstate-cpu.c} (100%)
rename target-s390x/{machine.c => vmstate-cpu.c} (100%)
rename target-sh4/{machine.c => vmstate-cpu.c} (100%)
rename target-sparc/{machine.c => vmstate-cpu.c} (100%)
rename target-xtensa/{machine.c => vmstate-cpu.c} (100%)
diff --git a/Makefile.target b/Makefile.target
index 63cf769..0f59106 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -204,7 +204,8 @@ endif #CONFIG_BSD_USER
# System emulator target
ifdef CONFIG_SOFTMMU
-obj-y = arch_init.o cpus.o monitor.o machine.o gdbstub.o balloon.o ioport.o
+obj-y = arch_init.o cpus.o monitor.o vmstate-cpu.o gdbstub.o balloon.o
+obj-y += ioport.o
# virtio has to be here due to weird dependency between PCI and virtio-net.
# need to fix this properly
obj-$(CONFIG_NO_PCI) += pci-stub.o
diff --git a/target-alpha/machine.c b/target-alpha/vmstate-cpu.c
similarity index 100%
rename from target-alpha/machine.c
rename to target-alpha/vmstate-cpu.c
diff --git a/target-arm/machine.c b/target-arm/vmstate-cpu.c
similarity index 100%
rename from target-arm/machine.c
rename to target-arm/vmstate-cpu.c
diff --git a/target-cris/machine.c b/target-cris/vmstate-cpu.c
similarity index 100%
rename from target-cris/machine.c
rename to target-cris/vmstate-cpu.c
diff --git a/target-i386/machine.c b/target-i386/vmstate-cpu.c
similarity index 100%
rename from target-i386/machine.c
rename to target-i386/vmstate-cpu.c
diff --git a/target-lm32/machine.c b/target-lm32/vmstate-cpu.c
similarity index 100%
rename from target-lm32/machine.c
rename to target-lm32/vmstate-cpu.c
diff --git a/target-m68k/machine.c b/target-m68k/vmstate-cpu.c
similarity index 100%
rename from target-m68k/machine.c
rename to target-m68k/vmstate-cpu.c
diff --git a/target-microblaze/machine.c b/target-microblaze/vmstate-cpu.c
similarity index 100%
rename from target-microblaze/machine.c
rename to target-microblaze/vmstate-cpu.c
diff --git a/target-mips/machine.c b/target-mips/vmstate-cpu.c
similarity index 100%
rename from target-mips/machine.c
rename to target-mips/vmstate-cpu.c
diff --git a/target-ppc/machine.c b/target-ppc/vmstate-cpu.c
similarity index 100%
rename from target-ppc/machine.c
rename to target-ppc/vmstate-cpu.c
diff --git a/target-s390x/machine.c b/target-s390x/vmstate-cpu.c
similarity index 100%
rename from target-s390x/machine.c
rename to target-s390x/vmstate-cpu.c
diff --git a/target-sh4/machine.c b/target-sh4/vmstate-cpu.c
similarity index 100%
rename from target-sh4/machine.c
rename to target-sh4/vmstate-cpu.c
diff --git a/target-sparc/machine.c b/target-sparc/vmstate-cpu.c
similarity index 100%
rename from target-sparc/machine.c
rename to target-sparc/vmstate-cpu.c
diff --git a/target-xtensa/machine.c b/target-xtensa/vmstate-cpu.c
similarity index 100%
rename from target-xtensa/machine.c
rename to target-xtensa/vmstate-cpu.c
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH 28/36] vmstate: rename machine.c to vmstate-cpu.c
2012-03-19 22:57 ` [Qemu-devel] [PATCH 28/36] vmstate: rename machine.c to vmstate-cpu.c Juan Quintela
@ 2012-03-22 12:42 ` Andreas Färber
2012-03-22 13:13 ` Juan Quintela
0 siblings, 1 reply; 60+ messages in thread
From: Andreas Färber @ 2012-03-22 12:42 UTC (permalink / raw)
To: Juan Quintela; +Cc: qemu-devel
Am 19.03.2012 23:57, schrieb Juan Quintela:
> They only contain vmstate cpu sections nowadays. Change name to reflect the case.
In light of me creating a file cpu.c for every target except ppc, might
it make more sense to call it cpu-vmstate.c? Or do you envision other
vmstate-*.c files?
Andreas
>
> Signed-off-by: Juan Quintela <quintela@redhat.com>
> ---
> Makefile.target | 3 ++-
> target-alpha/{machine.c => vmstate-cpu.c} | 0
> target-arm/{machine.c => vmstate-cpu.c} | 0
> target-cris/{machine.c => vmstate-cpu.c} | 0
> target-i386/{machine.c => vmstate-cpu.c} | 0
> target-lm32/{machine.c => vmstate-cpu.c} | 0
> target-m68k/{machine.c => vmstate-cpu.c} | 0
> target-microblaze/{machine.c => vmstate-cpu.c} | 0
> target-mips/{machine.c => vmstate-cpu.c} | 0
> target-ppc/{machine.c => vmstate-cpu.c} | 0
> target-s390x/{machine.c => vmstate-cpu.c} | 0
> target-sh4/{machine.c => vmstate-cpu.c} | 0
> target-sparc/{machine.c => vmstate-cpu.c} | 0
> target-xtensa/{machine.c => vmstate-cpu.c} | 0
> 14 files changed, 2 insertions(+), 1 deletions(-)
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH 28/36] vmstate: rename machine.c to vmstate-cpu.c
2012-03-22 12:42 ` Andreas Färber
@ 2012-03-22 13:13 ` Juan Quintela
0 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-22 13:13 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
Andreas Färber <afaerber@suse.de> wrote:
> Am 19.03.2012 23:57, schrieb Juan Quintela:
>> They only contain vmstate cpu sections nowadays. Change name to
>> reflect the case.
>
> In light of me creating a file cpu.c for every target except ppc, might
> it make more sense to call it cpu-vmstate.c? Or do you envision other
> vmstate-*.c files?
I renamed them pecause they don't contain the boards definitions
anymore. Will move next round to cpu-vmstate.c, I don't really care
about the name.
Later, Juan.
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Qemu-devel] [PATCH 29/36] vmstate: Add copyright info for alpha processor
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (27 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 28/36] vmstate: rename machine.c to vmstate-cpu.c Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 30/36] vmstate: Add copyright info for lm32 processor Juan Quintela
` (7 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
Acked-by: Richard Henderson <rth@twiddle.net>
---
target-alpha/vmstate-cpu.c | 15 +++++++++++++++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/target-alpha/vmstate-cpu.c b/target-alpha/vmstate-cpu.c
index 22c70f3..b94b1e5 100644
--- a/target-alpha/vmstate-cpu.c
+++ b/target-alpha/vmstate-cpu.c
@@ -1,3 +1,18 @@
+/*
+ * Migration support for alpha cpus
+ *
+ * Copyright (C) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ * Juan Quintela <quintela@redhat.com>
+ *
+ * Based on savevm serialization code by:
+ * Richard Henderson <rth@twiddle.net>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later. See the COPYING file in the top-level directory.
+ */
+
#include "hw/hw.h"
static int get_fpcr(QEMUFile *f, void *opaque, size_t size)
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 30/36] vmstate: Add copyright info for lm32 processor
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (28 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 29/36] vmstate: Add copyright info for alpha processor Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:57 ` [Qemu-devel] [PATCH 31/36] vmstate: Add copyright info for cris processor Juan Quintela
` (6 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
Acked-By: Michael Walle <michael@walle.cc>
---
target-lm32/vmstate-cpu.c | 15 +++++++++++++++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/target-lm32/vmstate-cpu.c b/target-lm32/vmstate-cpu.c
index 132259d..3867189 100644
--- a/target-lm32/vmstate-cpu.c
+++ b/target-lm32/vmstate-cpu.c
@@ -1,3 +1,18 @@
+/*
+ * Migration support for lm32 cpus
+ *
+ * Copyright (C) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ * Juan Quintela <quintela@redhat.com>
+ *
+ * Based on savevm serialization code by:
+ * Michael Walle <michael@walle.cc>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later. See the COPYING file in the top-level directory.
+ */
+
#include "hw/hw.h"
const VMStateDescription vmstate_cpu = {
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 31/36] vmstate: Add copyright info for cris processor
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (29 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 30/36] vmstate: Add copyright info for lm32 processor Juan Quintela
@ 2012-03-19 22:57 ` Juan Quintela
2012-03-19 22:58 ` [Qemu-devel] [PATCH 32/36] vmstate: Add copyright info for arm processor Juan Quintela
` (5 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:57 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
---
target-cris/vmstate-cpu.c | 15 +++++++++++++++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/target-cris/vmstate-cpu.c b/target-cris/vmstate-cpu.c
index 1dbf8b5..47ac170 100644
--- a/target-cris/vmstate-cpu.c
+++ b/target-cris/vmstate-cpu.c
@@ -1,3 +1,18 @@
+/*
+ * Migration support for cris cpus
+ *
+ * Copyright (C) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ * Juan Quintela <quintela@redhat.com>
+ *
+ * Based on savevm serialization code by:
+ * Edgar E. Iglesias <edgar.iglesias@gmail.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later. See the COPYING file in the top-level directory.
+ */
+
#include "hw/hw.h"
static const VMStateDescription vmstate_tlbset = {
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 32/36] vmstate: Add copyright info for arm processor
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (30 preceding siblings ...)
2012-03-19 22:57 ` [Qemu-devel] [PATCH 31/36] vmstate: Add copyright info for cris processor Juan Quintela
@ 2012-03-19 22:58 ` Juan Quintela
2012-03-19 22:58 ` [Qemu-devel] [PATCH 33/36] vmstate: Add copyright info for i386 processor Juan Quintela
` (4 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:58 UTC (permalink / raw)
To: qemu-devel
Signed-off-by: Juan Quintela <quintela@redhat.com>
Acked-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
---
target-arm/vmstate-cpu.c | 15 +++++++++++++++
1 files changed, 15 insertions(+), 0 deletions(-)
diff --git a/target-arm/vmstate-cpu.c b/target-arm/vmstate-cpu.c
index f8ccdd7..65ed6eb 100644
--- a/target-arm/vmstate-cpu.c
+++ b/target-arm/vmstate-cpu.c
@@ -1,3 +1,18 @@
+/*
+ * Migration support for arm cpus
+ *
+ * Copyright (C) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ * Juan Quintela <quintela@redhat.com>
+ *
+ * Based on savevm serialization code by:
+ * Andrzej Zaborowski <andrew.zaborowski@intel.com>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * later. See the COPYING file in the top-level directory.
+ */
+
#include "hw/hw.h"
static bool feature_vfp_needed(void *opaque)
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 33/36] vmstate: Add copyright info for i386 processor
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (31 preceding siblings ...)
2012-03-19 22:58 ` [Qemu-devel] [PATCH 32/36] vmstate: Add copyright info for arm processor Juan Quintela
@ 2012-03-19 22:58 ` Juan Quintela
2012-03-19 22:58 ` [Qemu-devel] [PATCH 34/36] vmstate: Add copyright info for mips processor Juan Quintela
` (3 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:58 UTC (permalink / raw)
To: qemu-devel
v2: Move license to BSD-like as in vl.c
Add Fabrice copyright from vl.c
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-i386/vmstate-cpu.c | 28 ++++++++++++++++++++++++++++
1 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/target-i386/vmstate-cpu.c b/target-i386/vmstate-cpu.c
index 0ef12ac..3a321e4 100644
--- a/target-i386/vmstate-cpu.c
+++ b/target-i386/vmstate-cpu.c
@@ -1,3 +1,31 @@
+/*
+ * Migration support for x86 cpu
+ *
+ * Copyright (c) 2003-2008 Fabrice Bellard
+ * Copyright (c) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ * Juan Quintela <quintela@redhat.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
#include "hw/hw.h"
static const VMStateDescription vmstate_segment = {
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 34/36] vmstate: Add copyright info for mips processor
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (32 preceding siblings ...)
2012-03-19 22:58 ` [Qemu-devel] [PATCH 33/36] vmstate: Add copyright info for i386 processor Juan Quintela
@ 2012-03-19 22:58 ` Juan Quintela
2012-03-19 22:58 ` [Qemu-devel] [PATCH 35/36] vmstate: Add copyright info for ppc processor Juan Quintela
` (2 subsequent siblings)
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:58 UTC (permalink / raw)
To: qemu-devel
v2: Move license to BSD-like as in vl.c
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-mips/vmstate-cpu.c | 29 +++++++++++++++++++++++++++++
1 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/target-mips/vmstate-cpu.c b/target-mips/vmstate-cpu.c
index bbfa2a9..1e28b3f 100644
--- a/target-mips/vmstate-cpu.c
+++ b/target-mips/vmstate-cpu.c
@@ -1,3 +1,32 @@
+/*
+ * Migration support for mips cpu
+ *
+ * Copyright (c) 2003-2008 Fabrice Bellard
+ * Copyright (c) 2003-2008 Thiemo Seufer
+ * Copyright (c) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ * Juan Quintela <quintela@redhat.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
#include "hw/hw.h"
static const VMStateDescription vmstate_tc = {
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 35/36] vmstate: Add copyright info for ppc processor
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (33 preceding siblings ...)
2012-03-19 22:58 ` [Qemu-devel] [PATCH 34/36] vmstate: Add copyright info for mips processor Juan Quintela
@ 2012-03-19 22:58 ` Juan Quintela
2012-03-19 22:58 ` [Qemu-devel] [PATCH 36/36] vmstate: Add copyright info for sparc processor Juan Quintela
2012-03-21 17:13 ` [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Andreas Färber
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:58 UTC (permalink / raw)
To: qemu-devel
v2: Move license to BSD-like as in vl.c
v3: change copyright dates
v4: add Fabrice & QEMU contributors
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-ppc/vmstate-cpu.c | 30 ++++++++++++++++++++++++++++++
1 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/target-ppc/vmstate-cpu.c b/target-ppc/vmstate-cpu.c
index c4547df..3fa6750 100644
--- a/target-ppc/vmstate-cpu.c
+++ b/target-ppc/vmstate-cpu.c
@@ -1,3 +1,33 @@
+/*
+ * Migration support for ppc cpu
+ *
+ * Copyright (c) 2003-2008 Fabrice Bellard
+ * Copyright (c) 2004-2009 Blue Swirl <blauwirbel@gmail.com>
+ * Copyright (c) 2003-2012 QEMU contributors
+ * Copyright (c) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ * Juan Quintela <quintela@redhat.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
#include "hw/hw.h"
static const VMStateDescription vmstate_tlb = {
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Qemu-devel] [PATCH 36/36] vmstate: Add copyright info for sparc processor
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (34 preceding siblings ...)
2012-03-19 22:58 ` [Qemu-devel] [PATCH 35/36] vmstate: Add copyright info for ppc processor Juan Quintela
@ 2012-03-19 22:58 ` Juan Quintela
2012-03-21 17:13 ` [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Andreas Färber
36 siblings, 0 replies; 60+ messages in thread
From: Juan Quintela @ 2012-03-19 22:58 UTC (permalink / raw)
To: qemu-devel
v2: Move license to BSD-like as in vl.c
v3: Change copyright dates
v4: add QEMU contributors
Signed-off-by: Juan Quintela <quintela@redhat.com>
---
target-sparc/vmstate-cpu.c | 30 ++++++++++++++++++++++++++++++
1 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/target-sparc/vmstate-cpu.c b/target-sparc/vmstate-cpu.c
index b599ac7..0d19e6a 100644
--- a/target-sparc/vmstate-cpu.c
+++ b/target-sparc/vmstate-cpu.c
@@ -1,3 +1,33 @@
+/*
+ * Migration support for sparc cpu
+ *
+ * Copyright (c) 2003-2008 Fabrice Bellard
+ * Copyright (c) 2004-2011 Blue Swirl <blauwirbel@gmail.com>
+ * Copyright (c) 2003-2012 QEMU contributors
+ * Copyright (c) 2011 Red Hat, Inc.
+ *
+ * Author(s):
+ * Juan Quintela <quintela@redhat.com>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
#include "hw/hw.h"
static const VMStateDescription vmstate_cpu_timer = {
--
1.7.7.6
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus
2012-03-19 22:57 [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Juan Quintela
` (35 preceding siblings ...)
2012-03-19 22:58 ` [Qemu-devel] [PATCH 36/36] vmstate: Add copyright info for sparc processor Juan Quintela
@ 2012-03-21 17:13 ` Andreas Färber
2012-03-21 17:24 ` Juan Quintela
36 siblings, 1 reply; 60+ messages in thread
From: Andreas Färber @ 2012-03-21 17:13 UTC (permalink / raw)
To: Juan Quintela; +Cc: qemu-devel
Am 19.03.2012 23:57, schrieb Juan Quintela:
> This repository contains all the changes:
>
> git://repo.or.cz/qemu/quintela.git vmstate-cpus-v4
>
> [v4]
> - rebase to top
> - adapt to vmstate.h change
> - adapt to CPUState -> CPU$archState rename
> - integrate arm changes in the meantime
> - add QEMU contributors to the copyright notice of ppc & sparc
>
> [v3]
> - rebase to top
> - fix sparc/arm/i386 changes in upstream
> - all reviews were positive, Anthony, please pull
>
> [v2] Changes since v1
>
> - preserve arm comment that was missing (pbrook)
> - add copyright notice to the files that were empty
> - new patches:
> * fix formating for i386
> * remove unneeded includes
> * rename machine.c to vmstate.c
>
> Later, Juan.
>
> [v1]
>
> This series port all cpus to use vmstate.
> - 1st patch is a fix of vmstate.
> - I discussed the arm changes over irc with Peter, he agreed that some
> simplification could be good, but he didn't saw the patches O:-)
> - mips: no pci chipset has been ported, so migration don't work there.
> I have embedded a couple of structs to improve vmstate checking. Notice
> that they were always allocated, so there shouldn't be any problem.
> - sparc: I changed the format a little bit to be able to use normal arrays.
> - sparc: If we always send the whole register windows, we don't need
> VMSTATE_VARRAY_MULTIPLY. As that array is quite big (520 elements), I am not
> sure what is best.
> - cpsr_vmstate on arm: I am not sure if I could "abuse" uncached_cpsr for that
> purpose?
>
> I have only tested on x86, for the rest, I double checked, but it is
> possible that I missed something. I expect all patches to be
> integrated by Anthony in one go. Architecture maintainers are CC'd
> for an ACK/NACK/comments.
>
> Please, review.
>
> PD. Is there an easy way of creating this "CC" list of mail addresses,
> or the only way is to edit comments and write it by hand as I did?
Actually I don't see any CCs at all in this series. Which makes me think
this is v1 rubbish in the new cover letter. :/
--cc-cmd="scripts/get_maintainer.pl --nogit-fallback" should work.
A general comment:
With regards to the ongoing CPU QOM'ification, if we ever arrive in a
scenario where we can have multiple targets in one machine, I guess the
VMState .name "cpu" would cause problems? In that case it might be
better to use the proposed QOM type names, i.e. "arm-cpu", etc. from the
start.
Andreas
>
> Juan Quintela (36):
> vmstate: Simplify test for CPU_SAVE_VERSION
> vmstate: make all architectures export a way to migrate cpu's
> vmstate: unicore32 don't support cpu migration
> vmstate: use new cpu style for x86
> vmstate: use new style for lm32 cpus
> vmstate: make microblaze cpus not migrateable
> vmstate: port cris cpu to vmstate
> vmstate: machine.c is only compiled for !CONFIG_USER_ONLY
> vmstate: introduce float32 arrays
> vmstate: introduce float64 arrays
> vmstate: introduce CPU_DoubleU arrays
> vmstate: Introduce VMSTATE_STRUCT_VARRAY_INT32_TEST
> vmstate: port ppc cpu
> vmstate: introduce VMSTATE_VARRAY_MULTIPLY
> vmstate: define vmstate_info_uinttls
> vmstate: port sparc cpu
> vmstate: make incompatible change for sparc
> mips_fulong2e: cpu vmstate already registered in cpu_exec_init
> mips: make mvp an embedded struct instead of a pointer
> mips: make tlb an embedded struct instead of a pointer
> mips: bump migration version to 4
> vmstate: port mips cpu
> arm: save always 32 fpu registers
> vmstate: port arm cpu
> vmstate: all cpus converted
> vmstate: fix vmstate formating for i386
> vmstate: remove unneeded includes from target-*/machine.c
> vmstate: rename machine.c to vmstate-cpu.c
> vmstate: Add copyright info for alpha processor
> vmstate: Add copyright info for lm32 processor
> vmstate: Add copyright info for cris processor
> vmstate: Add copyright info for arm processor
> vmstate: Add copyright info for i386 processor
> vmstate: Add copyright info for mips processor
> vmstate: Add copyright info for ppc processor
> vmstate: Add copyright info for sparc processor
>
> Makefile.target | 3 +-
> exec.c | 7 +-
> hw/hw.h | 2 +
> hw/mips_fulong2e.c | 1 -
> hw/mips_malta.c | 4 +-
> hw/mips_timer.c | 2 +-
> hw/sun4u.c | 20 --
> qemu-common.h | 4 -
> savevm.c | 90 ++++++++
> target-alpha/{machine.c => vmstate-cpu.c} | 28 ++-
> target-arm/cpu.h | 5 +-
> target-arm/machine.c | 233 ---------------------
> target-arm/vmstate-cpu.c | 191 +++++++++++++++++
> target-cris/cpu.h | 13 +-
> target-cris/machine.c | 90 --------
> target-cris/vmstate-cpu.c | 74 +++++++
> target-i386/cpu.h | 2 -
> target-i386/{machine.c => vmstate-cpu.c} | 64 ++++---
> target-lm32/cpu.h | 2 -
> target-lm32/{machine.c => vmstate-cpu.c} | 32 ++--
> target-m68k/vmstate-cpu.c | 21 ++
> target-microblaze/cpu.h | 2 -
> target-microblaze/machine.c | 11 -
> target-microblaze/vmstate-cpu.c | 21 ++
> target-mips/cpu.h | 11 +-
> target-mips/helper.c | 30 ++-
> target-mips/machine.c | 308 ----------------------------
> target-mips/op_helper.c | 70 ++++---
> target-mips/translate.c | 22 ++-
> target-mips/translate_init.c | 36 ++--
> target-mips/vmstate-cpu.c | 225 ++++++++++++++++++++
> target-ppc/cpu.h | 5 +-
> target-ppc/machine.c | 181 ----------------
> target-ppc/vmstate-cpu.c | 130 ++++++++++++
> target-s390x/{machine.c => vmstate-cpu.c} | 14 +-
> target-sh4/vmstate-cpu.c | 21 ++
> target-sparc/cpu.h | 9 +-
> target-sparc/machine.c | 217 -------------------
> target-sparc/vmstate-cpu.c | 175 ++++++++++++++++
> target-unicore32/cpu.h | 2 -
> target-xtensa/{machine.c => vmstate-cpu.c} | 14 +-
> vmstate.h | 60 +++++-
> 42 files changed, 1195 insertions(+), 1257 deletions(-)
> rename target-alpha/{machine.c => vmstate-cpu.c} (85%)
> delete mode 100644 target-arm/machine.c
> create mode 100644 target-arm/vmstate-cpu.c
> delete mode 100644 target-cris/machine.c
> create mode 100644 target-cris/vmstate-cpu.c
> rename target-i386/{machine.c => vmstate-cpu.c} (89%)
> rename target-lm32/{machine.c => vmstate-cpu.c} (58%)
> delete mode 100644 target-m68k/machine.c
> create mode 100644 target-m68k/vmstate-cpu.c
> delete mode 100644 target-microblaze/machine.c
> create mode 100644 target-microblaze/vmstate-cpu.c
> delete mode 100644 target-mips/machine.c
> create mode 100644 target-mips/vmstate-cpu.c
> delete mode 100644 target-ppc/machine.c
> create mode 100644 target-ppc/vmstate-cpu.c
> rename target-s390x/{machine.c => vmstate-cpu.c} (79%)
> delete mode 100644 target-sh4/machine.c
> create mode 100644 target-sh4/vmstate-cpu.c
> delete mode 100644 target-sparc/machine.c
> create mode 100644 target-sparc/vmstate-cpu.c
> rename target-xtensa/{machine.c => vmstate-cpu.c} (88%)
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus
2012-03-21 17:13 ` [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus Andreas Färber
@ 2012-03-21 17:24 ` Juan Quintela
2012-03-21 18:43 ` Andreas Färber
0 siblings, 1 reply; 60+ messages in thread
From: Juan Quintela @ 2012-03-21 17:24 UTC (permalink / raw)
To: Andreas Färber; +Cc: qemu-devel
Andreas Färber <afaerber@suse.de> wrote:
> Am 19.03.2012 23:57, schrieb Juan Quintela:
>> This repository contains all the changes:
>>
>> git://repo.or.cz/qemu/quintela.git vmstate-cpus-v4
>>
>> [v4]
>> - rebase to top
>> - adapt to vmstate.h change
>> - adapt to CPUState -> CPU$archState rename
>> - integrate arm changes in the meantime
>> - add QEMU contributors to the copyright notice of ppc & sparc
[...]
>
> Actually I don't see any CCs at all in this series. Which makes me think
> this is v1 rubbish in the new cover letter. :/
see the changelog for v4. All patches were already reviewed, only
changes were: copyright stuff that Blaw didn't liked (and he was cc'd),
and rebasing (move of stuff from hw/hw.h to vmstate.h and
s/CPUState/CPU$archState/).
Idea here was not to resend to everybody that already reviewed the
patches another copy.
>
> --cc-cmd="scripts/get_maintainer.pl --nogit-fallback" should work.
nice trick.
> A general comment:
> With regards to the ongoing CPU QOM'ification, if we ever arrive in a
> scenario where we can have multiple targets in one machine, I guess the
> VMState .name "cpu" would cause problems? In that case it might be
> better to use the proposed QOM type names, i.e. "arm-cpu", etc. from the
> start.
At least for x86 we need to maintain backward compatibility. For the
cest of architectures, we can change it after this series. It is more,
it would be better to have: "sparc32-cpu" and "sparc64-cpu", so we
could be able to read the vmstate section without more external info.
I would preffer to do this changes after this series goes in.
[note to all, I am sending a v5 with the changes suggested yesterday by
peter on float32/64 handling ]
Thanks, Juan.
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/36] VMState port of all cpus
2012-03-21 17:24 ` Juan Quintela
@ 2012-03-21 18:43 ` Andreas Färber
0 siblings, 0 replies; 60+ messages in thread
From: Andreas Färber @ 2012-03-21 18:43 UTC (permalink / raw)
To: quintela; +Cc: qemu-devel
Am 21.03.2012 18:24, schrieb Juan Quintela:
> Andreas Färber <afaerber@suse.de> wrote:
>> Am 19.03.2012 23:57, schrieb Juan Quintela:
>>> This repository contains all the changes:
>>>
>>> git://repo.or.cz/qemu/quintela.git vmstate-cpus-v4
>>>
>>> [v4]
>>> - rebase to top
>>> - adapt to vmstate.h change
>>> - adapt to CPUState -> CPU$archState rename
>>> - integrate arm changes in the meantime
>>> - add QEMU contributors to the copyright notice of ppc & sparc
>
> [...]
>>
>> Actually I don't see any CCs at all in this series. Which makes me think
>> this is v1 rubbish in the new cover letter. :/
>
> see the changelog for v4. All patches were already reviewed, only
There's no tags on the patches though, which equals unreviewed.
Especially I see no indication that Alex ack'ed ppc and s390x - do you
have links of where he did?
> changes were: copyright stuff that Blaw didn't liked (and he was cc'd),
> and rebasing (move of stuff from hw/hw.h to vmstate.h and
> s/CPUState/CPU$archState/).
>
> Idea here was not to resend to everybody that already reviewed the
> patches another copy.
My point was: Please remember to update the cover letter. In this case,
if no one is cc'ed, don't write they are (in the part you snipped above)
just because they were previously. Has nothing to do with what changes
you actually did in v4 and whether they should be cc'ed again (I'd
expect to be).
>> --cc-cmd="scripts/get_maintainer.pl --nogit-fallback" should work.
>
> nice trick.
sendemail.cccmd (no dash) is even handier long-term. :)
>> With regards to the ongoing CPU QOM'ification, if we ever arrive in a
>> scenario where we can have multiple targets in one machine, I guess the
>> VMState .name "cpu" would cause problems? In that case it might be
>> better to use the proposed QOM type names, i.e. "arm-cpu", etc. from the
>> start.
>
> At least for x86 we need to maintain backward compatibility. For the
> cest of architectures, we can change it after this series. It is more,
> it would be better to have: "sparc32-cpu" and "sparc64-cpu", so we
> could be able to read the vmstate section without more external info.
>
> I would preffer to do this changes after this series goes in.
It's unclear to me where that field is being used - is it being written
into the stream and does changing it mean a breakage of the format? Or
is this just for debugging?
If the former, then I think sparc32-cpu vs. sparc64-cpu is just candy
since I don't believe we'll manage to combine 32- and 64-bit CPUs
anytime soon.
My understanding was that this conversion series would generally
preserve the format and allow interoperability where no target-specific
changes are performed. Am I wrong if that only applies to x86 now?
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 60+ messages in thread