From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:54821) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SCh2W-0002yw-K4 for qemu-devel@nongnu.org; Tue, 27 Mar 2012 20:47:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SCh2U-0002lA-PX for qemu-devel@nongnu.org; Tue, 27 Mar 2012 20:47:04 -0400 Date: Wed, 28 Mar 2012 11:45:05 +1100 From: David Gibson Message-ID: <20120328004505.GD9582@truffala.fritz.box> References: <1332862915-27501-1-git-send-email-mark.cave-ayland@ilande.co.uk> <1332862915-27501-3-git-send-email-mark.cave-ayland@ilande.co.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1332862915-27501-3-git-send-email-mark.cave-ayland@ilande.co.uk> Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 2/2] PPC: Fix TLB invalidation bug within the PPC interrupt handler. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mark Cave-Ayland Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org On Tue, Mar 27, 2012 at 04:41:55PM +0100, Mark Cave-Ayland wrote: > Commit 41557447d30eeb944e42069513df13585f5e6c7f also introduced a subtle TLB > flush bug. By applying a mask to the interrupt MSR which cleared the IR/DR > bits at the start of the interrupt handler, the logic towards the end of the > handler to force a TLB flush if either one of these bits were set would never > be triggered. > > This patch simply changes the IR/DR bit check in the TLB flush logic to use > the original MSR value (albeit with some interrupt-specific bits cleared) so > that the IR/DR bits are preserved at the point where the check takes place. > > Signed-off-by: Mark Cave-Ayland Acked-by: David Gibson -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson