From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:35099) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SUrjs-0007rf-VT for qemu-devel@nongnu.org; Wed, 16 May 2012 23:50:58 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1SUrjq-0002GJ-NF for qemu-devel@nongnu.org; Wed, 16 May 2012 23:50:56 -0400 Received: from ozlabs.org ([203.10.76.45]:35822) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1SUrjq-0002EX-BE for qemu-devel@nongnu.org; Wed, 16 May 2012 23:50:54 -0400 Date: Thu, 17 May 2012 13:35:20 +1000 From: David Gibson Message-ID: <20120517033520.GD22069@truffala.fritz.box> References: <1336625347-10169-1-git-send-email-benh@kernel.crashing.org> <1336625347-10169-14-git-send-email-benh@kernel.crashing.org> <4FB1A8BF.7060503@codemonkey.ws> <20120515014449.GF30229@truffala.fritz.box> <1337142938.6727.122.camel@pasglop> <4FB4028F.7070003@codemonkey.ws> <1337213257.30558.22.camel@pasglop> <1337214293.30558.25.camel@pasglop> <1337215928.30558.28.camel@pasglop> <4FB46257.3060706@codemonkey.ws> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4FB46257.3060706@codemonkey.ws> Subject: Re: [Qemu-devel] [RFC/PATCH] Add a memory barrier to guest memory access functions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: qemu-devel@nongnu.org, "Michael S. Tsirkin" On Wed, May 16, 2012 at 09:28:39PM -0500, Anthony Liguori wrote: > On 05/16/2012 07:52 PM, Benjamin Herrenschmidt wrote: [snip] > >@@ -2794,6 +2795,9 @@ void *qemu_get_ram_ptr(ram_addr_t addr) > > { > > RAMBlock *block; > > > >+ /* We ensure ordering for all DMA transactions */ > >+ dma_mb(); > >+ > > I get being conservative, but I don't think this makes a lot of > sense. There are cases where the return of this function is cached > (like the VGA ram area). I think it would make more sense if you > explicitly put a barrier after write operations. I tend to agree. I think the barriers should be in cpu_physical_memory_rw() and the st*_phys() functions. -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson