* [Qemu-devel] [RFC PATCH V1 0/2] Microblaze CPU model v8.30 updates @ 2012-05-17 5:37 Peter A. G. Crosthwaite 2012-05-17 5:37 ` [Qemu-devel] [RFC PATCH V1 1/2] target-microblaze: impelemented swapx instructions Peter A. G. Crosthwaite 2012-05-17 5:37 ` [Qemu-devel] [RFC PATCH V1 2/2] target-microblaze: lwx/swx: first implementation Peter A. G. Crosthwaite 0 siblings, 2 replies; 5+ messages in thread From: Peter A. G. Crosthwaite @ 2012-05-17 5:37 UTC (permalink / raw) To: qemu-devel, edgar.iglesias Cc: peter.crosthwaite, david.holsgrove, john.williams Microblaze CPU v8.30 has some new instructions that are implemented in this instructions are: swapb, swaph (PATCH 1) lwx, swx (PATCH 2) Peter A. G. Crosthwaite (2): target-microblaze: impelemented swapx instructions target-microblaze: lwx/swx: first implementation target-microblaze/cpu.h | 1 + target-microblaze/helper.c | 2 + target-microblaze/translate.c | 63 ++++++++++++++++++++++++++++++++++++++-- 3 files changed, 62 insertions(+), 4 deletions(-) -- 1.7.3.2 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [Qemu-devel] [RFC PATCH V1 1/2] target-microblaze: impelemented swapx instructions 2012-05-17 5:37 [Qemu-devel] [RFC PATCH V1 0/2] Microblaze CPU model v8.30 updates Peter A. G. Crosthwaite @ 2012-05-17 5:37 ` Peter A. G. Crosthwaite 2012-05-18 10:21 ` Edgar E. Iglesias 2012-05-17 5:37 ` [Qemu-devel] [RFC PATCH V1 2/2] target-microblaze: lwx/swx: first implementation Peter A. G. Crosthwaite 1 sibling, 1 reply; 5+ messages in thread From: Peter A. G. Crosthwaite @ 2012-05-17 5:37 UTC (permalink / raw) To: qemu-devel, edgar.iglesias Cc: peter.crosthwaite, david.holsgrove, john.williams Implemented the swapb and swaph byte/halfword reversal instructions added to microblaze v8.30 Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> --- target-microblaze/translate.c | 12 +++++++++++- 1 files changed, 11 insertions(+), 1 deletions(-) diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 742b395..a362938 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -743,7 +743,7 @@ static void dec_bit(DisasContext *dc) unsigned int op; int mem_index = cpu_mmu_index(dc->env); - op = dc->ir & ((1 << 8) - 1); + op = dc->ir & ((1 << 9) - 1); switch (op) { case 0x21: /* src. */ @@ -825,6 +825,16 @@ static void dec_bit(DisasContext *dc) gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]); } break; + case 0x1e0: + /* swapb */ + LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra); + tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]); + break; + case 0x1e1: + /*swaph */ + LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra); + tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16); + break; default: cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", dc->pc, op, dc->rd, dc->ra, dc->rb); -- 1.7.3.2 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [RFC PATCH V1 1/2] target-microblaze: impelemented swapx instructions 2012-05-17 5:37 ` [Qemu-devel] [RFC PATCH V1 1/2] target-microblaze: impelemented swapx instructions Peter A. G. Crosthwaite @ 2012-05-18 10:21 ` Edgar E. Iglesias 0 siblings, 0 replies; 5+ messages in thread From: Edgar E. Iglesias @ 2012-05-18 10:21 UTC (permalink / raw) To: Peter A. G. Crosthwaite; +Cc: david.holsgrove, qemu-devel, john.williams On Thu, May 17, 2012 at 03:37:49PM +1000, Peter A. G. Crosthwaite wrote: > Implemented the swapb and swaph byte/halfword reversal instructions added > to microblaze v8.30 > > Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Applied, thanks Peter > --- > target-microblaze/translate.c | 12 +++++++++++- > 1 files changed, 11 insertions(+), 1 deletions(-) > > diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c > index 742b395..a362938 100644 > --- a/target-microblaze/translate.c > +++ b/target-microblaze/translate.c > @@ -743,7 +743,7 @@ static void dec_bit(DisasContext *dc) > unsigned int op; > int mem_index = cpu_mmu_index(dc->env); > > - op = dc->ir & ((1 << 8) - 1); > + op = dc->ir & ((1 << 9) - 1); > switch (op) { > case 0x21: > /* src. */ > @@ -825,6 +825,16 @@ static void dec_bit(DisasContext *dc) > gen_helper_clz(cpu_R[dc->rd], cpu_R[dc->ra]); > } > break; > + case 0x1e0: > + /* swapb */ > + LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra); > + tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]); > + break; > + case 0x1e1: > + /*swaph */ > + LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra); > + tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16); > + break; > default: > cpu_abort(dc->env, "unknown bit oc=%x op=%x rd=%d ra=%d rb=%d\n", > dc->pc, op, dc->rd, dc->ra, dc->rb); > -- > 1.7.3.2 > ^ permalink raw reply [flat|nested] 5+ messages in thread
* [Qemu-devel] [RFC PATCH V1 2/2] target-microblaze: lwx/swx: first implementation 2012-05-17 5:37 [Qemu-devel] [RFC PATCH V1 0/2] Microblaze CPU model v8.30 updates Peter A. G. Crosthwaite 2012-05-17 5:37 ` [Qemu-devel] [RFC PATCH V1 1/2] target-microblaze: impelemented swapx instructions Peter A. G. Crosthwaite @ 2012-05-17 5:37 ` Peter A. G. Crosthwaite 2012-05-18 10:36 ` Edgar E. Iglesias 1 sibling, 1 reply; 5+ messages in thread From: Peter A. G. Crosthwaite @ 2012-05-17 5:37 UTC (permalink / raw) To: qemu-devel, edgar.iglesias Cc: peter.crosthwaite, david.holsgrove, john.williams Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> --- target-microblaze/cpu.h | 1 + target-microblaze/helper.c | 2 + target-microblaze/translate.c | 51 ++++++++++++++++++++++++++++++++++++++-- 3 files changed, 51 insertions(+), 3 deletions(-) diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 718d5bb..775a16d 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -250,6 +250,7 @@ struct CPUMBState { #define DRTE_FLAG (1 << 17) #define DRTB_FLAG (1 << 18) #define D_FLAG (1 << 19) /* Bit in ESR. */ +#define R_FLAG (1 << 24) /* Reservation Bit */ /* TB dependent CPUMBState. */ #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) uint32_t iflags; diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index 2412a58..235f1be 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -29,6 +29,7 @@ void do_interrupt (CPUMBState *env) { env->exception_index = -1; + env->iflags &= ~R_FLAG; env->regs[14] = env->sregs[SR_PC]; } @@ -116,6 +117,7 @@ void do_interrupt(CPUMBState *env) assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG))); assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); /* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */ + env->iflags &= ~R_FLAG; switch (env->exception_index) { case EXCP_HW_EXCP: if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) { diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index a362938..9c1a0b5 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -948,12 +948,13 @@ static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size) static void dec_load(DisasContext *dc) { TCGv t, *addr; - unsigned int size, rev = 0; + unsigned int size, rev = 0, ex = 0; size = 1 << (dc->opcode & 3); if (!dc->type_b) { rev = (dc->ir >> 9) & 1; + ex = (dc->ir >> 10) & 1; } if (size > 4 && (dc->tb_flags & MSR_EE_FLAG) @@ -1019,6 +1020,17 @@ static void dec_load(DisasContext *dc) } } + /* lwx does not throw unaligned access errors, so force alignment */ + if (ex) { + /* Force addr into the temp. */ + if (addr != &t) { + t = tcg_temp_new(); + tcg_gen_mov_tl(t, *addr); + addr = &t; + } + tcg_gen_andi_tl(t, t, ~3); + } + /* If we get a fault on a dslot, the jmpstate better be in sync. */ sync_jmpstate(dc); @@ -1057,6 +1069,13 @@ static void dec_load(DisasContext *dc) } } + if (ex) { /* lwx */ + /* no support for for AXI exlusive so always clear C */ + TCGv_i32 zero = tcg_const_i32(0); + write_carry(dc, zero); + dc->tb_flags |= R_FLAG; + } + if (addr == &t) tcg_temp_free(t); } @@ -1078,12 +1097,14 @@ static void gen_store(DisasContext *dc, TCGv addr, TCGv val, static void dec_store(DisasContext *dc) { - TCGv t, *addr; - unsigned int size, rev = 0; + TCGv t, *addr, swx_carry = 0; + int swx_skip; + unsigned int size, rev = 0, ex = 0; size = 1 << (dc->opcode & 3); if (!dc->type_b) { rev = (dc->ir >> 9) & 1; + ex = (dc->ir >> 10) & 1; } if (size > 4 && (dc->tb_flags & MSR_EE_FLAG) @@ -1099,6 +1120,26 @@ static void dec_store(DisasContext *dc) sync_jmpstate(dc); addr = compute_ldst_addr(dc, &t); + if (ex) { /* swx */ + TCGv r_check = tcg_temp_new(); + swx_carry = tcg_temp_new(); + swx_skip = gen_new_label(); + + tcg_gen_andi_tl(r_check, env_iflags, R_FLAG); + tcg_gen_movi_tl(swx_carry, 1); + tcg_gen_brcondi_tl(TCG_COND_NE, r_check, R_FLAG, swx_skip); + tcg_gen_movi_tl(swx_carry, 0); + + /* Force addr into the temp. */ + if (addr != &t) { + t = tcg_temp_new(); + tcg_gen_mov_tl(t, *addr); + addr = &t; + } + /* swx does not throw unaligned access errors, so force alignment */ + tcg_gen_andi_tl(t, t, ~3); + } + if (rev && size != 4) { /* Endian reverse the address. t is addr. */ switch (size) { @@ -1174,6 +1215,10 @@ static void dec_store(DisasContext *dc) gen_helper_memalign(*addr, tcg_const_tl(dc->rd), tcg_const_tl(1), tcg_const_tl(size - 1)); } + if (ex) { + gen_set_label(swx_skip); + write_carry(dc, swx_carry); + } if (addr == &t) tcg_temp_free(t); -- 1.7.3.2 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [Qemu-devel] [RFC PATCH V1 2/2] target-microblaze: lwx/swx: first implementation 2012-05-17 5:37 ` [Qemu-devel] [RFC PATCH V1 2/2] target-microblaze: lwx/swx: first implementation Peter A. G. Crosthwaite @ 2012-05-18 10:36 ` Edgar E. Iglesias 0 siblings, 0 replies; 5+ messages in thread From: Edgar E. Iglesias @ 2012-05-18 10:36 UTC (permalink / raw) To: Peter A. G. Crosthwaite; +Cc: david.holsgrove, qemu-devel, john.williams On Thu, May 17, 2012 at 03:37:50PM +1000, Peter A. G. Crosthwaite wrote: > Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> > --- > target-microblaze/cpu.h | 1 + > target-microblaze/helper.c | 2 + > target-microblaze/translate.c | 51 ++++++++++++++++++++++++++++++++++++++-- > 3 files changed, 51 insertions(+), 3 deletions(-) > > diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h > index 718d5bb..775a16d 100644 > --- a/target-microblaze/cpu.h > +++ b/target-microblaze/cpu.h > @@ -250,6 +250,7 @@ struct CPUMBState { > #define DRTE_FLAG (1 << 17) > #define DRTB_FLAG (1 << 18) > #define D_FLAG (1 << 19) /* Bit in ESR. */ > +#define R_FLAG (1 << 24) /* Reservation Bit */ > /* TB dependent CPUMBState. */ > #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG) > uint32_t iflags; > diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c > index 2412a58..235f1be 100644 > --- a/target-microblaze/helper.c > +++ b/target-microblaze/helper.c > @@ -29,6 +29,7 @@ > void do_interrupt (CPUMBState *env) > { > env->exception_index = -1; > + env->iflags &= ~R_FLAG; > env->regs[14] = env->sregs[SR_PC]; > } > > @@ -116,6 +117,7 @@ void do_interrupt(CPUMBState *env) > assert(!((env->iflags & D_FLAG) && (env->iflags & IMM_FLAG))); > assert(!(env->iflags & (DRTI_FLAG | DRTE_FLAG | DRTB_FLAG))); > /* assert(env->sregs[SR_MSR] & (MSR_EE)); Only for HW exceptions. */ > + env->iflags &= ~R_FLAG; > switch (env->exception_index) { > case EXCP_HW_EXCP: > if (!(env->pvr.regs[0] & PVR0_USE_EXC_MASK)) { > diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c > index a362938..9c1a0b5 100644 > --- a/target-microblaze/translate.c > +++ b/target-microblaze/translate.c > @@ -948,12 +948,13 @@ static inline void dec_byteswap(DisasContext *dc, TCGv dst, TCGv src, int size) > static void dec_load(DisasContext *dc) > { > TCGv t, *addr; > - unsigned int size, rev = 0; > + unsigned int size, rev = 0, ex = 0; > > size = 1 << (dc->opcode & 3); > > if (!dc->type_b) { > rev = (dc->ir >> 9) & 1; > + ex = (dc->ir >> 10) & 1; > } > > if (size > 4 && (dc->tb_flags & MSR_EE_FLAG) > @@ -1019,6 +1020,17 @@ static void dec_load(DisasContext *dc) > } > } > > + /* lwx does not throw unaligned access errors, so force alignment */ > + if (ex) { > + /* Force addr into the temp. */ > + if (addr != &t) { > + t = tcg_temp_new(); > + tcg_gen_mov_tl(t, *addr); > + addr = &t; > + } > + tcg_gen_andi_tl(t, t, ~3); > + } > + > /* If we get a fault on a dslot, the jmpstate better be in sync. */ > sync_jmpstate(dc); > > @@ -1057,6 +1069,13 @@ static void dec_load(DisasContext *dc) > } > } > > + if (ex) { /* lwx */ > + /* no support for for AXI exlusive so always clear C */ > + TCGv_i32 zero = tcg_const_i32(0); > + write_carry(dc, zero); > + dc->tb_flags |= R_FLAG; Here, instead of touching tb_flags you need to emit code that sets the flag at execution time. > + } > + > if (addr == &t) > tcg_temp_free(t); > } > @@ -1078,12 +1097,14 @@ static void gen_store(DisasContext *dc, TCGv addr, TCGv val, > > static void dec_store(DisasContext *dc) > { > - TCGv t, *addr; > - unsigned int size, rev = 0; > + TCGv t, *addr, swx_carry = 0; > + int swx_skip; > + unsigned int size, rev = 0, ex = 0; > > size = 1 << (dc->opcode & 3); > if (!dc->type_b) { > rev = (dc->ir >> 9) & 1; > + ex = (dc->ir >> 10) & 1; > } > > if (size > 4 && (dc->tb_flags & MSR_EE_FLAG) > @@ -1099,6 +1120,26 @@ static void dec_store(DisasContext *dc) > sync_jmpstate(dc); > addr = compute_ldst_addr(dc, &t); > > + if (ex) { /* swx */ > + TCGv r_check = tcg_temp_new(); > + swx_carry = tcg_temp_new(); > + swx_skip = gen_new_label(); > + > + tcg_gen_andi_tl(r_check, env_iflags, R_FLAG); > + tcg_gen_movi_tl(swx_carry, 1); > + tcg_gen_brcondi_tl(TCG_COND_NE, r_check, R_FLAG, swx_skip); > + tcg_gen_movi_tl(swx_carry, 0); > + > + /* Force addr into the temp. */ > + if (addr != &t) { > + t = tcg_temp_new(); > + tcg_gen_mov_tl(t, *addr); > + addr = &t; > + } > + /* swx does not throw unaligned access errors, so force alignment */ > + tcg_gen_andi_tl(t, t, ~3); > + } > + > if (rev && size != 4) { > /* Endian reverse the address. t is addr. */ > switch (size) { > @@ -1174,6 +1215,10 @@ static void dec_store(DisasContext *dc) > gen_helper_memalign(*addr, tcg_const_tl(dc->rd), > tcg_const_tl(1), tcg_const_tl(size - 1)); > } > + if (ex) { > + gen_set_label(swx_skip); > + write_carry(dc, swx_carry); > + } > > if (addr == &t) > tcg_temp_free(t); > -- > 1.7.3.2 > ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2012-05-18 10:37 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2012-05-17 5:37 [Qemu-devel] [RFC PATCH V1 0/2] Microblaze CPU model v8.30 updates Peter A. G. Crosthwaite 2012-05-17 5:37 ` [Qemu-devel] [RFC PATCH V1 1/2] target-microblaze: impelemented swapx instructions Peter A. G. Crosthwaite 2012-05-18 10:21 ` Edgar E. Iglesias 2012-05-17 5:37 ` [Qemu-devel] [RFC PATCH V1 2/2] target-microblaze: lwx/swx: first implementation Peter A. G. Crosthwaite 2012-05-18 10:36 ` Edgar E. Iglesias
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