[Qemu-devel] r4k doesn't support movz

[Qemu-devel] r4k doesn't support movz

[Zhi-zhou Zhang]

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Hi Aurelien,

I found that when qemu-system-mips64el executed 'movz' with -M mips, it
would raise a reserved instruction exception.
The mips spec describes movz as below:

Mnemonic               Instructio                      Defined in MIPS ISA
MOVZ            Move Conditional on Zero       MIPS32

I think ISA-64 should support MIPS32 instructions for compatible. am I
right?

-- 
Regards,
Zhizhou Zhang

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Re: [Qemu-devel] r4k doesn't support movz

[Johnson, Eric]

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Hi Zhi-zhou Zhang,

You are correct.  This should not be a reserved instruction exception on MIPS64 (nor should MOVN).

-Eric

From: qemu-devel-bounces+ericj=mips.com@nongnu.org [mailto:qemu-devel-bounces+ericj=mips.com@nongnu.org] On Behalf Of Zhi-zhou Zhang
Sent: Friday, May 18, 2012 4:39 AM
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net
Subject: [Qemu-devel] r4k doesn't support movz

Hi Aurelien,

I found that when qemu-system-mips64el executed 'movz' with -M mips, it would raise a reserved instruction exception.
The mips spec describes movz as below:

Mnemonic               Instructio                      Defined in MIPS ISA
MOVZ            Move Conditional on Zero       MIPS32

I think ISA-64 should support MIPS32 instructions for compatible. am I right?

--
Regards,
Zhizhou Zhang


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Re: [Qemu-devel] r4k doesn't support movz

[Jia Liu]

Hi Eric&Zhang,

Nope, you two are wrong. Aurelien is right.
Let me show you the code.

1, qemu/hw/mips_r4k.c --    for    qemu-system-mips4el -M mips    board.
void mips_r4k_init (...)
{
...
    /* init CPUs */
    if (cpu_model == NULL) {
#ifdef TARGET_MIPS64
        cpu_model = "R4000";
#else
        cpu_model = "24Kf";
#endif
    }
...
}

OK, we all see the CPU is R4000 when we config qemu to MIPS64.

2, http://en.wikipedia.org/wiki/R4000
The R4000 is a microprocessor developed by MIPS Computer Systems that
implemented the MIPS III instruction set architecture (ISA).
Officially announced on 1 October 1991

3, qemu/target-mips/translate_init.c
#if defined(TARGET_MIPS64)
    {
        .name = "R4000",
...
        .insn_flags = CPU_MIPS3,
...
    },

we can see R400 has MIPS3 insns.

4, qemu/target-mips/mips_defs.h
#define		ISA_MIPS3	0x00000004
#define		ISA_MIPS4	0x00000008

#define		CPU_MIPS3	(CPU_MIPS2 | ISA_MIPS3)
#define		CPU_MIPS4	(CPU_MIPS3 | ISA_MIPS4)

we can see it, CPU_MIPS4 holds ISA_MIPS4 and all CPU_MIPS3 insns,
but CPU_MIPS3 doesn't hold ISA_MIPS4 insns.

5, qemu/target-mips/translate.c
        case OPC_MOVN:         /* Conditional move */
        case OPC_MOVZ:
            check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32 |
                                 INSN_LOONGSON2E | INSN_LOONGSON2F);
Here is NO MIPS3 support, that is R4000 does NOT support Conditional moves.



If this is not enough, all right, let check binutils file.

binutils/opcodes/mips-opc.c
#define I3	INSN_ISA3
#define I4	INSN_ISA4

{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,
	0,		I4_32|IL2E|IL2F	},

So, we all see it. movz is not a MIPS3/R4000 instruction.



Regards,
Jia.

On Sat, May 19, 2012 at 9:02 AM, Johnson, Eric <ericj@mips.com> wrote:
> Hi Zhi-zhou Zhang,
>
>
>
> You are correct.  This should not be a reserved instruction exception on
> MIPS64 (nor should MOVN).
>
>
>
> -Eric
>
>
>
> From: qemu-devel-bounces+ericj=mips.com@nongnu.org
> [mailto:qemu-devel-bounces+ericj=mips.com@nongnu.org] On Behalf Of Zhi-zhou
> Zhang
> Sent: Friday, May 18, 2012 4:39 AM
> To: qemu-devel@nongnu.org
> Cc: aurelien@aurel32.net
> Subject: [Qemu-devel] r4k doesn't support movz
>
>
>
> Hi Aurelien,
>
>
>
> I found that when qemu-system-mips64el executed 'movz' with -M mips, it
> would raise a reserved instruction exception.
>
> The mips spec describes movz as below:
>
>
>
> Mnemonic               Instructio                      Defined in MIPS ISA
>
> MOVZ            Move Conditional on Zero       MIPS32
>
>
>
> I think ISA-64 should support MIPS32 instructions for compatible. am I
> right?
>
>
>
> --
> Regards,
>
> Zhizhou Zhang
>
>

Re: [Qemu-devel] r4k doesn't support movz

[Aurelien Jarno]

On Fri, May 18, 2012 at 07:38:39PM +0800, Zhi-zhou Zhang wrote:
> Hi Aurelien,
> 
> I found that when qemu-system-mips64el executed 'movz' with -M mips, it
> would raise a reserved instruction exception.
> The mips spec describes movz as below:
> 
> Mnemonic               Instructio                      Defined in MIPS ISA
> MOVZ            Move Conditional on Zero       MIPS32
> 
> I think ISA-64 should support MIPS32 instructions for compatible. am I
> right?
> 

MIPS64 does support MIPS32 instructions. That said, the default CPU of 
the mips machine with qemu-system-mips64el is an R4000 CPU which doesn't
support this instruction.

You should try for example with a 5Kc, 5Kf or 20Kc CPU.

-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

[Qemu-devel] r4k doesn't support movz

[Hervé Poussineau]

Hi,

Zhi-zhou Zhang a écrit :
> I found that when qemu-system-mips64el executed 'movz' with -M mips, 
> it would raise a reserved instruction exception.
> The mips spec describes movz as below:
>
> Mnemonic               Instructio                      Defined in MIPS ISA
> MOVZ            Move Conditional on Zero       MIPS32
>
> I think ISA-64 should support MIPS32 instructions for compatible. am I 
> right?

movz instruction is available on MIPS4 and MIPS32 instruction sets (+ 
Loongson2E/2F CPUs)
However, by default, 'mips' machine on qemu-system-mips64el uses a R4000 
CPU, which is only MIPS3 compatible.
You need to use another cpu which is MIPS4 or MIPS32 compatible with the 
-cpu option.

Regards,

Hervé