From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([208.118.235.92]:58681)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <Paul_Brook@mentor.com>) id 1Sbif5-0001Sj-UU
	for qemu-devel@nongnu.org; Mon, 04 Jun 2012 21:34:21 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <Paul_Brook@mentor.com>) id 1Sbif4-00024E-0c
	for qemu-devel@nongnu.org; Mon, 04 Jun 2012 21:34:19 -0400
Received: from relay1.mentorg.com ([192.94.38.131]:49835)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <Paul_Brook@mentor.com>) id 1Sbif3-00023i-Qx
	for qemu-devel@nongnu.org; Mon, 04 Jun 2012 21:34:17 -0400
From: Paul Brook <paul@codesourcery.com>
Date: Tue, 5 Jun 2012 02:34:08 +0100
References: <cover.1338796049.git.peter.crosthwaite@petalogix.com>
In-Reply-To: <cover.1338796049.git.peter.crosthwaite@petalogix.com>
MIME-Version: 1.0
Content-Type: Text/Plain;
  charset="iso-8859-6"
Content-Transfer-Encoding: 7bit
Message-Id: <201206050234.09903.paul@codesourcery.com>
Subject: Re: [Qemu-devel] [PATCH V4 0/5] Ehnahced SSI bus support + M25P80
	SPI flash + Xilinx SPI controller
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: "Peter A. G. Crosthwaite" <peter.crosthwaite@petalogix.com>
Cc: stefanha@gmail.com, edgar.iglesias@gmail.com, qemu-devel@nongnu.org, john.williams@petalogix.com, peter.maydell@linaro.org

> Patch 1 Enhances SSI bus support to properly support multiple attached
> devices. An api is provided for SSI/SPI masters to select a particular
> device attached to the bus.
> 
> Patch 2 is a device model for the m25p80 style SPI flash chip.
> 
> Patch 3 is  the Xilinx XPS SPI contoller. Its a sysbus device that
> instantiates a ssi bus, and interfaces the two (as per the controllers
> functionality)
> 
> Patch 4 instantiates the XPS SPI controller in the petalogix ML605
> reference platform and connects two m25p80s to it.
> 
> Patch 5 updates the stellaris machine model to use the multi slave SSI
> support

I'm still not convinced modelling this as a multipoint bus is a good idea.  If 
nothing else you've failed to model the case where multiple slaves are 
selected simultanously.  Given the chip selects are actual wires, not part of 
the bus itself, I think multiple point-point busses are a better fit.

For the stellaris device we still have the synthetic mux device and 
intermediate bus.


Paul