From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:34177) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ScG8c-0007vB-1f for qemu-devel@nongnu.org; Wed, 06 Jun 2012 09:19:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ScG8a-0003r5-Bi for qemu-devel@nongnu.org; Wed, 06 Jun 2012 09:19:01 -0400 Received: from relay1.mentorg.com ([192.94.38.131]:54064) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ScG8a-0003qo-5f for qemu-devel@nongnu.org; Wed, 06 Jun 2012 09:19:00 -0400 From: Paul Brook Date: Wed, 6 Jun 2012 14:18:52 +0100 References: <201206050234.09903.paul@codesourcery.com> In-Reply-To: MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201206061418.53159.paul@codesourcery.com> Subject: Re: [Qemu-devel] [PATCH V4 0/5] Ehnahced SSI bus support + M25P80 SPI flash + Xilinx SPI controller List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: John Williams Cc: "Peter A. G. Crosthwaite" , edgar.iglesias@gmail.com, stefanha@gmail.com, qemu-devel@nongnu.org, peter.maydell@linaro.org > On 5th April, when we first RFC'd our SPI layer support, you said to Peter: > > == > I don't believe there is any difference between SSI and SPI. It's the > exact same thing - the same way that many devices support a "two-wire > interface" that is actually just I2C with a different name. > > The behavior of the CS pin varies between devices. It sounds like you need > a bit of extra logic not present in the current ssi code. You should fix > that, not invent a whole new bus. > == > > He's gone and done exactly that, indeed generalised it with the > proposed changes to SSI. No. There are two changes. Modelling the CS line in the SPI bus, and having SSI be a multipoint bus rather than point-point. Paul