Re: [Qemu-devel] [PATCH 0/3] xilinx: Speed up the build

["Edgar E. Iglesias" <edgar.iglesias@gmail.com>]

On Sat, Jun 09, 2012 at 03:54:28AM +0200, Andreas Färber wrote:
> Hello Edgar and Peter,
> 
> With the Makefile refactoring applied now, here's the Makefile improvements
> for MicroBlaze I mentioned.
> 
> All Xilinx devices that are used for more than one softmmu are compiled once
> in libhw32. Actually some also in libhw64 due to ppc440 being compiled into
> ppc64, but we can fix that in a second step via Alex' ppc-next, we're already
> down from thrice to twice.
> 
> The middle patch is extracted from Blue's logging refactoring.
> 
> Please test and apply. Your s3adp1800 and virtel_ml507 test images complain
> both with and without patches about not finding "eth0". Selftest completes ok
> except for not finding /usr/bin/sha1test on ppc440.

Thanks, I'll give these a try next week!

> 
> xilinx_ethlite.c uses tswap32(). Have you ever tested this device to work on
> microblazeel? I wonder if we could change the device from DEVICE_NATIVE_ENDIAN
> to DEVICE_BIG_ENDIAN and in place of tswap32() use a bswap32() conditional on
> HOST_WORDS_BIGENDIAN so that it becomes independent of the target, too?

I don't think that will work. the swap is needed if the endianness of the host
is different from the one of the target...

IIRC, the issue is that the device has a built-in RAM mapped so close to
the regs that they end up in the same "page". With Avis memory-api maybe it's
possible to expose this sub-page area as a memory?

Cheers