From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:41970) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Se6ys-0007fe-LZ for qemu-devel@nongnu.org; Mon, 11 Jun 2012 11:56:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Se6yq-0002Y3-Tv for qemu-devel@nongnu.org; Mon, 11 Jun 2012 11:56:38 -0400 Received: from mail-bk0-f45.google.com ([209.85.214.45]:42029) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Se6yq-0002XP-KL for qemu-devel@nongnu.org; Mon, 11 Jun 2012 11:56:36 -0400 Received: by bkwj10 with SMTP id j10so4013876bkw.4 for ; Mon, 11 Jun 2012 08:56:34 -0700 (PDT) Date: Mon, 11 Jun 2012 17:56:28 +0200 From: "Edgar E. Iglesias" Message-ID: <20120611155628.GC5062@zapo> References: <4FD208F6.3020307@codemonkey.ws> <4FD5EF75.7060707@us.ibm.com> <20120611143803.GA29685@edde.se.axis.com> <4FD608DC.30301@codemonkey.ws> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4FD608DC.30301@codemonkey.ws> Subject: Re: [Qemu-devel] [RFC] QOMification of AXI stream List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: Peter Maydell , Anthony Liguori , Michal Simek , "qemu-devel@nongnu.org Developers" , Peter Crosthwaite , Paul Brook , Andreas =?iso-8859-1?Q?F=E4rber?= , John Williams On Mon, Jun 11, 2012 at 10:03:56AM -0500, Anthony Liguori wrote: > On 06/11/2012 09:53 AM, Peter Maydell wrote: > >On 11 June 2012 15:38, Edgar E. Iglesias wrote: > >>On Mon, Jun 11, 2012 at 02:39:56PM +0100, Peter Maydell wrote: > >>>Ideally the interface used by DMA controllers should be identical to > >>>the interface used by CPUs to talk to the rest of the system: it's > >>>exactly the same bus interface in hardware, after all. > >> > >>I thought we were talking about the interface between the DMA ctrl > >>and the I/O (devices). Not between the DMA and the "memory" bus system. > > > >In hardware (at least for AXI) they're the same thing. A DMA > >controller is a bus master, just like a CPU. They don't care > >whether the slave is RAM or a device, they're just issuing > >memory transactions to addresses. > > It looks like the AXI stream interface also includes a word array. > I can't tell though whether this is just a decomposed scatter/gather > list though. Hi, IIRC the word array thing is device specific, not really AXI stream. I think the whole connection to AXI is a bit unfortunate, these devices are pretty much the same devices that in other contexts where connected to other bus standards. Xilinx choose to name them AXI-xxx and I used the name in our models but I didn't really model anything that is AXI stream specific.. > There doesn't appear to be a notion of an address though. You could > make all operations go to address 0 though but it makes me wonder if > that's stretching the concept of DMA a bit too much. Yes, IMO we need a different abstraction.. Cheers