Re: [Qemu-devel] q35 chipset support

[Jason Baron <jbaron@redhat.com>]

On Thu, Jun 14, 2012 at 03:16:03PM -0500, Anthony Liguori wrote:
> On 06/14/2012 02:54 PM, Jason Baron wrote:
> >Hi,
> >
> >I recently updated Isaku Yamahata's q35 patches to work on the latest qemu and
> >seabios trees. On the qemu side, most of the changes revolved around updating
> >to use QOM and updates to the memory API. I was also able to drop quite a few
> >patches that had already been resolved by the current qemu tree.
> >
> >The trees seem pretty stable and can be found here:
> >
> >git://github.com/jibaron/q35-qemu.git
> >git://github.com/jibaron/q35-seabios.git
> 
> I'm got the beginnings of a feature page started:
> 
> http://wiki.qemu.org/Features/Q35
> 
> The approach above will not work in a QOM world unfortunately.  We
> need to do quite a bit of ground work before adding another chipset.
> The biggest task is converting devices to not require an ISA bus
> since ICH9 simply doesn't have an ISA bus.
> 

Right, there is no h/w isa bus, but the LPC interface chip is modeled as an isa
bridge. So having an isa bus hanging off of it doesn't seem unreasonable. Unless
there is some more fundamental reason not do it this way?

It hows up in lspci as:

00:1f.0 ISA bridge: Intel Corporation 82801IB (ICH9) LPC Interface
Controller (rev 02)



> You can hack things together to work without this, but the result is
> unmaintainable spaghetti (which is pretty close to what we already
> have today).
> 
> Once the QOM bus support gets merged, I'm going to send out an ISA
> bus refactoring which gets most of the platform devices away from
> ISA..
> 
> Regards,
> 
> Anthony Liguori
>