From: Gleb Natapov <gleb@redhat.com>
To: Blue Swirl <blauwirbel@gmail.com>
Cc: Igor Mammedov <imammedo@redhat.com>,
seabios@seabios.org, Eduardo Habkost <ehabkost@redhat.com>,
Anthony Liguori <anthony@codemonkey.ws>,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [QEMU PATCH 2/7] hw/apic.c: rename bit functions to not conflict with bitops.h
Date: Sun, 15 Jul 2012 12:19:29 +0300 [thread overview]
Message-ID: <20120715091929.GA6345@redhat.com> (raw)
In-Reply-To: <CAAu8pHu_X6TNM1C0invT24sQsXn5TjwCENJPGc-vqzBHba3ZkA@mail.gmail.com>
On Sat, Jul 14, 2012 at 09:09:23AM +0000, Blue Swirl wrote:
> On Fri, Jul 13, 2012 at 6:07 PM, Eduardo Habkost <ehabkost@redhat.com> wrote:
> > On Thu, Jul 12, 2012 at 07:24:35PM +0000, Blue Swirl wrote:
> >> On Tue, Jul 10, 2012 at 8:22 PM, Eduardo Habkost <ehabkost@redhat.com> wrote:
> >> > Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
> >>
> >> Maybe the bitops functions should be renamed instead, for example
> >> prefixed by 'qemu_'. That may be safer if one day the kernel find
> >> their way to system headers too.
> >
> > Well, if there's any risk the kernel functions will conflict with the
> > QEMU function names, that would be an additional reason to rename the
> > apic.c functions too, so they don't conflict with the kernel functions
> > either.
>
> Yes, that could be the case too.
>
Than it would be Linux headers problem and will be fixed there.
> >
> > Personally, I would never sent a patch to rename the bitops.h functions,
> > as the current names work perfectly to me.
> >
> >>
> >> > ---
> >> > hw/apic.c | 34 +++++++++++++++++-----------------
> >> > 1 file changed, 17 insertions(+), 17 deletions(-)
> >> >
> >> > diff --git a/hw/apic.c b/hw/apic.c
> >> > index 60552df..d322fe3 100644
> >> > --- a/hw/apic.c
> >> > +++ b/hw/apic.c
> >> > @@ -50,7 +50,7 @@ static int ffs_bit(uint32_t value)
> >> > return ctz32(value);
> >> > }
> >> >
> >> > -static inline void set_bit(uint32_t *tab, int index)
> >> > +static inline void apic_set_bit(uint32_t *tab, int index)
> >> > {
> >> > int i, mask;
> >> > i = index >> 5;
> >> > @@ -58,7 +58,7 @@ static inline void set_bit(uint32_t *tab, int index)
> >> > tab[i] |= mask;
> >> > }
> >> >
> >> > -static inline void reset_bit(uint32_t *tab, int index)
> >> > +static inline void apic_reset_bit(uint32_t *tab, int index)
> >> > {
> >> > int i, mask;
> >> > i = index >> 5;
> >> > @@ -66,7 +66,7 @@ static inline void reset_bit(uint32_t *tab, int index)
> >> > tab[i] &= ~mask;
> >> > }
> >> >
> >> > -static inline int get_bit(uint32_t *tab, int index)
> >> > +static inline int apic_get_bit(uint32_t *tab, int index)
> >> > {
> >> > int i, mask;
> >> > i = index >> 5;
> >> > @@ -183,7 +183,7 @@ void apic_deliver_pic_intr(DeviceState *d, int level)
> >> > case APIC_DM_FIXED:
> >> > if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
> >> > break;
> >> > - reset_bit(s->irr, lvt & 0xff);
> >> > + apic_reset_bit(s->irr, lvt & 0xff);
> >> > /* fall through */
> >> > case APIC_DM_EXTINT:
> >> > cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
> >> > @@ -379,13 +379,13 @@ void apic_poll_irq(DeviceState *d)
> >> >
> >> > static void apic_set_irq(APICCommonState *s, int vector_num, int trigger_mode)
> >> > {
> >> > - apic_report_irq_delivered(!get_bit(s->irr, vector_num));
> >> > + apic_report_irq_delivered(!apic_get_bit(s->irr, vector_num));
> >> >
> >> > - set_bit(s->irr, vector_num);
> >> > + apic_set_bit(s->irr, vector_num);
> >> > if (trigger_mode)
> >> > - set_bit(s->tmr, vector_num);
> >> > + apic_set_bit(s->tmr, vector_num);
> >> > else
> >> > - reset_bit(s->tmr, vector_num);
> >> > + apic_reset_bit(s->tmr, vector_num);
> >> > if (s->vapic_paddr) {
> >> > apic_sync_vapic(s, SYNC_ISR_IRR_TO_VAPIC);
> >> > /*
> >> > @@ -405,8 +405,8 @@ static void apic_eoi(APICCommonState *s)
> >> > isrv = get_highest_priority_int(s->isr);
> >> > if (isrv < 0)
> >> > return;
> >> > - reset_bit(s->isr, isrv);
> >> > - if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, isrv)) {
> >> > + apic_reset_bit(s->isr, isrv);
> >> > + if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && apic_get_bit(s->tmr, isrv)) {
> >> > ioapic_eoi_broadcast(isrv);
> >> > }
> >> > apic_sync_vapic(s, SYNC_FROM_VAPIC | SYNC_TO_VAPIC);
> >> > @@ -445,7 +445,7 @@ static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
> >> > int idx = apic_find_dest(dest);
> >> > memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
> >> > if (idx >= 0)
> >> > - set_bit(deliver_bitmask, idx);
> >> > + apic_set_bit(deliver_bitmask, idx);
> >> > }
> >> > } else {
> >> > /* XXX: cluster mode */
> >> > @@ -455,11 +455,11 @@ static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
> >> > if (apic_iter) {
> >> > if (apic_iter->dest_mode == 0xf) {
> >> > if (dest & apic_iter->log_dest)
> >> > - set_bit(deliver_bitmask, i);
> >> > + apic_set_bit(deliver_bitmask, i);
> >> > } else if (apic_iter->dest_mode == 0x0) {
> >> > if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
> >> > (dest & apic_iter->log_dest & 0x0f)) {
> >> > - set_bit(deliver_bitmask, i);
> >> > + apic_set_bit(deliver_bitmask, i);
> >> > }
> >> > }
> >> > } else {
> >> > @@ -502,14 +502,14 @@ static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
> >> > break;
> >> > case 1:
> >> > memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
> >> > - set_bit(deliver_bitmask, s->idx);
> >> > + apic_set_bit(deliver_bitmask, s->idx);
> >> > break;
> >> > case 2:
> >> > memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
> >> > break;
> >> > case 3:
> >> > memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
> >> > - reset_bit(deliver_bitmask, s->idx);
> >> > + apic_reset_bit(deliver_bitmask, s->idx);
> >> > break;
> >> > }
> >> >
> >> > @@ -557,8 +557,8 @@ int apic_get_interrupt(DeviceState *d)
> >> > apic_sync_vapic(s, SYNC_TO_VAPIC);
> >> > return s->spurious_vec & 0xff;
> >> > }
> >> > - reset_bit(s->irr, intno);
> >> > - set_bit(s->isr, intno);
> >> > + apic_reset_bit(s->irr, intno);
> >> > + apic_set_bit(s->isr, intno);
> >> > apic_sync_vapic(s, SYNC_TO_VAPIC);
> >> > apic_update_irq(s);
> >> > return intno;
> >> > --
> >> > 1.7.10.4
> >> >
> >> >
> >>
> >
> > --
> > Eduardo
--
Gleb.
next prev parent reply other threads:[~2012-07-15 9:19 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-10 20:22 [Qemu-devel] [RFC 0/7+1] QEMU APIC ID + topology bug + CPU hotplug Eduardo Habkost
2012-07-10 20:22 ` [Qemu-devel] [PATCH 1/7] cpus.h: include cpu-common.h Eduardo Habkost
2012-07-10 20:22 ` [Qemu-devel] [QEMU PATCH 2/7] hw/apic.c: rename bit functions to not conflict with bitops.h Eduardo Habkost
2012-07-12 19:24 ` Blue Swirl
2012-07-13 18:07 ` Eduardo Habkost
2012-07-14 9:09 ` Blue Swirl
2012-07-15 9:19 ` Gleb Natapov [this message]
2012-07-10 20:22 ` [Qemu-devel] [QEMU PATCH 3/7] kvm: set vcpu_id to APIC ID instead of CPU index Eduardo Habkost
2012-07-10 20:22 ` [Qemu-devel] [QEMU RFC PATCH 4/7] i386: create apic_id_for_cpu() function Eduardo Habkost
2012-07-10 20:22 ` [Qemu-devel] [QEMU RFC PATCH 5/7] pc: write lapic info (apic IDs) to fw_cfg so seabios can use it Eduardo Habkost
2012-07-12 19:29 ` Blue Swirl
2012-07-13 18:09 ` Eduardo Habkost
2012-07-10 20:22 ` [Qemu-devel] [QEMU RFC PATCH 6/7] i386: topology & APIC ID utility functions Eduardo Habkost
2012-07-12 19:37 ` Blue Swirl
2012-07-13 18:51 ` Eduardo Habkost
2012-07-14 9:14 ` Blue Swirl
2012-07-16 17:42 ` Eduardo Habkost
2012-07-23 16:49 ` Blue Swirl
2012-07-23 18:59 ` Eduardo Habkost
2012-07-23 19:11 ` Blue Swirl
2012-07-23 19:28 ` Eduardo Habkost
2012-07-23 19:44 ` Blue Swirl
2012-07-23 20:14 ` Eduardo Habkost
2012-07-24 19:17 ` Blue Swirl
2012-07-10 20:22 ` [Qemu-devel] [QEMU RFC PATCH 7/7] generate APIC IDs according to CPU topology Eduardo Habkost
2012-07-10 20:22 ` [Qemu-devel] [Seabios RFC PATCH 1/1] get lapic IDs from fw_cfg Eduardo Habkost
2012-07-12 13:51 ` [Qemu-devel] [RFC 0/7+1] QEMU APIC ID + topology bug + CPU hotplug Igor Mammedov
2012-07-12 14:00 ` Gleb Natapov
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