From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59134) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1StIKw-0005qB-4t for qemu-devel@nongnu.org; Mon, 23 Jul 2012 09:06:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1StIKu-0006HR-Oi for qemu-devel@nongnu.org; Mon, 23 Jul 2012 09:06:09 -0400 Received: from e06smtp10.uk.ibm.com ([195.75.94.106]:34748) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1StIKu-0006HL-GA for qemu-devel@nongnu.org; Mon, 23 Jul 2012 09:06:08 -0400 Received: from /spool/local by e06smtp10.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Mon, 23 Jul 2012 14:06:07 +0100 Received: from d06av09.portsmouth.uk.ibm.com (d06av09.portsmouth.uk.ibm.com [9.149.37.250]) by d06nrmr1407.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id q6ND628t2715764 for ; Mon, 23 Jul 2012 14:06:02 +0100 Received: from d06av09.portsmouth.uk.ibm.com (loopback [127.0.0.1]) by d06av09.portsmouth.uk.ibm.com (8.14.4/8.13.1/NCO v10.0 AVout) with ESMTP id q6ND62RC001868 for ; Mon, 23 Jul 2012 07:06:02 -0600 Date: Mon, 23 Jul 2012 15:06:00 +0200 From: Cornelia Huck Message-ID: <20120723150600.57f2aab5@BR9GNB5Z> In-Reply-To: <500D4129.8030200@redhat.com> References: <1342811652-16931-1-git-send-email-peter.maydell@linaro.org> <500A52BF.9080207@web.de> <500A730F.8040604@web.de> <500A7A02.3050301@web.de> <500A8303.8020903@web.de> <500A8DAE.3040909@web.de> <500AA21E.9050506@web.de> <500AABC8.7080406@web.de> <20120723140418.76d8f874@BR9GNB5Z> <500D4129.8030200@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] kvm: Move kvm_allows_irq0_override() to target-i386 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Avi Kivity Cc: Peter Maydell , kvm , patches@linaro.org, Marcelo Tosatti , qemu-devel@nongnu.org, Alexander Graf , Jan Kiszka On Mon, 23 Jul 2012 15:18:49 +0300 Avi Kivity wrote: > > So, for example, if a specific subchannel (=device) has pending status > > and an I/O interrupt is to be generated, this interrupt remains pending > > until an arbitrary cpu is enabled for I/O interrupts. If several cpus > > are enabled for I/O interrupts, any of them may be interrupted. > > This may be costly to emulate. On x86 we do not have access to a > guest's interrupt status while it is running. Is this not the case for > s390? > > Oh, let me guess. You write some interrupt descriptor in memory > somewhere, issue one of your famous instructions, and the hardware finds > a guest vcpu and injects the interrupt. Basically, we have some flags in our control block we can set so that the cpu drops out of SIE whenever external/I/O/... interrupts are enabled and then have the host do the lowcore updates, psw swaps, etc. > > x86 has a "least priority" mode which is similar to what you're > describing, but I don't think we emulate it correctly. > > > When an > > I/O interrupt is delivered on a cpu, the cpu's lowcore contains the > > interrupt payload which defines the subchannel (=device) the interrupt > > is for. > > > > Any idea on how this architecture can be married with the irqchip > > concept is welcome. If all else fails, would a special irqfd concept > > for !irqchip be acceptable? > > I don't see an issue. You need an arch-specific irqfd configuration > ioctl (or your own data field in the existing ioctl) that defines the > payload. Then the kernel installs a poll function on that eventfd that, > when called, does the magic sequence needed to get the interrupt there. If extending the existing ioctl is acceptable, I think we will go that route. > While you don't have an irqchip, you do have asynchronous interrupt > injection, yes? That's what irqchip really is all about. You mean injection via ioctl() that is asynchronous to vcpu execution? Yes, although we use a different ioctl than the others. Cornelia