Re: [Qemu-devel] [PATCH for-1.2 v2] target-mips: Enable access to required RDHWR hardware registers

[Aurelien Jarno <aurelien@aurel32.net>]

On Tue, Aug 21, 2012 at 12:31:37PM -0500, Meador Inge wrote:
> While running in the usermode emulator all of the required*
> MIPS32r2 RDHWR hardware registers should be accessible (the
> Linux kernel enables access to these same registers).  Note
> that these registers are still enabled when the MIPS ISA is
> not release 2.  This is OK since the Linux kernel emulates
> access to them when they are not available in hardware.
> 
> * There is also the ULR register which is only recommended
>   for full release 2 compliance.  Incidentally, accessing
>   this register in the current implementation works fine
>   without flipping its access bit.
> 
> Signed-off-by: Meador Inge <meadori@codesourcery.com>
> ---
> 
> v1 -> v2:
> 
>  * Removed (env->insn_flags & ISA_MIPS32R2) condition per
>    feedback from Andreas and Aurelien.
> 
>  target-mips/translate.c |    5 +++--
>  1 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 47daf85..d643676 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -12768,8 +12768,9 @@ void cpu_state_reset(CPUMIPSState *env)
>  
>  #if defined(CONFIG_USER_ONLY)
>      env->hflags = MIPS_HFLAG_UM;
> -    /* Enable access to the SYNCI_Step register.  */
> -    env->CP0_HWREna |= (1 << 1);
> +    /* Enable access to the CPUNum, SYNCI_Step, CC, and CCRes RDHWR
> +       hardware registers.  */
> +    env->CP0_HWREna |= 0x0000000F;
>      if (env->CP0_Config1 & (1 << CP0C1_FP)) {
>          env->hflags |= MIPS_HFLAG_FPU;
>      }

Thanks, applied.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net