From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47665) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T5wQW-0003VX-TE for qemu-devel@nongnu.org; Mon, 27 Aug 2012 06:20:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1T5wQR-0007HH-31 for qemu-devel@nongnu.org; Mon, 27 Aug 2012 06:20:12 -0400 Received: from hall.aurel32.net ([88.191.126.93]:40196) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1T5wQQ-000728-Sw for qemu-devel@nongnu.org; Mon, 27 Aug 2012 06:20:07 -0400 Date: Mon, 27 Aug 2012 12:19:51 +0200 From: Aurelien Jarno Message-ID: <20120827101951.GK3553@ohm.aurel32.net> References: <1333127797-8133-1-git-send-email-rth@twiddle.net> <1333127797-8133-2-git-send-email-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1333127797-8133-2-git-send-email-rth@twiddle.net> Subject: Re: [Qemu-devel] [PATCH 1/2] target-mips: Streamline indexed cp1 memory addressing. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org On Fri, Mar 30, 2012 at 01:16:36PM -0400, Richard Henderson wrote: > We've already eliminated both base and index being zero. > --- > target-mips/translate.c | 3 +-- > 1 files changed, 1 insertions(+), 2 deletions(-) > > diff --git a/target-mips/translate.c b/target-mips/translate.c > index a663b74..300d95e 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -7742,8 +7742,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, > } else if (index == 0) { > gen_load_gpr(t0, base); > } else { > - gen_load_gpr(t0, index); > - gen_op_addr_add(ctx, t0, cpu_gpr[base], t0); > + gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]); > } > /* Don't do NOP if destination is zero: we must perform the actual > memory access. */ Thanks, applied. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net