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From: Aurelien Jarno <aurelien@aurel32.net>
To: Richard Henderson <rth@twiddle.net>
Cc: Riku Voipio <riku.voipio@iki.fi>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 2/2] mips-linux-user: Always support rdhwr.
Date: Mon, 27 Aug 2012 12:20:03 +0200	[thread overview]
Message-ID: <20120827102003.GL3553@ohm.aurel32.net> (raw)
In-Reply-To: <1333127797-8133-3-git-send-email-rth@twiddle.net>

On Fri, Mar 30, 2012 at 01:16:37PM -0400, Richard Henderson wrote:
> The kernel will emulate this instruction if it's not supported
> natively.  This insn is used for TLS, among other things, and
> so is required by modern glibc.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> Cc: Riku Voipio <riku.voipio@iki.fi>
> ---
>  target-mips/translate.c |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 300d95e..ed28ca8 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -8111,7 +8111,11 @@ gen_rdhwr (CPUMIPSState *env, DisasContext *ctx, int rt, int rd)
>  {
>      TCGv t0;
>  
> +#if !defined(CONFIG_USER_ONLY)
> +    /* The Linux kernel will emulate rdhwr if it's not supported natively.
> +       Therefore only check the ISA in system mode.  */
>      check_insn(env, ctx, ISA_MIPS32R2);
> +#endif
>      t0 = tcg_temp_new();
>  
>      switch (rd) {

Thanks, applied.
 
-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

      reply	other threads:[~2012-08-27 10:20 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2012-03-30 17:16 [Qemu-devel] [PATCH v2 0/2] misc MIPS improvments Richard Henderson
2012-03-30 17:16 ` [Qemu-devel] [PATCH 1/2] target-mips: Streamline indexed cp1 memory addressing Richard Henderson
2012-08-27 10:19   ` Aurelien Jarno
2012-03-30 17:16 ` [Qemu-devel] [PATCH 2/2] mips-linux-user: Always support rdhwr Richard Henderson
2012-08-27 10:20   ` Aurelien Jarno [this message]

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