[Qemu-devel] [PATCH v2 0/2] misc MIPS improvments

[Qemu-devel] [PATCH v2 0/2] misc MIPS improvments

[Richard Henderson]

Extracted and rebased from a larger patch set from December.

Available as 

   git://repo.or.cz/qemu/rth.git rth/mips/next


r~


Richard Henderson (2):
  target-mips: Streamline indexed cp1 memory addressing.
  mips-linux-user: Always support rdhwr.

 target-mips/translate.c |    7 +++++--
 1 files changed, 5 insertions(+), 2 deletions(-)

-- 
1.7.7.6

[Qemu-devel] [PATCH 1/2] target-mips: Streamline indexed cp1 memory addressing.

[Richard Henderson]

We've already eliminated both base and index being zero.
---
 target-mips/translate.c |    3 +--
 1 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index a663b74..300d95e 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -7742,8 +7742,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
     } else if (index == 0) {
         gen_load_gpr(t0, base);
     } else {
-        gen_load_gpr(t0, index);
-        gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
+        gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
     }
     /* Don't do NOP if destination is zero: we must perform the actual
        memory access. */
-- 
1.7.7.6

Re: [Qemu-devel] [PATCH 1/2] target-mips: Streamline indexed cp1 memory addressing.

[Aurelien Jarno]

On Fri, Mar 30, 2012 at 01:16:36PM -0400, Richard Henderson wrote:
> We've already eliminated both base and index being zero.
> ---
>  target-mips/translate.c |    3 +--
>  1 files changed, 1 insertions(+), 2 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index a663b74..300d95e 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -7742,8 +7742,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
>      } else if (index == 0) {
>          gen_load_gpr(t0, base);
>      } else {
> -        gen_load_gpr(t0, index);
> -        gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
> +        gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
>      }
>      /* Don't do NOP if destination is zero: we must perform the actual
>         memory access. */

Thanks, applied.


-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

[Qemu-devel] [PATCH 2/2] mips-linux-user: Always support rdhwr.

[Richard Henderson]

The kernel will emulate this instruction if it's not supported
natively.  This insn is used for TLS, among other things, and
so is required by modern glibc.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Cc: Riku Voipio <riku.voipio@iki.fi>
---
 target-mips/translate.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 300d95e..ed28ca8 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -8111,7 +8111,11 @@ gen_rdhwr (CPUMIPSState *env, DisasContext *ctx, int rt, int rd)
 {
     TCGv t0;
 
+#if !defined(CONFIG_USER_ONLY)
+    /* The Linux kernel will emulate rdhwr if it's not supported natively.
+       Therefore only check the ISA in system mode.  */
     check_insn(env, ctx, ISA_MIPS32R2);
+#endif
     t0 = tcg_temp_new();
 
     switch (rd) {
-- 
1.7.7.6

Re: [Qemu-devel] [PATCH 2/2] mips-linux-user: Always support rdhwr.

[Aurelien Jarno]

On Fri, Mar 30, 2012 at 01:16:37PM -0400, Richard Henderson wrote:
> The kernel will emulate this instruction if it's not supported
> natively.  This insn is used for TLS, among other things, and
> so is required by modern glibc.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> Cc: Riku Voipio <riku.voipio@iki.fi>
> ---
>  target-mips/translate.c |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 300d95e..ed28ca8 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -8111,7 +8111,11 @@ gen_rdhwr (CPUMIPSState *env, DisasContext *ctx, int rt, int rd)
>  {
>      TCGv t0;
>  
> +#if !defined(CONFIG_USER_ONLY)
> +    /* The Linux kernel will emulate rdhwr if it's not supported natively.
> +       Therefore only check the ISA in system mode.  */
>      check_insn(env, ctx, ISA_MIPS32R2);
> +#endif
>      t0 = tcg_temp_new();
>  
>      switch (rd) {

Thanks, applied.
 
-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net