* [Qemu-devel] [PATCH 00/25] q35 series take #1
@ 2012-09-13 20:12 Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 01/25] pci: pci capability must be in PCI space Jason Baron
` (26 more replies)
0 siblings, 27 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
Hi,
Qemu bits for q35 support, I'm posting the seabios changes separately. The
patches require '-M pc_q35' and -L 'seabios dir with q35 changes' on the
qemu command line. Hopefully, we can make it the default for x86 at some future
point when we feel comfortable with it.
Since q35 patches have been posted before I've tried to keep the authorship as
clear as possible. Its not quite bi-sectable (I can combine things if that works
better) due to that fact.
The current patches have been tested with basic install testing and memory testing
on f16, f17, windows 7 and windows 8. They can be run on the various BSD flavors
by adding a 'piix4-ide' device to the pci bus. ie: -device piix4-ide.
I've also added a few new features to try and get us on par with the current
piix, including:
1) migration
I've added support for ahci migration. I've done basic testing but this support
is incomplete. We should probably be migration more state than we currently are.
2) hotplug
I've added piix acpi style hotplug to ich9.
I'm hoping this series will spark a discussion as to what areas I need to focus
in order to make this patch series acceptable.
For those interested in git trees, see:
git://github.com/jibaron/q35-qemu.git
git://github.com/jibaron/q35-seabios.git
Thanks,
-Jason
Isaku Yamahata (9):
pci: pci capability must be in PCI space
pci: add opaque argument to pci_map_irq_fn
pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt
pin swizzle
ahci: add ide device initialization helper
pc, pc_piix: split out pc nic initialization
pc/piix_pci: factor out smram/pam logic
pci_ids: add intel 82801BA pci-to-pci bridge id and
PCI_CLASS_SERIAL_SMBUS
q35: Introduce q35 pc based chipset emulator
q35: Fix irr initialization for slots 25..31
Jan Kiszka (5):
q35: Suppress SMM BIOS initialization under KVM
q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic
q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and
PCI_STATUS_DETECTED_PARITY from w1cmask
pci: Add class 0xc05 as 'SMBus'
q35: Add kvmclock support
Jason Baron (11):
pc: Move ioapic_init() from pc_piix.c to pc.c
pcie: pass pcie window size to pcie_host_mmcfg_update()
pcie: Convert PCIExpressHost to use the QOM.
q35: Re-base q35
ahci: add migration support
pcie: drop version_id field for live migration
pcie_aer: clear cmask for Advanced Error Interrupt Message Number
ahci: properly reset PxCMD on HBA reset
q35: add acpi-based pci hotplug.
Add a fallback bios file search, if -L fails.
q35: automatically load the q35 dsdt table
hw/acpi_ich9.c | 492 +++++++++++++++++++++++++
hw/acpi_ich9.h | 56 +++
hw/apb_pci.c | 4 +-
hw/bonito.c | 2 +-
hw/dec_pci.c | 2 +-
hw/grackle_pci.c | 2 +-
hw/gt64xxx.c | 2 +-
hw/i386/Makefile.objs | 2 +
hw/ide.h | 3 +
hw/ide/ahci.c | 82 +++++-
hw/ide/ahci.h | 10 +
hw/ide/ich.c | 11 +-
hw/pam.c | 121 +++++++
hw/pam.h | 98 +++++
hw/pc.c | 39 ++
hw/pc.h | 5 +
hw/pc_piix.c | 38 +--
hw/pc_q35.c | 476 +++++++++++++++++++++++++
hw/pci.c | 30 ++-
hw/pci.h | 4 +-
hw/pci_bridge_dev.c | 2 +-
hw/pci_ids.h | 16 +
hw/pcie.h | 1 -
hw/pcie_aer.c | 5 +
hw/pcie_host.c | 35 ++-
hw/pcie_host.h | 12 +-
hw/piix_pci.c | 67 +---
hw/ppc4xx_pci.c | 2 +-
hw/ppce500_pci.c | 2 +-
hw/prep_pci.c | 2 +-
hw/q35.c | 945 +++++++++++++++++++++++++++++++++++++++++++++++++
hw/q35.h | 361 +++++++++++++++++++
hw/q35_smbus.c | 166 +++++++++
hw/sh_pci.c | 2 +-
hw/unin_pci.c | 2 +-
hw/versatile_pci.c | 2 +-
hw/xen.h | 2 +-
vl.c | 28 ++-
xen-all.c | 2 +-
xen-stub.c | 2 +-
40 files changed, 2997 insertions(+), 138 deletions(-)
create mode 100644 hw/acpi_ich9.c
create mode 100644 hw/acpi_ich9.h
create mode 100644 hw/pam.c
create mode 100644 hw/pam.h
create mode 100644 hw/pc_q35.c
create mode 100644 hw/q35.c
create mode 100644 hw/q35.h
create mode 100644 hw/q35_smbus.c
^ permalink raw reply [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 01/25] pci: pci capability must be in PCI space
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 02/25] pci: add opaque argument to pci_map_irq_fn Jason Baron
` (25 subsequent siblings)
26 siblings, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
From: Isaku Yamahata <yamahata@valinux.co.jp>
pci capability must be in PCI space.
It can't lay in PCIe extended config space.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pci.c | 5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 4d95984..b348596 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1626,12 +1626,11 @@ PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
return pci_create_simple_multifunction(bus, devfn, false, name);
}
-static int pci_find_space(PCIDevice *pdev, uint8_t size)
+static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size)
{
- int config_size = pci_config_size(pdev);
int offset = PCI_CONFIG_HEADER_SIZE;
int i;
- for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
+ for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i)
if (pdev->used[i])
offset = i + 1;
else if (i - offset + 1 == size)
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 02/25] pci: add opaque argument to pci_map_irq_fn
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 01/25] pci: pci capability must be in PCI space Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-14 16:32 ` Alex Williamson
2012-09-13 20:12 ` [Qemu-devel] [PATCH 03/25] pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle Jason Baron
` (24 subsequent siblings)
26 siblings, 1 reply; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
From: Isaku Yamahata <yamahata@valinux.co.jp>
Pass opaque argument to pci_map_irq_fn like pci_set_irq_fn.
ICH9 irq routing is not static, but configurable by chipset configuration
registers, so the corresponding irq mapping function of pci_map_irq_fn
needs to know the pointer to ich9.
[jbaron@redhat.com: minor tweaks]
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/apb_pci.c | 4 ++--
hw/bonito.c | 2 +-
hw/dec_pci.c | 2 +-
hw/grackle_pci.c | 2 +-
hw/gt64xxx.c | 2 +-
hw/pci.c | 4 ++--
hw/pci.h | 2 +-
hw/pci_bridge_dev.c | 2 +-
hw/piix_pci.c | 2 +-
hw/ppc4xx_pci.c | 2 +-
hw/ppce500_pci.c | 2 +-
hw/prep_pci.c | 2 +-
hw/sh_pci.c | 2 +-
hw/unin_pci.c | 2 +-
hw/versatile_pci.c | 2 +-
hw/xen.h | 2 +-
xen-all.c | 2 +-
xen-stub.c | 2 +-
18 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/hw/apb_pci.c b/hw/apb_pci.c
index c28411a..1bdac9f 100644
--- a/hw/apb_pci.c
+++ b/hw/apb_pci.c
@@ -285,12 +285,12 @@ static const MemoryRegionOps pci_ioport_ops = {
};
/* The APB host has an IRQ line for each IRQ line of each slot. */
-static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_apb_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
return ((pci_dev->devfn & 0x18) >> 1) + irq_num;
}
-static int pci_pbm_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_pbm_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
int bus_offset;
if (pci_dev->devfn & 1)
diff --git a/hw/bonito.c b/hw/bonito.c
index 6084ac4..1213652 100644
--- a/hw/bonito.c
+++ b/hw/bonito.c
@@ -651,7 +651,7 @@ static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
}
/* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
-static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num)
+static int pci_bonito_map_irq(void *opaque, PCIDevice * pci_dev, int irq_num)
{
int slot;
diff --git a/hw/dec_pci.c b/hw/dec_pci.c
index c30ade3..29a10bb 100644
--- a/hw/dec_pci.c
+++ b/hw/dec_pci.c
@@ -46,7 +46,7 @@ typedef struct DECState {
PCIHostState parent_obj;
} DECState;
-static int dec_map_irq(PCIDevice *pci_dev, int irq_num)
+static int dec_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
return irq_num;
}
diff --git a/hw/grackle_pci.c b/hw/grackle_pci.c
index 67da307..d1c4093 100644
--- a/hw/grackle_pci.c
+++ b/hw/grackle_pci.c
@@ -48,7 +48,7 @@ typedef struct GrackleState {
} GrackleState;
/* Don't know if this matches real hardware, but it agrees with OHW. */
-static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_grackle_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
return (irq_num + (pci_dev->devfn >> 3)) & 3;
}
diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index e95e664..e251658 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -874,7 +874,7 @@ static const MemoryRegionOps isd_mem_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
+static int gt64120_pci_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
int slot;
diff --git a/hw/pci.c b/hw/pci.c
index b348596..1c847c5 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -128,7 +128,7 @@ static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
PCIBus *bus;
for (;;) {
bus = pci_dev->bus;
- irq_num = bus->map_irq(pci_dev, irq_num);
+ irq_num = bus->map_irq(bus->irq_opaque, pci_dev, irq_num);
if (bus->set_irq)
break;
pci_dev = bus->parent_dev;
@@ -1091,7 +1091,7 @@ PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin)
do {
bus = dev->bus;
- pin = bus->map_irq(dev, pin);
+ pin = bus->map_irq(bus->irq_opaque, dev, pin);
dev = bus->parent_dev;
} while (dev);
assert(bus->route_intx_to_irq);
diff --git a/hw/pci.h b/hw/pci.h
index 4b6ab3d..26dc522 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -292,7 +292,7 @@ MemoryRegion *pci_address_space(PCIDevice *dev);
MemoryRegion *pci_address_space_io(PCIDevice *dev);
typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
-typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
+typedef int (*pci_map_irq_fn)(void *opaque, PCIDevice *pci_dev, int irq_num);
typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
typedef enum {
diff --git a/hw/pci_bridge_dev.c b/hw/pci_bridge_dev.c
index f706396..e72d32d 100644
--- a/hw/pci_bridge_dev.c
+++ b/hw/pci_bridge_dev.c
@@ -43,7 +43,7 @@ typedef struct PCIBridgeDev PCIBridgeDev;
/* Mapping mandated by PCI-to-PCI Bridge architecture specification,
* revision 1.2 */
/* Table 9-1: Interrupt Binding for Devices Behind a Bridge */
-static int pci_bridge_dev_map_irq_fn(PCIDevice *dev, int irq_num)
+static int pci_bridge_dev_map_irq_fn(void *opaque, PCIDevice *dev, int irq_num)
{
return (irq_num + PCI_SLOT(dev->devfn)) % PCI_NUM_PINS;
}
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 537fc19..376a287 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -98,7 +98,7 @@ static void piix3_write_config_xen(PCIDevice *dev,
/* return the global irq number corresponding to a given device irq
pin. We could also use the bus number to have a more precise
mapping. */
-static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
+static int pci_slot_get_pirq(void *opaque, PCIDevice *pci_dev, int pci_intx)
{
int slot_addend;
slot_addend = (pci_dev->devfn >> 3) - 1;
diff --git a/hw/ppc4xx_pci.c b/hw/ppc4xx_pci.c
index a14fd42..2de94d3 100644
--- a/hw/ppc4xx_pci.c
+++ b/hw/ppc4xx_pci.c
@@ -268,7 +268,7 @@ static void ppc4xx_pci_reset(void *opaque)
/* On Bamboo, all pins from each slot are tied to a single board IRQ. This
* may need further refactoring for other boards. */
-static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
+static int ppc4xx_pci_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
int slot = pci_dev->devfn >> 3;
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
index 92b1dc0..b789f29 100644
--- a/hw/ppce500_pci.c
+++ b/hw/ppce500_pci.c
@@ -233,7 +233,7 @@ static const MemoryRegionOps e500_pci_reg_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
+static int mpc85xx_pci_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
int devno = pci_dev->devfn >> 3, ret = 0;
diff --git a/hw/prep_pci.c b/hw/prep_pci.c
index cc44e61..2493b7a 100644
--- a/hw/prep_pci.c
+++ b/hw/prep_pci.c
@@ -91,7 +91,7 @@ static const MemoryRegionOps PPC_intack_ops = {
},
};
-static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
+static int prep_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
return (irq_num + (pci_dev->devfn >> 3)) & 1;
}
diff --git a/hw/sh_pci.c b/hw/sh_pci.c
index 0cfac46..76a5e5f 100644
--- a/hw/sh_pci.c
+++ b/hw/sh_pci.c
@@ -98,7 +98,7 @@ static const MemoryRegionOps sh_pci_reg_ops = {
},
};
-static int sh_pci_map_irq(PCIDevice *d, int irq_num)
+static int sh_pci_map_irq(void *opaque, PCIDevice *d, int irq_num)
{
return (d->devfn >> 3);
}
diff --git a/hw/unin_pci.c b/hw/unin_pci.c
index d1cc680..a8ae95a 100644
--- a/hw/unin_pci.c
+++ b/hw/unin_pci.c
@@ -59,7 +59,7 @@ typedef struct UNINState {
MemoryRegion pci_hole;
} UNINState;
-static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
+static int pci_unin_map_irq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
int retval;
int devfn = pci_dev->devfn & 0x00FFFFFF;
diff --git a/hw/versatile_pci.c b/hw/versatile_pci.c
index ae53a8b..1f4e6b6 100644
--- a/hw/versatile_pci.c
+++ b/hw/versatile_pci.c
@@ -46,7 +46,7 @@ static const MemoryRegionOps pci_vpb_config_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
+static int pci_vpb_map_irq(void *opaque, PCIDevice *d, int irq_num)
{
return irq_num;
}
diff --git a/hw/xen.h b/hw/xen.h
index e5926b7..d43b883 100644
--- a/hw/xen.h
+++ b/hw/xen.h
@@ -31,7 +31,7 @@ static inline int xen_enabled(void)
#endif
}
-int xen_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num);
+int xen_pci_slot_get_pirq(void *opaque, PCIDevice *pci_dev, int irq_num);
void xen_piix3_set_irq(void *opaque, int irq_num, int level);
void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len);
void xen_hvm_inject_msi(uint64_t addr, uint32_t data);
diff --git a/xen-all.c b/xen-all.c
index f76b051..22ee5a3 100644
--- a/xen-all.c
+++ b/xen-all.c
@@ -99,7 +99,7 @@ typedef struct XenIOState {
/* Xen specific function for piix pci */
-int xen_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
+int xen_pci_slot_get_pirq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
return irq_num + ((pci_dev->devfn >> 3) << 2);
}
diff --git a/xen-stub.c b/xen-stub.c
index 8ff2b79..5f71f43 100644
--- a/xen-stub.c
+++ b/xen-stub.c
@@ -16,7 +16,7 @@ void xenstore_store_pv_console_info(int i, CharDriverState *chr)
{
}
-int xen_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
+int xen_pci_slot_get_pirq(void *opaque, PCIDevice *pci_dev, int irq_num)
{
return -1;
}
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 03/25] pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 01/25] pci: pci capability must be in PCI space Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 02/25] pci: add opaque argument to pci_map_irq_fn Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 05/25] pc, pc_piix: split out pc nic initialization Jason Baron
` (23 subsequent siblings)
26 siblings, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
From: Isaku Yamahata <yamahata@valinux.co.jp>
Introduce pci_swizzle_map_irq_fn() for interrupt pin swizzle which is
standardized. PCI bridge swizzle is common logic, by introducing
this function duplicated swizzle logic will be avoided later.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pci.c | 18 ++++++++++++++++++
hw/pci.h | 2 ++
2 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 1c847c5..55e4ad3 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1121,6 +1121,24 @@ void pci_device_set_intx_routing_notifier(PCIDevice *dev,
dev->intx_routing_notifier = notifier;
}
+/*
+ * PCI-to-PCI bridge specification
+ * 9.1: Interrupt routing. Table 9-1
+ *
+ * the PCI Express Base Specification, Revision 2.1
+ * 2.2.8.1: INTx interrutp signaling - Rules
+ * the Implementation Note
+ * Table 2-20
+ */
+/*
+ * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD
+ * 0-origin unlike PCI interrupt pin register.
+ */
+int pci_swizzle_map_irq_fn(void *opaque, PCIDevice *pci_dev, int pin)
+{
+ return (pin + PCI_SLOT(pci_dev->devfn)) % PCI_NUM_PINS;
+}
+
/***********************************************************/
/* monitor info on PCI */
diff --git a/hw/pci.h b/hw/pci.h
index 26dc522..47ae740 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -316,6 +316,8 @@ void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
void *irq_opaque, int nirq);
int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);
+/* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
+int pci_swizzle_map_irq_fn(void *opaque, PCIDevice *pci_dev, int pin);
PCIBus *pci_register_bus(DeviceState *parent, const char *name,
pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
void *irq_opaque,
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 04/25] ahci: add ide device initialization helper
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (3 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 05/25] pc, pc_piix: split out pc nic initialization Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-21 14:05 ` Markus Armbruster
2012-09-13 20:12 ` [Qemu-devel] [PATCH 06/25] pc: Move ioapic_init() from pc_piix.c to pc.c Jason Baron
` (21 subsequent siblings)
26 siblings, 1 reply; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
From: Isaku Yamahata <yamahata@valinux.co.jp>
Introduce a helper function which initializes the ahci port with ide devices.
It will be used by q35 support.
Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/ide.h | 3 +++
hw/ide/ahci.c | 16 ++++++++++++++++
2 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/hw/ide.h b/hw/ide.h
index 2db4079..8df872e 100644
--- a/hw/ide.h
+++ b/hw/ide.h
@@ -36,4 +36,7 @@ int ide_get_bios_chs_trans(BusState *bus, int unit);
/* ide/core.c */
void ide_drive_get(DriveInfo **hd, int max_bus);
+/* ide/ahci.c */
+void pci_ahci_ide_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table);
+
#endif /* HW_IDE_H */
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 5ea3cad..9561210 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -1260,3 +1260,19 @@ static void sysbus_ahci_register_types(void)
}
type_init(sysbus_ahci_register_types)
+
+void pci_ahci_ide_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)
+{
+ struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card, pci_dev);
+ int i;
+
+ for (i = 0; i < dev->ahci.ports; i++) {
+ /* master device only, ignore slaves */
+ if (hd_table[i * MAX_IDE_DEVS] == NULL) {
+ continue;
+ }
+ ide_create_drive(&dev->ahci.dev[i].port, 0,
+ hd_table[i * MAX_IDE_DEVS]);
+ }
+}
+
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 05/25] pc, pc_piix: split out pc nic initialization
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (2 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 03/25] pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 04/25] ahci: add ide device initialization helper Jason Baron
` (22 subsequent siblings)
26 siblings, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
From: Isaku Yamahata <yamahata@valinux.co.jp>
Factor out pc nic initialization.
This simplifies the pc initialization and will reduce the code
duplication of q35 pc initialization.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pc.c | 15 +++++++++++++++
hw/pc.h | 1 +
hw/pc_piix.c | 9 +--------
3 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/hw/pc.c b/hw/pc.c
index 112739a..532c973 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -1150,6 +1150,21 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
*floppy = fdctrl_init_isa(isa_bus, fd);
}
+void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus)
+{
+ int i;
+
+ for (i = 0; i < nb_nics; i++) {
+ NICInfo *nd = &nd_table[i];
+
+ if (!pci_bus || (nd->model && strcmp(nd->model, "ne2k_isa") == 0)) {
+ pc_init_ne2k_isa(isa_bus, nd);
+ } else {
+ pci_nic_init_nofail(nd, "e1000", NULL);
+ }
+ }
+}
+
void pc_pci_device_init(PCIBus *pci_bus)
{
int max_bus;
diff --git a/hw/pc.h b/hw/pc.h
index e4db071..d0feb20 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -125,6 +125,7 @@ void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
const char *boot_device,
ISADevice *floppy, BusState *ide0, BusState *ide1,
ISADevice *s);
+void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
void pc_pci_device_init(PCIBus *pci_bus);
typedef void (*cpu_set_smm_t)(int smm, void *arg);
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 88ff041..fed1d0a 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -233,14 +233,7 @@ static void pc_init1(MemoryRegion *system_memory,
/* init basic PC hardware */
pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, xen_enabled());
- for(i = 0; i < nb_nics; i++) {
- NICInfo *nd = &nd_table[i];
-
- if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
- pc_init_ne2k_isa(isa_bus, nd);
- else
- pci_nic_init_nofail(nd, "e1000", NULL);
- }
+ pc_nic_init(isa_bus, pci_bus);
ide_drive_get(hd, MAX_IDE_BUS);
if (pci_enabled) {
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 07/25] pc/piix_pci: factor out smram/pam logic
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (5 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 06/25] pc: Move ioapic_init() from pc_piix.c to pc.c Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-14 18:52 ` Blue Swirl
2012-09-13 20:12 ` [Qemu-devel] [PATCH 08/25] pci_ids: add intel 82801BA pci-to-pci bridge id and PCI_CLASS_SERIAL_SMBUS Jason Baron
` (19 subsequent siblings)
26 siblings, 1 reply; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
From: Isaku Yamahata <yamahata@valinux.co.jp>
Factor out smram/pam logic for later use.
Which will be used by q35 too.
[jbaron@redhat.com: changes for updated memory API]
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/i386/Makefile.objs | 1 +
hw/pam.c | 121 +++++++++++++++++++++++++++++++++++++++++++++++++
hw/pam.h | 98 +++++++++++++++++++++++++++++++++++++++
hw/piix_pci.c | 65 ++++----------------------
4 files changed, 230 insertions(+), 55 deletions(-)
create mode 100644 hw/pam.c
create mode 100644 hw/pam.h
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index 8c764bb..2f0c172 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -6,6 +6,7 @@ obj-y += pci-hotplug.o smbios.o wdt_ib700.o
obj-y += debugcon.o multiboot.o
obj-y += pc_piix.o
obj-y += pc_sysfw.o
+obj-y += pam.o
obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o
obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o
obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
diff --git a/hw/pam.c b/hw/pam.c
new file mode 100644
index 0000000..11afeb3
--- /dev/null
+++ b/hw/pam.c
@@ -0,0 +1,121 @@
+/*
+ * QEMU i440FX/PIIX3 PCI Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * Split out from piix_pci.c
+ * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ * Copyright (c) 2012 Jason Baron <jbaron@redhat.com>
+ *
+ */
+
+#include "sysemu.h"
+#include "pam.h"
+
+void smram_update(MemoryRegion *smram_region, uint8_t smram,
+ uint8_t smm_enabled)
+{
+ bool smram_enabled;
+
+ smram_enabled = ((smm_enabled && (smram & SMRAM_G_SMRAME)) ||
+ (smram & SMRAM_D_OPEN));
+ memory_region_set_enabled(smram_region, !smram_enabled);
+}
+
+void smram_set_smm(uint8_t *host_smm_enabled, int smm, uint8_t smram,
+ MemoryRegion *smram_region)
+{
+ uint8_t smm_enabled = (smm != 0);
+ if (*host_smm_enabled != smm_enabled) {
+ *host_smm_enabled = smm_enabled;
+ smram_update(smram_region, smram, *host_smm_enabled);
+ }
+}
+
+static void pam_update_seg(PAMMemoryRegion *mem, uint32_t start, uint32_t size,
+ MemoryRegion *ram_memory,
+ MemoryRegion *pci_address_space,
+ MemoryRegion *system_memory, uint8_t attr)
+{
+ if (mem->initialized) {
+ memory_region_del_subregion(system_memory, &mem->mem);
+ memory_region_destroy(&mem->mem);
+ }
+
+ // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
+ switch (attr) {
+ case PAM_ATTR_WE | PAM_ATTR_RE:
+ /* RAM */
+ memory_region_init_alias(&mem->mem, "pam-ram", ram_memory,
+ start, size);
+ break;
+ case PAM_ATTR_RE:
+ /* ROM (XXX: not quite correct) */
+ memory_region_init_alias(&mem->mem, "pam-rom", ram_memory,
+ start, size);
+ memory_region_set_readonly(&mem->mem, true);
+ break;
+ case PAM_ATTR_WE:
+ case 0:
+ /* XXX: should distinguish read/write cases */
+ memory_region_init_alias(&mem->mem, "pam-pci", pci_address_space,
+ start, size);
+ break;
+ default:
+ abort();
+ break;
+ }
+ memory_region_add_subregion_overlap(system_memory, start, &mem->mem, 1);
+ mem->initialized = true;
+
+}
+
+static uint8_t pam_attr(uint8_t val, int hi)
+{
+ return (val >> ((!!hi) * 4)) & PAM_ATTR_MASK;
+}
+
+void pam_update(PAMMemoryRegion *mem, int idx, uint8_t val,
+ MemoryRegion *ram_memory, MemoryRegion *pci_address_space,
+ MemoryRegion *system_memory)
+{
+ uint32_t phys_addr;
+ int map_idx;
+
+ assert(0 <= idx && idx <= PAM_IDX_MAX);
+
+ if (idx == 0) {
+ pam_update_seg(&mem[0], PAM_BIOS_BASE, PAM_BIOS_SIZE, ram_memory,
+ pci_address_space, system_memory, pam_attr(val, 1));
+ return;
+ }
+
+ map_idx = (idx - 1) * 2;
+
+ phys_addr = PAM_EXPAN_BASE + PAM_EXPAN_SIZE * map_idx;
+ pam_update_seg(&mem[map_idx + 1], phys_addr, PAM_EXPAN_SIZE, ram_memory,
+ pci_address_space, system_memory, pam_attr(val, 0));
+
+ phys_addr += PAM_EXPAN_SIZE;
+ pam_update_seg(&mem[map_idx + 2], phys_addr, PAM_EXPAN_SIZE, ram_memory,
+ pci_address_space, system_memory, pam_attr(val, 1));
+}
diff --git a/hw/pam.h b/hw/pam.h
new file mode 100644
index 0000000..ce89a2a
--- /dev/null
+++ b/hw/pam.h
@@ -0,0 +1,98 @@
+#ifndef QEMU_PAM_H
+#define QEMU_PAM_H
+
+/*
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+/*
+ * Split out from piix_pci.c
+ * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ * Copyright (c) 2012 Jason Baron <jbaron@redhat.com>
+ *
+ * SMRAM memory area and PAM memory area in Legacy address range for PC.
+ * PAM: Programmable Attribute Map registers
+ *
+ * 0xa0000 - 0xbffff compatible SMRAM
+ *
+ * 0xc0000 - 0xc3fff Expansion area memory segments
+ * 0xc4000 - 0xc7fff
+ * 0xc8000 - 0xcbfff
+ * 0xcc000 - 0xcffff
+ * 0xd0000 - 0xd7fff
+ * 0xd8000 - 0xdbfff
+ * 0xdc000 - 0xdffff
+ * 0xe0000 - 0xe3fff Extended System BIOS Area Memory Segments
+ * 0xe4000 - 0xe7fff
+ * 0xe8000 - 0xebfff
+ * 0xec000 - 0xeffff
+ *
+ * 0xf0000 - 0xfffff System BIOS Area Memory Segments
+ */
+
+#include "qemu-common.h"
+#include "memory.h"
+
+#define SMRAM_C_BASE 0xa0000
+#define SMRAM_C_END 0xc0000
+#define SMRAM_C_SIZE 0x20000
+
+
+#define PAM_EXPAN_BASE 0xc0000
+#define PAM_EXPAN_SIZE 0x04000
+
+#define PAM_EXBIOS_BASE 0xe0000
+#define PAM_EXBIOS_SIZE 0x04000
+
+#define PAM_BIOS_BASE 0xf0000
+#define PAM_BIOS_END 0xfffff
+/* 64KB: Intel 3 series express chipset family p. 58*/
+#define PAM_BIOS_SIZE 0x10000
+
+/* PAM registers: log nibble and high nibble*/
+#define PAM_ATTR_WE ((uint8_t)2)
+#define PAM_ATTR_RE ((uint8_t)1)
+#define PAM_ATTR_MASK ((uint8_t)3)
+
+#define PAM_IDX_MAX 6 /* pam0 - pam6 */
+
+/* SMRAM register */
+#define SMRAM_D_OPEN ((uint8_t)(1 << 6))
+#define SMRAM_D_CLS ((uint8_t)(1 << 5))
+#define SMRAM_D_LCK ((uint8_t)(1 << 4))
+#define SMRAM_G_SMRAME ((uint8_t)(1 << 3))
+#define SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
+#define SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */
+
+typedef struct PAMMemoryRegion {
+ MemoryRegion mem;
+ bool initialized;
+} PAMMemoryRegion;
+
+void smram_update(MemoryRegion *smram_region, uint8_t smram,
+ uint8_t smm_enabled);
+void smram_set_smm(uint8_t *host_smm_enabled, int smm, uint8_t smram,
+ MemoryRegion *smram_region);
+void pam_update(PAMMemoryRegion *mem, int idx, uint8_t val,
+ MemoryRegion *ram_memory, MemoryRegion *pci_address_space,
+ MemoryRegion *system_memory);
+
+#endif /* QEMU_PAM_H */
diff --git a/hw/piix_pci.c b/hw/piix_pci.c
index 376a287..4861cf6 100644
--- a/hw/piix_pci.c
+++ b/hw/piix_pci.c
@@ -30,6 +30,7 @@
#include "sysbus.h"
#include "range.h"
#include "xen.h"
+#include "pam.h"
/*
* I440FX chipset data sheet.
@@ -68,11 +69,6 @@ typedef struct PIIX3State {
int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
} PIIX3State;
-typedef struct PAMMemoryRegion {
- MemoryRegion mem;
- bool initialized;
-} PAMMemoryRegion;
-
struct PCII440FXState {
PCIDevice dev;
MemoryRegion *system_memory;
@@ -105,56 +101,16 @@ static int pci_slot_get_pirq(void *opaque, PCIDevice *pci_dev, int pci_intx)
return (pci_intx + slot_addend) & 3;
}
-static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r,
- PAMMemoryRegion *mem)
-{
- if (mem->initialized) {
- memory_region_del_subregion(d->system_memory, &mem->mem);
- memory_region_destroy(&mem->mem);
- }
-
- // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
- switch(r) {
- case 3:
- /* RAM */
- memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory,
- start, end - start);
- break;
- case 1:
- /* ROM (XXX: not quite correct) */
- memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory,
- start, end - start);
- memory_region_set_readonly(&mem->mem, true);
- break;
- case 2:
- case 0:
- /* XXX: should distinguish read/write cases */
- memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space,
- start, end - start);
- break;
- }
- memory_region_add_subregion_overlap(d->system_memory,
- start, &mem->mem, 1);
- mem->initialized = true;
-}
-
static void i440fx_update_memory_mappings(PCII440FXState *d)
{
- int i, r;
- uint32_t smram;
- bool smram_enabled;
+ int i;
memory_region_transaction_begin();
- update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
- &d->pam_regions[0]);
- for(i = 0; i < 12; i++) {
- r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
- update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r,
- &d->pam_regions[i+1]);
+ for (i = 0; i <= PAM_IDX_MAX; i++) {
+ pam_update(&d->pam_regions[0], i, d->dev.config[I440FX_PAM + i],
+ d->ram_memory, d->pci_address_space, d->system_memory);
}
- smram = d->dev.config[I440FX_SMRAM];
- smram_enabled = (d->smm_enabled && (smram & 0x08)) || (smram & 0x40);
- memory_region_set_enabled(&d->smram_region, !smram_enabled);
+ smram_update(&d->smram_region, d->dev.config[I440FX_SMRAM], d->smm_enabled);
memory_region_transaction_commit();
}
@@ -162,11 +118,10 @@ static void i440fx_set_smm(int val, void *arg)
{
PCII440FXState *d = arg;
- val = (val != 0);
- if (d->smm_enabled != val) {
- d->smm_enabled = val;
- i440fx_update_memory_mappings(d);
- }
+ memory_region_transaction_begin();
+ smram_set_smm(&d->smm_enabled, val, d->dev.config[I440FX_SMRAM],
+ &d->smram_region);
+ memory_region_transaction_commit();
}
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 06/25] pc: Move ioapic_init() from pc_piix.c to pc.c
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (4 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 04/25] ahci: add ide device initialization helper Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 07/25] pc/piix_pci: factor out smram/pam logic Jason Baron
` (20 subsequent siblings)
26 siblings, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
Move ioapic_init from pc_piix.c to pc.c, to make it a common function.
Rename ioapic_init -> ioapic_init_gsi.
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pc.c | 24 ++++++++++++++++++++++++
hw/pc.h | 2 ++
hw/pc_piix.c | 25 +------------------------
3 files changed, 27 insertions(+), 24 deletions(-)
diff --git a/hw/pc.c b/hw/pc.c
index 532c973..b436026 100644
--- a/hw/pc.c
+++ b/hw/pc.c
@@ -1175,3 +1175,27 @@ void pc_pci_device_init(PCIBus *pci_bus)
pci_create_simple(pci_bus, -1, "lsi53c895a");
}
}
+
+void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name)
+{
+ DeviceState *dev;
+ SysBusDevice *d;
+ unsigned int i;
+
+ if (kvm_irqchip_in_kernel()) {
+ dev = qdev_create(NULL, "kvm-ioapic");
+ } else {
+ dev = qdev_create(NULL, "ioapic");
+ }
+ if (parent_name) {
+ object_property_add_child(object_resolve_path(parent_name, NULL),
+ "ioapic", OBJECT(dev), NULL);
+ }
+ qdev_init_nofail(dev);
+ d = sysbus_from_qdev(dev);
+ sysbus_mmio_map(d, 0, 0xfec00000);
+
+ for (i = 0; i < IOAPIC_NUM_PINS; i++) {
+ gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
+ }
+}
diff --git a/hw/pc.h b/hw/pc.h
index d0feb20..c78923c 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -131,6 +131,8 @@ void pc_pci_device_init(PCIBus *pci_bus);
typedef void (*cpu_set_smm_t)(int smm, void *arg);
void cpu_smm_register(cpu_set_smm_t callback, void *arg);
+void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
+
/* acpi.c */
extern int acpi_enabled;
extern char *acpi_tables;
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index fed1d0a..60c7166 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -94,29 +94,6 @@ static void kvm_piix3_gsi_handler(void *opaque, int n, int level)
}
}
-static void ioapic_init(GSIState *gsi_state)
-{
- DeviceState *dev;
- SysBusDevice *d;
- unsigned int i;
-
- if (kvm_irqchip_in_kernel()) {
- dev = qdev_create(NULL, "kvm-ioapic");
- } else {
- dev = qdev_create(NULL, "ioapic");
- }
- /* FIXME: this should be under the piix3. */
- object_property_add_child(object_resolve_path("i440fx", NULL),
- "ioapic", OBJECT(dev), NULL);
- qdev_init_nofail(dev);
- d = sysbus_from_qdev(dev);
- sysbus_mmio_map(d, 0, 0xfec00000);
-
- for (i = 0; i < IOAPIC_NUM_PINS; i++) {
- gsi_state->ioapic_irq[i] = qdev_get_gpio_in(dev, i);
- }
-}
-
/* PC hardware initialisation */
static void pc_init1(MemoryRegion *system_memory,
MemoryRegion *system_io,
@@ -220,7 +197,7 @@ static void pc_init1(MemoryRegion *system_memory,
gsi_state->i8259_irq[i] = i8259[i];
}
if (pci_enabled) {
- ioapic_init(gsi_state);
+ ioapic_init_gsi(gsi_state, "i440fx");
}
pc_register_ferr_irq(gsi[13]);
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 08/25] pci_ids: add intel 82801BA pci-to-pci bridge id and PCI_CLASS_SERIAL_SMBUS
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (6 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 07/25] pc/piix_pci: factor out smram/pam logic Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 10/25] pcie: Convert PCIExpressHost to use the QOM Jason Baron
` (18 subsequent siblings)
26 siblings, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
From: Isaku Yamahata <yamahata@valinux.co.jp>
Adds pci id constants which will be used by q35.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pci_ids.h | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 301bf1c..6deeac0 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -31,6 +31,7 @@
#define PCI_CLASS_SYSTEM_OTHER 0x0880
#define PCI_CLASS_SERIAL_USB 0x0c03
+#define PCI_CLASS_SERIAL_SMBUS 0x0c05
#define PCI_CLASS_BRIDGE_HOST 0x0600
#define PCI_CLASS_BRIDGE_ISA 0x0601
@@ -106,6 +107,7 @@
#define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415
#define PCI_DEVICE_ID_INTEL_82801D 0x24CD
#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab
+#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e
#define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
#define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
#define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 10/25] pcie: Convert PCIExpressHost to use the QOM.
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (7 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 08/25] pci_ids: add intel 82801BA pci-to-pci bridge id and PCI_CLASS_SERIAL_SMBUS Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-15 15:16 ` Andreas Färber
2012-09-13 20:12 ` [Qemu-devel] [PATCH 09/25] pcie: pass pcie window size to pcie_host_mmcfg_update() Jason Baron
` (17 subsequent siblings)
26 siblings, 1 reply; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
Let's use PCIExpressHost with QOM.
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pcie_host.c | 14 ++++++++++++++
hw/pcie_host.h | 4 ++++
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/hw/pcie_host.c b/hw/pcie_host.c
index e2fd276..027ba05 100644
--- a/hw/pcie_host.c
+++ b/hw/pcie_host.c
@@ -145,3 +145,17 @@ void pcie_host_mmcfg_update(PCIExpressHost *e,
pcie_host_mmcfg_map(e, addr, size);
}
}
+
+static const TypeInfo pcie_host_type_info = {
+ .name = TYPE_PCIE_HOST_BRIDGE,
+ .parent = TYPE_PCI_HOST_BRIDGE,
+ .abstract = true,
+ .instance_size = sizeof(PCIExpressHost),
+};
+
+static void pcie_host_register_types(void)
+{
+ type_register_static(&pcie_host_type_info);
+}
+
+type_init(pcie_host_register_types)
diff --git a/hw/pcie_host.h b/hw/pcie_host.h
index 2faa54e..2494c71 100644
--- a/hw/pcie_host.h
+++ b/hw/pcie_host.h
@@ -24,6 +24,10 @@
#include "pci_host.h"
#include "memory.h"
+#define TYPE_PCIE_HOST_BRIDGE "pcie-host-bridge"
+#define PCIE_HOST_BRIDGE(obj) \
+ OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE)
+
struct PCIExpressHost {
PCIHostState pci;
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 09/25] pcie: pass pcie window size to pcie_host_mmcfg_update()
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (8 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 10/25] pcie: Convert PCIExpressHost to use the QOM Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator Jason Baron
` (16 subsequent siblings)
26 siblings, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
This allows q35 to pass/set the size of the pcie window in its update routine.
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pcie_host.c | 21 ++++++++++++---------
hw/pcie_host.h | 8 +++++---
2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/hw/pcie_host.c b/hw/pcie_host.c
index 28bbe72..e2fd276 100644
--- a/hw/pcie_host.c
+++ b/hw/pcie_host.c
@@ -107,14 +107,9 @@ static const MemoryRegionOps pcie_mmcfg_ops = {
/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
#define PCIE_BASE_ADDR_UNMAPPED ((target_phys_addr_t)-1ULL)
-int pcie_host_init(PCIExpressHost *e, uint32_t size)
+int pcie_host_init(PCIExpressHost *e)
{
- assert(!(size & (size - 1))); /* power of 2 */
- assert(size >= PCIE_MMCFG_SIZE_MIN);
- assert(size <= PCIE_MMCFG_SIZE_MAX);
e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
- e->size = size;
- memory_region_init_io(&e->mmio, &pcie_mmcfg_ops, e, "pcie-mmcfg", e->size);
return 0;
}
@@ -123,22 +118,30 @@ void pcie_host_mmcfg_unmap(PCIExpressHost *e)
{
if (e->base_addr != PCIE_BASE_ADDR_UNMAPPED) {
memory_region_del_subregion(get_system_memory(), &e->mmio);
+ memory_region_destroy(&e->mmio);
e->base_addr = PCIE_BASE_ADDR_UNMAPPED;
}
}
-void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr)
+void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr,
+ uint32_t size)
{
+ assert(!(size & (size - 1))); /* power of 2 */
+ assert(size >= PCIE_MMCFG_SIZE_MIN);
+ assert(size <= PCIE_MMCFG_SIZE_MAX);
+ e->size = size;
+ memory_region_init_io(&e->mmio, &pcie_mmcfg_ops, e, "pcie-mmcfg", e->size);
e->base_addr = addr;
memory_region_add_subregion(get_system_memory(), e->base_addr, &e->mmio);
}
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
- target_phys_addr_t addr)
+ target_phys_addr_t addr,
+ uint32_t size)
{
pcie_host_mmcfg_unmap(e);
if (enable) {
- pcie_host_mmcfg_map(e, addr);
+ pcie_host_mmcfg_map(e, addr, size);
}
}
diff --git a/hw/pcie_host.h b/hw/pcie_host.h
index 0074508..2faa54e 100644
--- a/hw/pcie_host.h
+++ b/hw/pcie_host.h
@@ -39,11 +39,13 @@ struct PCIExpressHost {
MemoryRegion mmio;
};
-int pcie_host_init(PCIExpressHost *e, uint32_t size);
+int pcie_host_init(PCIExpressHost *e);
void pcie_host_mmcfg_unmap(PCIExpressHost *e);
-void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr);
+void pcie_host_mmcfg_map(PCIExpressHost *e, target_phys_addr_t addr,
+ uint32_t size);
void pcie_host_mmcfg_update(PCIExpressHost *e,
int enable,
- target_phys_addr_t addr);
+ target_phys_addr_t addr,
+ uint32_t size);
#endif /* PCIE_HOST_H */
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (9 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 09/25] pcie: pass pcie window size to pcie_host_mmcfg_update() Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-14 7:02 ` Paolo Bonzini
` (3 more replies)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 12/25] q35: Re-base q35 to 1.2 Jason Baron
` (15 subsequent siblings)
26 siblings, 4 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
From: Isaku Yamahata <yamahata@valinux.co.jp>
pc q35 based chipset emulator to support pci express natively.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/acpi_ich9.c | 315 ++++++++++++++++++
hw/acpi_ich9.h | 53 +++
hw/i386/Makefile.objs | 1 +
hw/pc_q35.c | 378 +++++++++++++++++++++
hw/pci_ids.h | 14 +
hw/q35.c | 877 +++++++++++++++++++++++++++++++++++++++++++++++++
hw/q35.h | 272 +++++++++++++++
hw/q35_smbus.c | 154 +++++++++
8 files changed, 2064 insertions(+), 0 deletions(-)
create mode 100644 hw/acpi_ich9.c
create mode 100644 hw/acpi_ich9.h
create mode 100644 hw/pc_q35.c
create mode 100644 hw/q35.c
create mode 100644 hw/q35.h
create mode 100644 hw/q35_smbus.c
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
new file mode 100644
index 0000000..59c0807
--- /dev/null
+++ b/hw/acpi_ich9.c
@@ -0,0 +1,315 @@
+/*
+ * ACPI implementation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+/*
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This is based on acpi.c.
+ */
+#include "hw.h"
+#include "pc.h"
+#include "pci.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
+#include "acpi.h"
+
+#include "q35.h"
+
+//#define DEBUG
+
+#ifdef DEBUG
+#define ICH9_DEBUG(fmt, ...) \
+do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
+#else
+#define ICH9_DEBUG(fmt, ...) do { } while (0)
+#endif
+
+static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
+ uint32_t val);
+static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len);
+
+static void pm_update_sci(ICH9_LPCPmRegs *pm)
+{
+ int sci_level, pm1a_sts;
+
+ pm1a_sts = acpi_pm1_evt_get_sts(&pm->pm1a, pm->tmr.overflow_time);
+
+ sci_level = (((pm1a_sts & pm->pm1a.en) &
+ (ACPI_BITMASK_RT_CLOCK_ENABLE |
+ ACPI_BITMASK_POWER_BUTTON_ENABLE |
+ ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
+ ACPI_BITMASK_TIMER_ENABLE)) != 0);
+ qemu_set_irq(pm->irq, sci_level);
+
+ /* schedule a timer interruption if needed */
+ acpi_pm_tmr_update(&pm->tmr,
+ (pm->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
+ !(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
+}
+
+static void ich9_pm_update_sci_fn(ACPIPMTimer *tmr)
+{
+ ICH9_LPCPmRegs *pm = container_of(tmr, ICH9_LPCPmRegs, tmr);
+ pm_update_sci(pm);
+}
+
+static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+
+ switch (addr & ICH9_PMIO_MASK) {
+ case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
+ acpi_gpe_ioport_writeb(&pm->gpe0, addr, val);
+ break;
+ default:
+ break;
+ }
+
+ ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
+}
+
+static uint32_t pm_ioport_readb(void *opaque, uint32_t addr)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+ uint32_t val = 0;
+
+ switch (addr & ICH9_PMIO_MASK) {
+ case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
+ val = acpi_gpe_ioport_readb(&pm->gpe0, addr);
+ break;
+ default:
+ val = 0;
+ break;
+ }
+ ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
+ return val;
+}
+
+static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+
+ switch (addr & ICH9_PMIO_MASK) {
+ case ICH9_PMIO_PM1_STS:
+ acpi_pm1_evt_write_sts(&pm->pm1a, &pm->tmr, val);
+ pm_update_sci(pm);
+ break;
+ case ICH9_PMIO_PM1_EN:
+ pm->pm1a.en = val;
+ pm_update_sci(pm);
+ break;
+ case ICH9_PMIO_PM1_CNT:
+ acpi_pm1_cnt_write(&pm->pm1a, &pm->pm1_cnt, val);
+ break;
+ default:
+ pm_ioport_write_fallback(opaque, addr, 2, val);
+ break;
+ }
+ ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
+}
+
+static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+ uint32_t val;
+
+ switch (addr & ICH9_PMIO_MASK) {
+ case ICH9_PMIO_PM1_STS:
+ val = acpi_pm1_evt_get_sts(&pm->pm1a, pm->tmr.overflow_time);
+ break;
+ case ICH9_PMIO_PM1_EN:
+ val = pm->pm1a.en;
+ break;
+ case ICH9_PMIO_PM1_CNT:
+ val = pm->pm1_cnt.cnt;
+ break;
+ default:
+ val = pm_ioport_read_fallback(opaque, addr, 2);
+ break;
+ }
+ ICH9_DEBUG("port=0x%04x val=0x%04x\n", addr, val);
+ return val;
+}
+
+static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+
+ switch (addr & ICH9_PMIO_MASK) {
+ case ICH9_PMIO_SMI_EN:
+ pm->smi_en = val;
+ break;
+ default:
+ pm_ioport_write_fallback(opaque, addr, 4, val);
+ break;
+ }
+ ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
+}
+
+static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+ uint32_t val;
+
+ switch (addr & ICH9_PMIO_MASK) {
+ case ICH9_PMIO_PM1_TMR:
+ val = acpi_pm_tmr_get(&pm->tmr);
+ break;
+ case ICH9_PMIO_SMI_EN:
+ val = pm->smi_en;
+ break;
+
+ default:
+ val = pm_ioport_read_fallback(opaque, addr, 4);
+ break;
+ }
+ ICH9_DEBUG("port=0x%04x val=0x%08x\n", addr, val);
+ return val;
+}
+
+static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
+ uint32_t val)
+ {
+ int subsize = (len == 4) ? 2 : 1;
+ IOPortWriteFunc *ioport_write =
+ (subsize == 2) ? pm_ioport_writew : pm_ioport_writeb;
+
+ int i;
+
+ for (i = 0; i < len; i += subsize) {
+ ioport_write(opaque, addr, val);
+ val >>= 8 * subsize;
+ }
+}
+
+static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len)
+{
+ int subsize = (len == 4) ? 2 : 1;
+ IOPortReadFunc *ioport_read =
+ (subsize == 2) ? pm_ioport_readw : pm_ioport_readb;
+
+ uint32_t val;
+ int i;
+
+ val = 0;
+ for (i = 0; i < len; i += subsize) {
+ val <<= 8 * subsize;
+ val |= ioport_read(opaque, addr);
+ }
+
+ return val;
+}
+
+void ich9_pm_iospace_update(ICH9_LPCPmRegs *pm, uint32_t pm_io_base)
+{
+ ICH9_DEBUG("to 0x%x\n", pm_io_base);
+
+ assert((pm_io_base & ICH9_PMIO_MASK) == 0);
+
+ if (pm->pm_io_base != 0) {
+ isa_unassign_ioport(pm->pm_io_base, ICH9_PMIO_SIZE);
+ }
+
+ /* don't map at 0 */
+ if (pm_io_base == 0) {
+ return;
+ }
+
+ register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_writeb, pm);
+ register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 1, pm_ioport_readb, pm);
+ register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_writew, pm);
+ register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 2, pm_ioport_readw, pm);
+ register_ioport_write(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_writel, pm);
+ register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_readl, pm);
+
+ pm->pm_io_base = pm_io_base;
+ acpi_gpe_blk(&pm->gpe0, pm_io_base + ICH9_PMIO_GPE0_STS);
+}
+
+static int ich9_pm_post_load(void *opaque, int version_id)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+ uint32_t pm_io_base = pm->pm_io_base;
+ pm->pm_io_base = 0;
+ ich9_pm_iospace_update(pm, pm_io_base);
+ return 0;
+}
+
+#define VMSTATE_GPE_ARRAY(_field, _state) \
+ { \
+ .name = (stringify(_field)), \
+ .version_id = 0, \
+ .num = ICH9_PMIO_GPE0_LEN, \
+ .info = &vmstate_info_uint8, \
+ .size = sizeof(uint8_t), \
+ .flags = VMS_ARRAY | VMS_POINTER, \
+ .offset = vmstate_offset_pointer(_state, _field, uint8_t), \
+ }
+
+const VMStateDescription vmstate_ich9_pm = {
+ .name = "ich9_pm",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .post_load = ich9_pm_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT16(pm1a.sts, ICH9_LPCPmRegs),
+ VMSTATE_UINT16(pm1a.en, ICH9_LPCPmRegs),
+ VMSTATE_UINT16(pm1_cnt.cnt, ICH9_LPCPmRegs),
+ VMSTATE_TIMER(tmr.timer, ICH9_LPCPmRegs),
+ VMSTATE_INT64(tmr.overflow_time, ICH9_LPCPmRegs),
+ VMSTATE_GPE_ARRAY(gpe0.sts, ICH9_LPCPmRegs),
+ VMSTATE_GPE_ARRAY(gpe0.en, ICH9_LPCPmRegs),
+ VMSTATE_UINT32(smi_en, ICH9_LPCPmRegs),
+ VMSTATE_UINT32(smi_sts, ICH9_LPCPmRegs),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void pm_reset(void *opaque)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+ ich9_pm_iospace_update(pm, 0);
+
+ acpi_pm1_evt_reset(&pm->pm1a);
+ acpi_pm1_cnt_reset(&pm->pm1_cnt);
+ acpi_pm_tmr_reset(&pm->tmr);
+ acpi_gpe_reset(&pm->gpe0);
+
+ pm_update_sci(pm);
+}
+
+static void pm_powerdown(void *opaque, int irq, int power_failing)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+ ACPIPM1EVT *pm1a = pm ? &pm->pm1a : NULL;
+ ACPIPMTimer *tmr = pm ? &pm->tmr : NULL;
+
+ acpi_pm1_evt_power_down(pm1a, tmr);
+}
+
+void ich9_pm_init(ICH9_LPCPmRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
+{
+ acpi_pm_tmr_init(&pm->tmr, ich9_pm_update_sci_fn);
+ acpi_pm1_cnt_init(&pm->pm1_cnt, cmos_s3);
+ acpi_gpe_init(&pm->gpe0, ICH9_PMIO_GPE0_LEN);
+
+ pm->irq = sci_irq;
+ qemu_register_reset(pm_reset, pm);
+ qemu_system_powerdown = *qemu_allocate_irqs(pm_powerdown, pm, 1);
+}
diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h
new file mode 100644
index 0000000..f55c0e9
--- /dev/null
+++ b/hw/acpi_ich9.h
@@ -0,0 +1,53 @@
+/*
+ * QEMU GMCH/ICH9 LPC PM Emulation
+ *
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#ifndef HW_ACPI_ICH9_H
+#define HW_ACPI_ICH9_H
+
+#include "acpi.h"
+
+typedef struct ICH9_LPCPmRegs {
+ ACPIPM1EVT pm1a;
+
+ /*
+ * In ich9 spec says that pm1_cnt register is 32bit width and
+ * that the upper 16bits are reserved and unused.
+ * PM1a_CNT_BLK = 2 in FADT so it is defined as uint16_t.
+ */
+ ACPIPM1CNT pm1_cnt;
+
+ ACPIPMTimer tmr;
+
+ ACPIGPE gpe0;
+
+ uint32_t smi_en;
+ uint32_t smi_sts;
+
+ qemu_irq irq; /* SCI */
+
+ uint32_t pm_io_base;
+} ICH9_LPCPmRegs;
+
+void ich9_pm_init(ICH9_LPCPmRegs *pm,
+ qemu_irq sci_irq, qemu_irq cmos_s3_resume);
+void ich9_pm_iospace_update(ICH9_LPCPmRegs *pm, uint32_t pm_io_base);
+extern const VMStateDescription vmstate_ich9_pm;
+
+#endif /* HW_ACPI_ICH9_H */
diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
index 2f0c172..f24dc6b 100644
--- a/hw/i386/Makefile.objs
+++ b/hw/i386/Makefile.objs
@@ -7,6 +7,7 @@ obj-y += debugcon.o multiboot.o
obj-y += pc_piix.o
obj-y += pc_sysfw.o
obj-y += pam.o
+obj-y += pc_q35.o q35.o q35_smbus.o acpi_ich9.o
obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o
obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o
obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
new file mode 100644
index 0000000..4f75d97
--- /dev/null
+++ b/hw/pc_q35.c
@@ -0,0 +1,378 @@
+/*
+ * QEMU PC System Emulator
+ *
+ * Copyright (c) 2003-2004 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+/*
+ * Q35 chipset based pc system emulator
+ *
+ * Copyright (c) 2009, 2010
+ * Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This is based on pc.c, but heavily modified.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+#include "hw.h"
+#include "arch_init.h"
+#include "pc.h"
+#include "fdc.h"
+#include "pci.h"
+#include "pci_bridge.h"
+#include "pci_p2pbr.h"
+#include "ioh3420.h"
+#include "xio3130_upstream.h"
+#include "xio3130_downstream.h"
+#include "block.h"
+#include "blockdev.h"
+#include "sysemu.h"
+#include "audio/audio.h"
+#include "net.h"
+#include "smbus.h"
+#include "boards.h"
+#include "monitor.h"
+#include "fw_cfg.h"
+#include "hpet_emul.h"
+#include "watchdog.h"
+#include "smbios.h"
+#include "ide.h"
+#include "usb-uhci.h"
+
+#include "q35.h"
+
+/* ICH9 AHCI has 6 ports */
+#define MAX_SATA_PORTS 6
+
+#define I21154_REV 0x05
+#define I21154_PI 0x00
+
+static PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
+ bool multifunction)
+{
+ const PCIP2PBridgeInit init = {
+ .bus = bus,
+ .devfn = devfn,
+ .multifunction = multifunction,
+
+ .bus_name = bus_name,
+ .map_irq = pci_swizzle_map_irq_fn,
+ };
+ const PCIP2PBridgeProp prop = {
+ .vendor_id = PCI_VENDOR_ID_DEC,
+ .device_id = PCI_DEVICE_ID_DEC_21154,
+ .revision_id = I21154_REV,
+ .prog_interface = I21154_PI,
+ };
+ return pci_p2pbr_create_simple(&init, &prop);
+}
+
+static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
+{
+ uint8_t dev;
+ uint8_t sec_bus;
+ uint8_t port = 0;
+ uint8_t chassis = 0;
+ uint16_t slot = 0;
+ uint8_t upstream_port;
+ PCIESlot *s;
+ uint8_t fn;
+ PCIESlot *root_port;
+ PCIBus *root_port_bus;
+ char buf[16];
+
+ /* PCI to PCI bridge b6:d[29 - 31]:f0, 6:[1c - 1f].0 with subordinate bus
+ of 7 - 9 on b0:d30:f0, 0.1e.0 = bus */
+#define Q35_P2P_BRDIGE_DEV_BASE 28
+#define Q35_P2P_BRDIGE_DEV_MAX 32
+#define Q35_P2P_BRDIGE_SUBBUS_BASE (ICH9_D2P_SECONDARY_DEFAULT + 1)
+ for (dev = Q35_P2P_BRDIGE_DEV_BASE; dev < Q35_P2P_BRDIGE_DEV_MAX; dev++) {
+ PCIBridge *br;
+ sec_bus = Q35_P2P_BRDIGE_SUBBUS_BASE + dev - Q35_P2P_BRDIGE_DEV_BASE;
+
+ snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
+ br = i21154_init(pci_bus, PCI_DEVFN(dev, 0), buf, true);
+ }
+
+ /* PCIe root port b0:d1:f0 in GMCH.
+ * Actually it's vid/did = 0x8086:0x29c1, but we substitute ioh for it.
+ */
+ sec_bus = 32;
+ snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+ s = ioh3420_init(host_bus, PCI_DEVFN(GMCH_PCIE_DEV, GMCH_PCIE_FUNC), true,
+ buf, pci_swizzle_map_irq_fn, port, chassis, slot);
+
+
+ /* more slots. ICH9 doesn't have those, but many slots are wanted. */
+//#define Q35_MANY_SLOTS
+#undef Q35_MANY_SLOTS
+
+#ifdef Q35_MANY_SLOTS
+#define Q35_NR_ROOTPORT 6
+#define Q35_NR_UPSTREAM 8
+#define Q35_NR_DOWNSTREAM 16
+#else
+#define Q35_NR_ROOTPORT 1
+#define Q35_NR_UPSTREAM 1
+#define Q35_NR_DOWNSTREAM 1
+#endif
+
+ /* PCIe root port b0:d23:f[0-5], 0.17.[0-5] */
+ for (fn = 0; fn < Q35_NR_ROOTPORT; fn++) {
+ sec_bus++;
+ port++;
+ slot++;
+
+ snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+ s = ioh3420_init(host_bus, PCI_DEVFN(23, fn), true,
+ buf, pci_swizzle_map_irq_fn, port, chassis, slot);
+ }
+
+ /* PCIe root port b0:d24:f0 */
+ sec_bus++;
+ port++;
+ slot++;
+ snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+ root_port = ioh3420_init(host_bus, PCI_DEVFN(24, 0), true,
+ buf, pci_swizzle_map_irq_fn, port, chassis, slot);
+ root_port_bus = pci_bridge_get_sec_bus(&root_port->port.br);
+
+ /* 8 * 16 = 128 slots */
+ upstream_port = 0;
+ for (fn = 0; fn < Q35_NR_UPSTREAM; fn++) {
+ PCIEPort *upstream;
+ PCIBus *upstream_bus;
+ uint16_t downstream_port;
+
+ uint8_t ds_dev_max;
+ uint8_t ds_dev;
+ uint8_t ds_fn_max;
+ uint8_t ds_fn;
+
+ /* PCIe upstream port d0:f[0-7] */
+ sec_bus++;
+ snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+ upstream = xio3130_upstream_init(root_port_bus, PCI_DEVFN(0, fn),
+ true, buf, pci_swizzle_map_irq_fn,
+ upstream_port);
+
+ upstream_bus = pci_bridge_get_sec_bus(&upstream->br);
+ upstream_port++;
+
+ /* PCIe downstream port */
+ downstream_port = 0;
+ ds_fn_max = MIN(Q35_NR_DOWNSTREAM / PCI_SLOT_MAX, PCI_FUNC_MAX);
+ ds_dev_max = MIN(Q35_NR_DOWNSTREAM / (ds_fn_max + 1), PCI_SLOT_MAX);
+
+ for (ds_dev = 0; ds_dev <= ds_dev_max &&
+ downstream_port < Q35_NR_DOWNSTREAM; ds_dev++) {
+ for (ds_fn = 0; ds_fn <= ds_fn_max &&
+ downstream_port < Q35_NR_DOWNSTREAM; ds_fn++) {
+ sec_bus++;
+ slot++;
+ snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+
+ xio3130_downstream_init(upstream_bus, PCI_DEVFN(ds_dev, ds_fn),
+ true, buf, pci_swizzle_map_irq_fn,
+ downstream_port, chassis, slot);
+ downstream_port++;
+ }
+ }
+ }
+
+ /* PCIe root port b0:d28:f[0-6] in ICH9.
+ * Actually it's vid/did = 0x8086:0x294[02468A], but we substitute ioh
+ * for them.
+ */
+ for (fn = 0; fn < ICH9_PCIE_FUNC_MAX; fn++) {
+ sec_bus++;
+ port++;
+ slot++;
+
+ snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
+ s = ioh3420_init(host_bus, PCI_DEVFN(ICH9_PCIE_DEV, fn), true,
+ buf, pci_swizzle_map_irq_fn,
+ port, chassis, slot);
+ }
+}
+
+static void pc_q35_init_early(qemu_irq *isa_irq, IsaIrqState *isa_irq_state,
+ DeviceState **gmch_host_p,
+ PCIBus **host_bus_p, PCIBus **pci_bus_p,
+ PCIDevice **lpc_p)
+{
+ DeviceState *gmch_host;
+ PCIBus *host_bus;
+ PCIBus *pci_bus;
+
+ PCIDevice *gmch_state;
+ PCIDevice *lpc;
+
+ /* create pci host bus */
+ host_bus = gmch_host_init(&gmch_host, isa_irq, isa_irq_state->ioapic);
+ gmch_state = gmch_init(gmch_host, host_bus);
+
+ /* create conventional pci bus: pcie2pci bridge */
+ pci_bus = ich9_d2pbr_init(host_bus, PCI_DEVFN(ICH9_D2P_BRIDGE_DEV,
+ ICH9_D2P_BRIDGE_FUNC),
+ ICH9_D2P_SECONDARY_DEFAULT);
+
+ /* create child pci/pcie buses */
+ pc_q35_bridge_init(host_bus, pci_bus);
+
+ /* create ISA bus */
+ lpc = gmch_lpc_init(gmch_host, host_bus);
+
+ *gmch_host_p = gmch_host;
+ *host_bus_p = host_bus;
+ *pci_bus_p = pci_bus;
+ *lpc_p = lpc;
+}
+
+static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,
+ DeviceState *gmch_host,
+ PCIBus *host_bus, PCIBus *pci_bus,
+ PCIDevice *lpc)
+{
+ qemu_irq *cmos_s3;
+ PCIDevice *ahci;
+ DriveInfo *hd[MAX_SATA_PORTS * MAX_IDE_DEVS];
+
+ /* connect pm stuff to lpc */
+ cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
+ ich9_lpc_pm_init(gmch_host, lpc, *cmos_s3);
+
+ /* ahci and SATA device */
+ ide_drive_get(hd, MAX_SATA_PORTS);
+ ahci = pci_create_simple_multifunction(host_bus,
+ PCI_DEVFN(ICH9_SATA1_DEV,
+ ICH9_SATA1_FUNC),
+ true, "ich9-ahci");
+ pci_ahci_ide_create_devs(ahci, hd);
+ idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
+ idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
+
+ if (usb_enabled) {
+ /* Should we create 6 UHCI according to ich9 spec? */
+ pci_create_simple_multifunction(
+ host_bus, PCI_DEVFN(ICH9_USB_UHCI1_DEV, ICH9_USB_UHCI1_FUNC),
+ true, "ich9-usb-uhci1");
+ /* XXX: EHCI */
+ }
+
+ /* TODO: Populate SPD eeprom data. */
+ smbus_eeprom_init(ich9_smb_init(host_bus,
+ PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
+ 0xb100),
+ 8, NULL, 0);
+}
+
+/* PC hardware initialisation */
+static void pc_q35_init(ram_addr_t ram_size,
+ const char *boot_device,
+ const char *kernel_filename,
+ const char *kernel_cmdline,
+ const char *initrd_filename,
+ const char *cpu_model)
+{
+ ram_addr_t below_4g_mem_size, above_4g_mem_size;
+ DeviceState *gmch_host;
+ PCIBus *host_bus;
+ PCIBus *pci_bus;
+ PCIDevice *lpc;
+ qemu_irq *isa_irq;
+ IsaIrqState *isa_irq_state;
+ BusState *idebus[MAX_SATA_PORTS];
+ ISADevice *rtc_state;
+ MemoryRegion *pci_memory;
+ MemoryRegion *rom_memory;
+ MemoryRegion *ram_memory;
+
+ pc_cpus_init(cpu_model);
+
+ /* FIXME: add kvm clock ? */
+
+ if (ram_size >= 0xe0000000) {
+ above_4g_mem_size = ram_size - 0xe0000000;
+ below_4g_mem_size = 0xe0000000;
+ } else {
+ above_4g_mem_size = 0;
+ below_4g_mem_size = ram_size;
+ }
+
+ /* pci enabled */
+ pci_memory = g_new(MemoryRegion, 1);
+ memory_region_init(pci_memory, "pci", INT64_MAX);
+ rom_memory = pci_memory;
+
+ /* allocate ram and load rom/bios */
+ pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
+ initrd_filename, below_4g_mem_size, above_4g_mem_size,
+ rom_memory, &ram_memory);
+
+ /* irq lines */
+ isa_irq = pc_isa_irq(&isa_irq_state);
+ ioapic_init(isa_irq_state);
+
+ pc_q35_init_early(isa_irq, isa_irq_state,
+ &gmch_host, &host_bus, &pci_bus, &lpc);
+ isa_bus_irqs(isa_irq);
+ pc_register_ferr_irq(isa_get_irq(13));
+
+ /* init basic PC hardware */
+ pc_basic_device_init(isa_irq, &rtc_state, false);
+
+ pc_q35_init_late(idebus, rtc_state, gmch_host, host_bus, pci_bus, lpc);
+
+ pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
+ idebus[0], idebus[1], rtc_state);
+
+ /* the rest devices to which pci devfn is automatically assigned */
+ pc_vga_init(host_bus);
+ audio_init(isa_irq, pci_bus);
+ pc_nic_init(pci_bus);
+ pc_pci_device_init(pci_bus);
+}
+
+static QEMUMachine pc_q35_machine = {
+ .name = "pc_q35",
+ .desc = "Q35 chipset PC",
+ .init = pc_q35_init,
+ .max_cpus = 255,
+};
+
+static void pc_q35_machine_init(void)
+{
+ qemu_register_machine(&pc_q35_machine);
+}
+
+machine_init(pc_q35_machine_init);
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 6deeac0..50744dd 100644
--- a/hw/pci_ids.h
+++ b/hw/pci_ids.h
@@ -36,6 +36,7 @@
#define PCI_CLASS_BRIDGE_HOST 0x0600
#define PCI_CLASS_BRIDGE_ISA 0x0601
#define PCI_CLASS_BRIDGE_PCI 0x0604
+#define PCI_CLASS_BRDIGE_PCI_INF_SUB 0x01
#define PCI_CLASS_BRIDGE_OTHER 0x0680
#define PCI_CLASS_COMMUNICATION_OTHER 0x0780
@@ -115,6 +116,17 @@
#define PCI_DEVICE_ID_INTEL_82371AB 0x7111
#define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112
#define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
+
+#define PCI_DEVICE_ID_INTEL_ICH9_0 0x2910
+#define PCI_DEVICE_ID_INTEL_ICH9_1 0x2917
+#define PCI_DEVICE_ID_INTEL_ICH9_2 0x2912
+#define PCI_DEVICE_ID_INTEL_ICH9_3 0x2913
+#define PCI_DEVICE_ID_INTEL_ICH9_4 0x2914
+#define PCI_DEVICE_ID_INTEL_ICH9_5 0x2919
+#define PCI_DEVICE_ID_INTEL_ICH9_6 0x2930
+#define PCI_DEVICE_ID_INTEL_ICH9_7 0x2916
+#define PCI_DEVICE_ID_INTEL_ICH9_8 0x2918
+
#define PCI_DEVICE_ID_INTEL_82801I_UHCI1 0x2934
#define PCI_DEVICE_ID_INTEL_82801I_UHCI2 0x2935
#define PCI_DEVICE_ID_INTEL_82801I_UHCI3 0x2936
@@ -125,6 +137,8 @@
#define PCI_DEVICE_ID_INTEL_82801I_EHCI2 0x293c
#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
+#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0
+
#define PCI_VENDOR_ID_XEN 0x5853
#define PCI_DEVICE_ID_XEN_PLATFORM 0x0001
diff --git a/hw/q35.c b/hw/q35.c
new file mode 100644
index 0000000..1776ac3
--- /dev/null
+++ b/hw/q35.c
@@ -0,0 +1,877 @@
+/*
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+/*
+ * QEMU GMCH/ICH9 PCI Bridge Emulation
+ *
+ * Copyright (c) 2009, 2010, 2011
+ * Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This is based on piix_pci.c, but heavily modified.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#include "hw.h"
+#include "range.h"
+#include "isa.h"
+#include "sysbus.h"
+#include "pc.h"
+#include "apm.h"
+#include "apic.h"
+#include "pci.h"
+#include "pcie_host.h"
+#include "pci_bridge.h"
+#include "pci_p2pbr.h"
+#include "q35.h"
+#include "acpi.h"
+#include "acpi_ich9.h"
+#include "pam.h"
+
+
+struct ICH9_LPCState;
+
+typedef struct ICH9_LPCIrqState {
+ struct ICH9_LPCState *lpc;
+ qemu_irq *pic;
+ qemu_irq *ioapic;
+} ICH9_LPCIrqState;
+
+typedef struct GMCH_PCIHost {
+ PCIExpressHost host;
+
+ PCIDevice *dev;
+ ICH9_LPCIrqState irq_state;
+} GMCH_PCIHost;
+
+typedef struct GMCH_PCIState {
+ PCIDevice d;
+ /*
+ * GMCH_PCIHost *gmch_host;
+ * In order to get GMCH_PCIHost
+ * PCIDevice -> qdev -> parent_bus -> qdev -upcast-> GMCH_PCIHost
+ */
+
+ PAM pam;
+} GMCH_PCIState;
+
+typedef struct ICH9_LPCState {
+ /* ICH9 LPC PCI to ISA bridge */
+ PCIDevice d;
+
+ /* (pci device, intx) -> pirq
+ * In real chipset case, the unused slots are never used
+ * as ICH9 supports only D25-D32 irq routing.
+ * On the other hand in qemu case, any slot/function can be populated
+ * via command line option.
+ * So fallback interrupt routing for any devices in any slots is necessary.
+ */
+ uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
+
+ APMState apm;
+ ICH9_LPCPmRegs pm;
+ uint32_t sci_level; /* track sci level */
+
+ /* 10.1 Chipset Configuration registers(Memory Space)
+ which is pointed by RCBA */
+ uint8_t chip_config[ICH9_CC_SIZE];
+ int rbca_index;
+} ICH9_LPCState;
+
+
+/****************************************************************************
+ * GMCH PCI host
+ */
+/* ich9 irq */
+static int ich9_lpc_map_irq(void *opaque, PCIDevice *pci_dev, int intx);
+static void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
+static int ich9_lpc_sci_irq(ICH9_LPCState *lpc);
+
+static GMCH_PCIHost *gmch_pcihost_from_qdev(DeviceState *gmch_host_qdev)
+{
+ SysBusDevice *sysdev = sysbus_from_qdev(gmch_host_qdev);
+ PCIHostState *pci = FROM_SYSBUS(PCIHostState, sysdev);
+ PCIExpressHost *pcie = DO_UPCAST(PCIExpressHost, pci, pci);
+ return DO_UPCAST(GMCH_PCIHost, host, pcie);
+}
+
+static int gmch_pcihost_initfn(SysBusDevice *dev)
+{
+ GMCH_PCIHost *s = gmch_pcihost_from_qdev(&dev->qdev);
+
+ pci_host_conf_register_ioport(GMCH_HOST_BRIDGE_CONFIG_ADDR, &s->host.pci);
+ pci_host_data_register_ioport(GMCH_HOST_BRIDGE_CONFIG_DATA, &s->host.pci);
+
+ if (pcie_host_init(&s->host) < 0) {
+ abort();
+ }
+
+ return 0;
+}
+
+static SysBusDeviceInfo gmch_pcihost_info = {
+ .init = gmch_pcihost_initfn,
+ .qdev.name = "gmch-pcihost",
+ .qdev.size = sizeof(GMCH_PCIHost),
+ .qdev.no_user = 1,
+ .qdev.props = (Property[]) {
+ {
+ .name = "MCFG",
+ .info = &qdev_prop_uint64,
+ .offset = offsetof(GMCH_PCIHost, host.base_addr),
+ .defval = (uint64_t[]){ GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT },
+ },
+ DEFINE_PROP_END_OF_LIST(),
+ },
+};
+
+/* host bridge */
+PCIBus *gmch_host_init(DeviceState **gmch_hostp,
+ qemu_irq *pic, qemu_irq *ioapic)
+{
+ DeviceState *dev;
+ GMCH_PCIHost *s;
+ PCIBus *b;
+
+ dev = qdev_create(NULL, "gmch-pcihost");
+ s = gmch_pcihost_from_qdev(dev);
+ s->irq_state.pic = pic;
+ s->irq_state.ioapic = ioapic;
+
+ b = pci_bus_new(dev, "pcie.0", 0);
+ pci_bus_irqs(b, ich9_lpc_set_irq, ich9_lpc_map_irq, &s->irq_state,
+ ICH9_LPC_NB_PIRQS);
+ s->host.pci.bus = b;
+ qdev_init_nofail(dev);
+
+ *gmch_hostp = dev;
+ return b;
+}
+
+
+/****************************************************************************
+ * GMCH
+ */
+static GMCH_PCIState *gmch_from_pci(PCIDevice *gmch_pci)
+{
+ return DO_UPCAST(GMCH_PCIState, d, gmch_pci);
+}
+
+/* PCIE MMCFG */
+static void gmch_update_pciexbar(GMCH_PCIState *gs)
+{
+ PCIDevice *pci_dev = &gs->d;
+ BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
+ DeviceState *qdev = bus->parent;
+ GMCH_PCIHost *s = gmch_pcihost_from_qdev(qdev);
+
+ uint64_t pciexbar;
+ int enable;
+ uint64_t addr;
+ uint64_t addr_mask;
+ uint32_t length;
+
+ pciexbar = pci_get_quad(pci_dev->config + GMCH_HOST_BRIDGE_PCIEXBAR);
+ enable = pciexbar & GMCH_HOST_BRIDGE_PCIEXBAREN;
+
+ addr_mask = GMCH_HOST_BRIDGE_PCIEXBAR_ADMSK;
+ switch (pciexbar & GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) {
+ case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M:
+ length = 256 * 1024 * 1024;
+ break;
+ case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M:
+ length = 128 * 1024 * 1024;
+ addr_mask |= GMCH_HOST_BRIDGE_PCIEXBAR_128ADMSK |
+ GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
+ break;
+ case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M:
+ length = 64 * 1024 * 1024;
+ addr_mask |= GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK;
+ break;
+ case GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD:
+ default:
+ enable = 0;
+ length = 0;
+ abort();
+ break;
+ }
+ addr = pciexbar & addr_mask;
+
+ pcie_host_mmcfg_update(&s->host, enable, addr, length);
+}
+
+/* PAM */
+static void gmch_update_pam(GMCH_PCIState *gs)
+{
+ int i;
+ for (i = 0; i <= PAM_IDX_MAX; i++) {
+ pam_update(&gs->pam, i, gs->d.config[GMCH_HOST_BRIDGE_PAM0 + i]);
+ }
+}
+
+/* SMRAM */
+static void gmch_update_smram(GMCH_PCIState *gs)
+{
+ smram_update(&gs->pam, gs->d.config[GMCH_HOST_BRDIGE_SMRAM]);
+}
+
+static void gmch_set_smm(int smm, void *arg)
+{
+ GMCH_PCIState *gs = arg;
+ smram_set_smm(&gs->pam, smm, gs->d.config[GMCH_HOST_BRDIGE_SMRAM]);
+}
+
+static void gmch_write_config(PCIDevice *d,
+ uint32_t address, uint32_t val, int len)
+{
+ GMCH_PCIState *gs = gmch_from_pci(d);
+
+ /* XXX: implement SMRAM.D_LOCK */
+ pci_default_write_config(d, address, val, len);
+
+ if (ranges_overlap(address, len, GMCH_HOST_BRIDGE_PAM0,
+ GMCH_HOST_BRIDGE_PAM_SIZE)) {
+ gmch_update_pam(gs);
+ }
+
+ if (ranges_overlap(address, len, GMCH_HOST_BRIDGE_PCIEXBAR,
+ GMCH_HOST_BRIDGE_PCIEXBAR_SIZE)) {
+ gmch_update_pciexbar(gs);
+ }
+
+ if (ranges_overlap(address, len, GMCH_HOST_BRDIGE_SMRAM,
+ GMCH_HOST_BRDIGE_SMRAM_SIZE)) {
+ gmch_update_smram(gs);
+ }
+}
+
+static void gmch_update(GMCH_PCIState *gs)
+{
+ gmch_update_pciexbar(gs);
+ gmch_update_pam(gs);
+ gmch_update_smram(gs);
+}
+
+static int gmch_post_load(void *opaque, int version_id)
+{
+ GMCH_PCIState *gs = opaque;
+ gmch_update(gs);
+ return 0;
+}
+
+static const VMStateDescription vmstate_gmch = {
+ .name = "gmch",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .post_load = gmch_post_load,
+ .fields = (VMStateField []) {
+ VMSTATE_PCI_DEVICE(d, GMCH_PCIState),
+ VMSTATE_UINT8(pam.smm_enabled, GMCH_PCIState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void gmch_reset(DeviceState *qdev)
+{
+ PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
+ GMCH_PCIState *gs = gmch_from_pci(d);
+
+ pci_set_quad(d->config + GMCH_HOST_BRIDGE_PCIEXBAR,
+ GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
+
+ d->config[GMCH_HOST_BRDIGE_SMRAM] = GMCH_HOST_BRIDGE_SMRAM_DEFAULT;
+
+ gmch_update(gs);
+}
+
+static int gmch_initfn(PCIDevice *d)
+{
+ GMCH_PCIState *gs = gmch_from_pci(d);
+
+ pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
+ pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_Q35_MCH);
+ pci_config_set_revision(d->config, GMCH_HOST_BRIDGE_REVISION_DEFUALT);
+ pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
+
+ cpu_smm_register(&gmch_set_smm, gs);
+ pam_init_memory_mappings(&gs->pam);
+
+ return 0;
+}
+
+static PCIDeviceInfo gmch_info = {
+ .qdev.name = "gmch",
+ .qdev.desc = "Host bridge",
+ .qdev.size = sizeof(GMCH_PCIState),
+ .qdev.vmsd = &vmstate_gmch,
+ .qdev.no_user = 1,
+ .init = gmch_initfn,
+ .config_write = gmch_write_config,
+ .qdev.reset = gmch_reset,
+};
+
+/* host bridge */
+PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b)
+{
+ GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
+ PCIDevice *d;
+
+ d = pci_create_simple_multifunction(b, 0, false, "gmch");
+ s->dev = d;
+
+ return d;
+}
+
+/*****************************************************************************/
+/* ICH9 DMI-to-PCI bridge */
+#define I82801ba_SSVID_OFFSET 0x50
+#define I82801ba_SSVID_SVID 0
+#define I82801ba_SSVID_SSID 0
+
+static PCIBridge *i82801ba11_init(PCIBus *bus, int devfn, const char *bus_name,
+ bool multifunction)
+{
+ const PCIP2PBridgeInit init = {
+ .bus = bus,
+ .devfn = devfn,
+ .multifunction = multifunction,
+
+ .bus_name = bus_name,
+ .map_irq = pci_swizzle_map_irq_fn,
+ };
+ const PCIP2PBridgeProp prop = {
+ .vendor_id = PCI_VENDOR_ID_INTEL,
+ .device_id = PCI_DEVICE_ID_INTEL_82801BA_11,
+ .revision_id = ICH9_D2P_A2_REVISION,
+ .prog_interface = PCI_CLASS_BRDIGE_PCI_INF_SUB,
+
+ .ssvid_cap = I82801ba_SSVID_OFFSET,
+ .svid = I82801ba_SSVID_SVID,
+ .ssid = I82801ba_SSVID_SSID,
+ };
+ return pci_p2pbr_create_simple(&init, &prop);
+}
+
+PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus)
+{
+ PCIBridge *br;
+ char buf[16];
+
+ snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
+ br = i82801ba11_init(bus, devfn, buf, true);
+ if (br == NULL) {
+ return NULL;
+ }
+ return pci_bridge_get_sec_bus(br);
+}
+
+
+/*****************************************************************************/
+/* ICH9 LPC PCI to ISA bridge */
+
+static void ich9_lpc_reset(DeviceState *qdev);
+
+static ICH9_LPCState *ich9_lpc_from_pci(PCIDevice *lpc_pci)
+{
+ return DO_UPCAST(ICH9_LPCState, d, lpc_pci);
+}
+
+/* chipset configuration register
+ * to access chipset configuration registers, pci_[sg]et_{byte, word, long}
+ * are used.
+ * Although it's not pci configuration space, it's little endian as Intel.
+ */
+
+static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
+{
+ int intx;
+ for (intx = 0; intx < PCI_NUM_PINS; intx++) {
+ irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK;
+ }
+}
+
+static void ich9_cc_update(ICH9_LPCState *lpc)
+{
+ int slot;
+ int reg_offset;
+ int intx;
+
+ /* D{25 - 31}IR, but D30IR is read only to 0. */
+ for (slot = 25, reg_offset = 0; slot < 32; slot++, reg_offset++) {
+ if (slot != 30) {
+ ich9_cc_update_ir(lpc->irr[slot],
+ lpc->chip_config[ICH9_CC_D31IR + reg_offset]);
+ }
+ }
+
+ /*
+ * D30: DMI2PCI bridge
+ * It is arbitrarily decided how INTx lines of PCI devicesbehind the bridge
+ * are connected to pirq lines. Our choice is PIRQ[E-H].
+ * INT[A-D] are connected to PIRQ[E-H]
+ */
+ for (intx = 0; intx < PCI_NUM_PINS; intx++) {
+ lpc->irr[30][intx] = intx + 4;
+ }
+}
+
+static void ich9_cc_init(ICH9_LPCState *lpc)
+{
+ int slot;
+ int intx;
+
+ /* the default irq routing is arbitrary as long as it matches with
+ * acpi irq routing table.
+ * The one that is incompatible with piix_pci(= bochs) one is
+ * intentionally chosen to let the users know that the different
+ * board is used.
+ *
+ * int[A-D] -> pirq[E-F]
+ * avoid pirq A-D because they are used for pci express port
+ */
+ for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
+ for (intx = 0; intx < PCI_NUM_PINS; intx++) {
+ lpc->irr[slot][intx] = (slot + intx) % 4 + 4;
+ }
+ }
+ ich9_cc_update(lpc);
+}
+
+static void ich9_cc_reset(ICH9_LPCState *lpc)
+{
+ uint8_t *c = lpc->chip_config;
+
+ memset(lpc->chip_config, 0, sizeof(lpc->chip_config));
+
+ pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT);
+ pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT);
+ pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT);
+ pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT);
+ pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT);
+ pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT);
+ pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT);
+
+ ich9_cc_update(lpc);
+}
+
+static void ich9_cc_addr_len(uint32_t *addr, int *len)
+{
+ *addr &= ICH9_CC_ADDR_MASK;
+ if (*addr + *len >= ICH9_CC_SIZE) {
+ *len = ICH9_CC_SIZE - *addr;
+ }
+}
+
+/* val: little endian */
+static void ich9_cc_write(ICH9_LPCState *lpc, uint32_t addr,
+ uint32_t val, int len)
+{
+ ich9_cc_addr_len(&addr, &len);
+ memcpy(lpc->chip_config + addr, &val, len);
+}
+
+/* return value: little endian */
+static uint32_t ich9_cc_read(ICH9_LPCState *lpc, uint32_t addr, int len)
+{
+ uint32_t val = 0;
+ ich9_cc_addr_len(&addr, &len);
+ memcpy(&val, lpc->chip_config + addr, len);
+ return val;
+}
+
+#define ICH9_CC_MMIO_WRITE(type, len) \
+ static void ich9_cc_mmio_write ## type \
+ (void *opaque, target_phys_addr_t addr, uint32_t val) \
+ { \
+ ich9_cc_write(opaque, addr, val, len); \
+ }
+
+#define ICH9_CC_MMIO_READ(type, len) \
+ static uint32_t ich9_cc_mmio_read ## type \
+ (void *opaque, target_phys_addr_t addr) \
+ { \
+ return ich9_cc_read(opaque, addr, len); \
+ }
+
+ICH9_CC_MMIO_WRITE(b, 1)
+ICH9_CC_MMIO_WRITE(w, 2)
+ICH9_CC_MMIO_WRITE(l, 4)
+
+ICH9_CC_MMIO_READ(b, 1)
+ICH9_CC_MMIO_READ(w, 2)
+ICH9_CC_MMIO_READ(l, 4)
+
+static CPUWriteMemoryFunc * const ich9_cc_mmio_write[] = {
+ ich9_cc_mmio_writeb,
+ ich9_cc_mmio_writew,
+ ich9_cc_mmio_writel,
+};
+
+static CPUReadMemoryFunc * const ich9_cc_mmio_read[] = {
+ ich9_cc_mmio_readb,
+ ich9_cc_mmio_readw,
+ ich9_cc_mmio_readl,
+};
+
+/* IRQ routing */
+/* */
+static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis)
+{
+ *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK;
+ *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN;
+}
+
+static void ich9_lpc_pic_irq(ICH9_LPCState *lpc, int irq_num,
+ int *pic_irq, int *pic_dis)
+{
+ switch (irq_num) {
+ case 0 ... 3: /* A-D */
+ ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + irq_num],
+ pic_irq, pic_dis);
+ return;
+ case 4 ... 7: /* E-H */
+ ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (irq_num - 4)],
+ pic_irq, pic_dis);
+ return;
+ default:
+ break;
+ }
+ abort();
+}
+
+/* pic_irq: i8254 irq 0-15 */
+static void ich9_lpc_update_pic(ICH9_LPCIrqState *irq_state, int pic_irq)
+{
+ GMCH_PCIHost *s = container_of(irq_state, GMCH_PCIHost, irq_state);
+ ICH9_LPCState *lpc = irq_state->lpc;
+ int i, pic_level;
+
+ /* The pic level is the logical OR of all the PCI irqs mapped to it */
+ pic_level = 0;
+ for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) {
+ int tmp_irq;
+ int tmp_dis;
+ ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis);
+ if (!tmp_dis && pic_irq == tmp_irq) {
+ pic_level |= pci_bus_get_irq_level(s->host.pci.bus, i);
+ }
+ }
+ if (pic_irq == ich9_lpc_sci_irq(lpc)) {
+ pic_level |= lpc->sci_level;
+ }
+
+ qemu_set_irq(irq_state->pic[pic_irq], pic_level);
+}
+
+/* pirq: pirq[A-H] 0-7*/
+static void ich9_lpc_update_by_pirq(ICH9_LPCIrqState *irq_state, int pirq)
+{
+ ICH9_LPCState *lpc = irq_state->lpc;
+ int pic_irq;
+ int pic_dis;
+
+ ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis);
+ assert(pic_irq < ICH9_LPC_PIC_NUM_PINS);
+ if (pic_dis) {
+ return;
+ }
+
+ ich9_lpc_update_pic(irq_state, pic_irq);
+}
+
+/* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */
+static int ich9_pirq_to_gsi(int pirq)
+{
+ return pirq + ICH9_LPC_PIC_NUM_PINS;
+}
+
+static int ich9_gsi_to_pirq(int gsi)
+{
+ return gsi - ICH9_LPC_PIC_NUM_PINS;
+}
+
+static void ich9_lpc_update_apic(ICH9_LPCIrqState *irq_state, int gsi)
+{
+ GMCH_PCIHost *s = container_of(irq_state, GMCH_PCIHost, irq_state);
+ ICH9_LPCState *lpc = irq_state->lpc;
+ int level;
+
+ level = pci_bus_get_irq_level(s->host.pci.bus, ich9_gsi_to_pirq(gsi));
+ if (gsi == ich9_lpc_sci_irq(lpc)) {
+ level |= lpc->sci_level;
+ }
+
+ qemu_set_irq(irq_state->ioapic[gsi], level);
+}
+
+/* return the pirq number (PIRQ[A-H]:0-7) corresponding to
+ a given device irq pin. */
+static int ich9_lpc_map_irq(void *opaque, PCIDevice *pci_dev, int intx)
+{
+ ICH9_LPCIrqState *irq_state = opaque;
+ return irq_state->lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
+}
+
+static void ich9_lpc_set_irq(void *opaque, int pirq, int level)
+{
+ ICH9_LPCIrqState *irq_state = opaque;
+
+ assert(0 <= pirq);
+ assert(pirq < ICH9_LPC_NB_PIRQS);
+
+ ich9_lpc_update_apic(irq_state, ich9_pirq_to_gsi(pirq));
+ ich9_lpc_update_by_pirq(irq_state, pirq);
+}
+
+static int ich9_lpc_sci_irq(ICH9_LPCState *lpc)
+{
+ switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] &
+ ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) {
+ case ICH9_LPC_ACPI_CTRL_9:
+ return 9;
+ case ICH9_LPC_ACPI_CTRL_10:
+ return 10;
+ case ICH9_LPC_ACPI_CTRL_11:
+ return 11;
+ case ICH9_LPC_ACPI_CTRL_20:
+ return 20;
+ case ICH9_LPC_ACPI_CTRL_21:
+ return 21;
+ default:
+ /* reserved */
+ break;
+ }
+ return -1;
+}
+
+static void ich9_set_sci(void *opaque, int irq_num, int level)
+{
+ ICH9_LPCIrqState *irq_state = opaque;
+ ICH9_LPCState *lpc = irq_state->lpc;
+ int irq;
+
+ assert(irq_num == 0);
+ level = !!level;
+ if (level == lpc->sci_level) {
+ return;
+ }
+ lpc->sci_level = level;
+
+ irq = ich9_lpc_sci_irq(lpc);
+ if (irq < 0) {
+ return;
+ }
+
+ ich9_lpc_update_apic(irq_state, irq);
+ if (irq < ICH9_LPC_PIC_NUM_PINS) {
+ ich9_lpc_update_pic(irq_state, irq);
+ }
+}
+
+void ich9_lpc_pm_init(DeviceState *gmch_host, PCIDevice *lpc_pci,
+ qemu_irq cmos_s3)
+{
+ GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
+ ICH9_LPCState *lpc = ich9_lpc_from_pci(lpc_pci);
+ qemu_irq *sci_irq;
+
+ sci_irq = qemu_allocate_irqs(ich9_set_sci, &s->irq_state, 1);
+ ich9_pm_init(&lpc->pm, sci_irq[0], cmos_s3);
+
+ ich9_lpc_reset(&lpc->d.qdev);
+}
+
+/* APM */
+static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
+{
+ ICH9_LPCState *lpc = arg;
+
+ /* ACPI specs 3.0, 4.7.2.5 */
+ acpi_pm1_cnt_update(&lpc->pm.pm1_cnt,
+ val == ICH9_APM_ACPI_ENABLE,
+ val == ICH9_APM_ACPI_DISABLE);
+
+ /* SMI_EN = PMBASE + 30. SMI control and enable register */
+ if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) {
+ cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
+ }
+}
+
+/* config:PMBASE */
+static void
+ich9_lpc_pmbase_update(ICH9_LPCState *lpc)
+{
+ uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE);
+ pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK;
+
+ ich9_pm_iospace_update(&lpc->pm, pm_io_base);
+}
+
+/* config:RBCA */
+static void ich9_lpc_rcba_update(ICH9_LPCState *lpc, uint32_t rbca_old)
+{
+ uint32_t rbca = pci_get_long(lpc->d.config + ICH9_LPC_RCBA);
+
+ if (rbca_old & ICH9_LPC_RCBA_EN) {
+ cpu_register_physical_memory(rbca_old & ICH9_LPC_RCBA_BA_MASK,
+ ICH9_CC_SIZE, IO_MEM_UNASSIGNED);
+ }
+ if (rbca & ICH9_LPC_RCBA_EN) {
+ cpu_register_physical_memory(rbca & ICH9_LPC_RCBA_BA_MASK,
+ ICH9_CC_SIZE, lpc->rbca_index);
+ }
+}
+
+static int ich9_lpc_post_load(void *opaque, int version_id)
+{
+ ICH9_LPCState *lpc = opaque;
+
+ ich9_lpc_pmbase_update(lpc);
+ ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RBCA_EN */);
+ return 0;
+}
+
+static void ich9_lpc_config_write(PCIDevice *d,
+ uint32_t addr, uint32_t val, int len)
+{
+ ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
+ uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA);
+
+ pci_default_write_config(d, addr, val, len);
+ if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4)) {
+ ich9_lpc_pmbase_update(lpc);
+ }
+ if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) {
+ ich9_lpc_rcba_update(lpc, rbca_old);
+ }
+}
+
+static void ich9_lpc_reset(DeviceState *qdev)
+{
+ PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
+ ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
+ uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA);
+ int i;
+
+ for (i = 0; i < 4; i++) {
+ pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i,
+ ICH9_LPC_PIRQ_ROUT_DEFAULT);
+ }
+ for (i = 0; i < 4; i++) {
+ pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i,
+ ICH9_LPC_PIRQ_ROUT_DEFAULT);
+ }
+ pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT);
+
+ pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT);
+ pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT);
+
+ ich9_cc_reset(lpc);
+
+ ich9_lpc_pmbase_update(lpc);
+ ich9_lpc_rcba_update(lpc, rbca_old);
+
+ lpc->sci_level = 0;
+}
+
+static int ich9_lpc_initfn(PCIDevice *d)
+{
+ ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
+
+ isa_bus_new(&d->qdev);
+ pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
+ pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_ICH9_8); /* ICH9 LPC */
+ pci_config_set_revision(d->config, ICH9_A2_LPC_REVISION);
+ pci_config_set_class(d->config, PCI_CLASS_BRIDGE_ISA);
+
+ pci_set_long(d->wmask + ICH9_LPC_PMBASE,
+ ICH9_LPC_PMBASE_BASE_ADDRESS_MASK);
+
+ lpc->rbca_index = cpu_register_io_memory(ich9_cc_mmio_read,
+ ich9_cc_mmio_write,
+ lpc, DEVICE_LITTLE_ENDIAN);
+
+ ich9_cc_init(lpc);
+ apm_init(&lpc->apm, ich9_apm_ctrl_changed, lpc);
+ return 0;
+}
+
+static const VMStateDescription vmstate_ich9_lpc = {
+ .name = "ICH9LPC",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .post_load = ich9_lpc_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_PCI_DEVICE(d, ICH9_LPCState),
+ VMSTATE_STRUCT(apm, ICH9_LPCState, 0, vmstate_apm, APMState),
+ VMSTATE_STRUCT(pm, ICH9_LPCState, 0, vmstate_ich9_pm, ICH9_LPCPmRegs),
+ VMSTATE_UINT8_ARRAY(chip_config, ICH9_LPCState, ICH9_CC_SIZE),
+ VMSTATE_UINT32(sci_level, ICH9_LPCState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+PCIDevice *gmch_lpc_init(DeviceState *gmch_host, PCIBus *bus)
+{
+ GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
+ PCIDevice *d;
+ ICH9_LPCState *lpc;
+
+ d = pci_create_simple_multifunction(bus, PCI_DEVFN(ICH9_LPC_DEV,
+ ICH9_LPC_FUNC),
+ true, "ICH9 LPC");
+ lpc = ich9_lpc_from_pci(d);
+ s->irq_state.lpc = lpc;
+ return &lpc->d;
+}
+
+static PCIDeviceInfo ich9_lpc_info = {
+ .qdev.name = "ICH9 LPC",
+ .qdev.desc = "ICH9 LPC bridge",
+ .qdev.size = sizeof(ICH9_LPCState),
+ .qdev.vmsd = &vmstate_ich9_lpc,
+ .qdev.no_user = 1,
+ .init = ich9_lpc_initfn,
+ .config_write = ich9_lpc_config_write,
+ .qdev.reset = ich9_lpc_reset,
+};
+
+static void q35_register(void)
+{
+ sysbus_register_withprop(&gmch_pcihost_info);
+ pci_qdev_register(&gmch_info);
+ pci_qdev_register(&ich9_lpc_info);
+}
+device_init(q35_register);
diff --git a/hw/q35.h b/hw/q35.h
new file mode 100644
index 0000000..be2e96b
--- /dev/null
+++ b/hw/q35.h
@@ -0,0 +1,272 @@
+/*
+ * q35.h
+ *
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+
+#ifndef HW_Q35_H
+#define HW_Q35_H
+
+#include "sysbus.h"
+#include "acpi_ich9.h"
+
+PCIBus *gmch_host_init(DeviceState **gmch_hostp,
+ qemu_irq *pic, qemu_irq *ioapic);
+
+PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b);
+PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus);
+PCIDevice *gmch_lpc_init(DeviceState *gmch_host, PCIBus *bus);
+void ich9_lpc_pm_init(DeviceState *gmch_host, PCIDevice *pci_lpc,
+ qemu_irq cmos_s3);
+
+i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
+
+#define Q35_MASK(bit, ms_bit, ls_bit) \
+((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
+
+/*
+ * gmch part
+ */
+
+/* PCI configuration */
+#define GMCH_HOST_BRIDGE "GMCH"
+
+#define GMCH_HOST_BRIDGE_CONFIG_ADDR 0xcf8
+#define GMCH_HOST_BRIDGE_CONFIG_DATA 0xcfc
+
+/* D0:F0 configuration space */
+#define GMCH_HOST_BRIDGE_REVISION_DEFUALT 0x0
+
+#define GMCH_HOST_BRIDGE_PCIEXBAR 0x60 /* 64bit register */
+#define GMCH_HOST_BRIDGE_PCIEXBAR_SIZE 8 /* 64bit register */
+#define GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT 0xe0000000
+#define GMCH_HOST_BRIDGE_PCIEXBAR_ADMSK Q35_MASK(64, 35, 25) /* bit 35:28 */
+#define GMCH_HOST_BRIDGE_PCIEXBAR_128ADMSK ((uint64_t)(1 << 26))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_64ADMSK ((uint64_t)(1 << 25))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK ((uint64_t)(0x3 << 1))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M ((uint64_t)(0x0 << 1))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M ((uint64_t)(0x1 << 1))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M ((uint64_t)(0x2 << 1))
+#define GMCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD ((uint64_t)(0x3 << 1))
+#define GMCH_HOST_BRIDGE_PCIEXBAREN ((uint64_t)1)
+
+#define GMCH_HOST_BRIDGE_PAM_NB 7
+#define GMCH_HOST_BRIDGE_PAM_SIZE 7
+#define GMCH_HOST_BRIDGE_PAM0 0x90
+#define GMCH_HOST_BRIDGE_PAM_BIOS_AREA 0xf0000
+#define GMCH_HOST_BRIDGE_PAM_AREA_SIZE 0x10000 /* 16KB */
+#define GMCH_HOST_BRIDGE_PAM1 0x91
+#define GMCH_HOST_BRIDGE_PAM_EXPAN_AREA 0xc0000
+#define GMCH_HOST_BRIDGE_PAM_EXPAN_SIZE 0x04000
+#define GMCH_HOST_BRIDGE_PAM2 0x92
+#define GMCH_HOST_BRIDGE_PAM3 0x93
+#define GMCH_HOST_BRIDGE_PAM4 0x94
+#define GMCH_HOST_BRIDGE_PAM_EXBIOS_AREA 0xe0000
+#define GMCH_HOST_BRIDGE_PAM_EXBIOS_SIZE 0x04000
+#define GMCH_HOST_BRIDGE_PAM5 0x95
+#define GMCH_HOST_BRIDGE_PAM6 0x96
+#define GMCH_HOST_BRIDGE_PAM_WE_HI ((uint8_t)(0x2 << 4))
+#define GMCH_HOST_BRIDGE_PAM_RE_HI ((uint8_t)(0x1 << 4))
+#define GMCH_HOST_BRIDGE_PAM_HI_MASK ((uint8_t)(0x3 << 4))
+#define GMCH_HOST_BRIDGE_PAM_WE_LO ((uint8_t)0x2)
+#define GMCH_HOST_BRIDGE_PAM_RE_LO ((uint8_t)0x1)
+#define GMCH_HOST_BRIDGE_PAM_LO_MASK ((uint8_t)0x3)
+#define GMCH_HOST_BRIDGE_PAM_WE ((uint8_t)0x2)
+#define GMCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1)
+#define GMCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3)
+
+#define GMCH_HOST_BRDIGE_SMRAM 0x9d
+#define GMCH_HOST_BRDIGE_SMRAM_SIZE 1
+#define GMCH_HOST_BRIDGE_SMRAM_DEFAULT ((uint8_t)0x2)
+#define GMCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6))
+#define GMCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5))
+#define GMCH_HOST_BRIDGE_SMRAM_D_LCK ((uint8_t)(1 << 4))
+#define GMCH_HOST_BRIDGE_SMRAM_G_SMRAME ((uint8_t)(1 << 3))
+#define GMCH_HOST_BRIDGE_SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
+#define GMCH_HOST_BRIDGE_SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */
+#define GMCH_HOST_BRIDGE_SMRAM_C_BASE 0xa0000
+#define GMCH_HOST_BRIDGE_SMRAM_C_END 0xc0000
+#define GMCH_HOST_BRIDGE_SMRAM_C_SIZE 0x20000
+#define GMCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000
+
+#define GMCH_HOST_BRIDGE_ESMRAMC 0x9e
+#define GMCH_HOST_BRDIGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6))
+#define GMCH_HOST_BRDIGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5))
+#define GMCH_HOST_BRDIGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4))
+#define GMCH_HOST_BRDIGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3))
+#define GMCH_HOST_BRDIGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2))
+#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
+#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
+#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
+#define GMCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
+#define GMCH_HOST_BRDIGE_ESMRAMC_T_EN ((uint8_t)1)
+
+/* D1:F0 PCIE* port*/
+#define GMCH_PCIE_DEV 1
+#define GMCH_PCIE_FUNC 0
+
+/*
+ * ich9 part
+ */
+
+/* ICH9: Chipset Configuration Registers */
+#define ICH9_CC_SIZE (16 * 1024) /* 16KB */
+#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
+
+#define ICH9_CC
+#define ICH9_CC_D28IP 0x310C
+#define ICH9_CC_D28IP_SHIFT 4
+#define ICH9_CC_D28IP_MASK 0xf
+#define ICH9_CC_D28IP_DEFAULT 0x00214321
+#define ICH9_CC_D31IR 0x3140
+#define ICH9_CC_D30IR 0x3142
+#define ICH9_CC_D29IR 0x3144
+#define ICH9_CC_D28IR 0x3146
+#define ICH9_CC_D27IR 0x3148
+#define ICH9_CC_D26IR 0x314C
+#define ICH9_CC_D25IR 0x3150
+#define ICH9_CC_DIR_DEFAULT 0x3210
+#define ICH9_CC_D30IR_DEFAULT 0x0
+#define ICH9_CC_DIR_SHIFT 4
+#define ICH9_CC_DIR_MASK 0x7
+#define ICH9_CC_OIC 0x31FF
+#define ICH9_CC_OIC_AEN 0x1
+
+/* D28:F[0-5] */
+#define ICH9_PCIE_DEV 28
+#define ICH9_PCIE_FUNC_MAX 6
+
+
+/* D29:F0 USB UHCI Controller #1 */
+#define ICH9_USB_UHCI1_DEV 29
+#define ICH9_USB_UHCI1_FUNC 0
+
+/* D30:F0 DMI-to-PCI brdige */
+#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
+#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
+
+#define ICH9_D2P_BRIDGE_DEV 30
+#define ICH9_D2P_BRIDGE_FUNC 0
+
+#define ICH9_D2P_SECONDARY_DEFAULT (256 - 8)
+
+#define ICH9_D2P_A2_REVISION 0x92
+
+
+/* D31:F1 LPC controller */
+#define ICH9_A2_LPC "ICH9 A2 LPC"
+#define ICH9_A2_LPC_SAVEVM_VERSION 0
+
+#define ICH9_LPC_DEV 31
+#define ICH9_LPC_FUNC 0
+
+#define ICH9_A2_LPC_REVISION 0x2
+#define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */
+
+#define ICH9_LPC_PMBASE 0x40
+#define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
+#define ICH9_LPC_PMBASE_RTE 0x1
+#define ICH9_LPC_PMBASE_DEFAULT 0x1
+#define ICH9_LPC_ACPI_CTRL 0x44
+#define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
+#define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
+#define ICH9_LPC_ACPI_CTRL_9 0x0
+#define ICH9_LPC_ACPI_CTRL_10 0x1
+#define ICH9_LPC_ACPI_CTRL_11 0x2
+#define ICH9_LPC_ACPI_CTRL_20 0x4
+#define ICH9_LPC_ACPI_CTRL_21 0x5
+#define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0
+
+#define ICH9_LPC_PIRQA_ROUT 0x60
+#define ICH9_LPC_PIRQB_ROUT 0x61
+#define ICH9_LPC_PIRQC_ROUT 0x62
+#define ICH9_LPC_PIRQD_ROUT 0x63
+
+#define ICH9_LPC_PIRQE_ROUT 0x68
+#define ICH9_LPC_PIRQF_ROUT 0x69
+#define ICH9_LPC_PIRQG_ROUT 0x6a
+#define ICH9_LPC_PIRQH_ROUT 0x6b
+
+#define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
+#define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
+#define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
+
+#define ICH9_LPC_RCBA 0xf0
+#define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
+#define ICH9_LPC_RCBA_EN 0x1
+#define ICH9_LPC_RCBA_DEFAULT 0x0
+
+#define ICH9_LPC_PIC_NUM_PINS 16
+#define ICH9_LPC_IOAPIC_NUM_PINS 24
+
+/* D31:F2 SATA Controller #1 */
+#define ICH9_SATA1_DEV 31
+#define ICH9_SATA1_FUNC 2
+
+/* D30:F1 power management I/O registers
+ offset from the address ICH9_LPC_PMBASE */
+
+/* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
+#define ICH9_PMIO_SIZE 128
+#define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1)
+
+#define ICH9_PMIO_PM1_STS 0x00
+#define ICH9_PMIO_PM1_EN 0x02
+#define ICH9_PMIO_PM1_CNT 0x04
+#define ICH9_PMIO_PM1_TMR 0x08
+#define ICH9_PMIO_GPE0_STS 0x20
+#define ICH9_PMIO_GPE0_EN 0x28
+#define ICH9_PMIO_GPE0_LEN 16
+#define ICH9_PMIO_SMI_EN 0x30
+#define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
+#define ICH9_PMIO_SMI_STS 0x34
+
+/* FADT ACPI_ENABLE/ACPI_DISABLE */
+#define ICH9_APM_ACPI_ENABLE 0x2
+#define ICH9_APM_ACPI_DISABLE 0x3
+
+
+/* D31:F3 SMBus controller */
+#define ICH9_A2_SMB_REVISION 0x02
+#define ICH9_SMB_PI 0x00
+
+#define ICH9_SMB_SMBMBAR0 0x10
+#define ICH9_SMB_SMBMBAR1 0x14
+#define ICH9_SMB_SMBM_BAR 0
+#define ICH9_SMB_SMBM_SIZE (1 << 8)
+#define ICH9_SMB_SMB_BASE 0x20
+#define ICH9_SMB_SMB_BASE_BAR 4
+#define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
+#define ICH9_SMB_HOSTC 0x40
+#define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
+#define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
+#define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
+#define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
+
+/* D31:F3 SMBus I/O and memory mapped I/O registers */
+#define ICH9_SMB_DEV 31
+#define ICH9_SMB_FUNC 3
+
+#define ICH9_SMB_HST_STS 0x00
+#define ICH9_SMB_HST_CNT 0x02
+#define ICH9_SMB_HST_CMD 0x03
+#define ICH9_SMB_XMIT_SLVA 0x04
+#define ICH9_SMB_HST_D0 0x05
+#define ICH9_SMB_HST_D1 0x06
+#define ICH9_SMB_HOST_BLOCK_DB 0x07
+
+#endif /* HW_Q35_H */
diff --git a/hw/q35_smbus.c b/hw/q35_smbus.c
new file mode 100644
index 0000000..fe445ac
--- /dev/null
+++ b/hw/q35_smbus.c
@@ -0,0 +1,154 @@
+/*
+ * ACPI implementation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
+ */
+/*
+ * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This is based on acpi.c, but heavily rewritten.
+ */
+#include "hw.h"
+#include "pc.h"
+#include "pm_smbus.h"
+#include "pci.h"
+#include "sysemu.h"
+#include "i2c.h"
+#include "smbus.h"
+
+#include "q35.h"
+
+typedef struct ICH9_SMBState {
+ PCIDevice dev;
+
+ PMSMBus smb;
+} ICH9_SMBState;
+
+static ICH9_SMBState *ich9_pci_to_smb(PCIDevice* pci_dev)
+{
+ return DO_UPCAST(ICH9_SMBState, dev, pci_dev);
+}
+
+static const VMStateDescription vmstate_ich9_smbus = {
+ .name = "ich9_smb",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_PCI_DEVICE(dev, struct ICH9_SMBState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void ich9_smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+ ICH9_SMBState *s = opaque;
+ uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
+
+ if ((hostc & ICH9_SMB_HOSTC_HST_EN) && !(hostc & ICH9_SMB_HOSTC_I2C_EN)) {
+ uint64_t offset = addr - s->dev.io_regions[ICH9_SMB_SMB_BASE_BAR].addr;
+ smb_ioport_writeb(&s->smb, offset, val);
+ }
+}
+
+static uint32_t ich9_smb_ioport_readb(void *opaque, uint32_t addr)
+{
+ ICH9_SMBState *s = opaque;
+ uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
+
+ if ((hostc & ICH9_SMB_HOSTC_HST_EN) && !(hostc & ICH9_SMB_HOSTC_I2C_EN)) {
+ uint64_t offset = addr - s->dev.io_regions[ICH9_SMB_SMB_BASE_BAR].addr;
+ return smb_ioport_readb(&s->smb, offset);
+ }
+
+ return 0xff;
+}
+
+static void ich9_smb_map_ioport(PCIDevice *dev, int region_num,
+ uint64_t addr, uint64_t size, int type)
+{
+ ICH9_SMBState *s = ich9_pci_to_smb(dev);
+
+ assert(size == ICH9_SMB_SMB_BASE_SIZE);
+ assert(type == PCI_BASE_ADDRESS_SPACE_IO);
+
+ register_ioport_write(addr, 64, 1, ich9_smb_ioport_writeb, s);
+ register_ioport_read(addr, 64, 1, ich9_smb_ioport_readb, s);
+}
+
+static int ich9_smb_initfn(PCIDevice *d)
+{
+ ICH9_SMBState *s = ich9_pci_to_smb(d);
+
+ pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
+ pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_ICH9_6);
+
+ pci_set_word(d->wmask + PCI_STATUS,
+ PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
+
+ pci_config_set_revision(d->config, ICH9_A2_SMB_REVISION);
+ pci_config_set_prog_interface(d->config, ICH9_SMB_PI);
+ pci_config_set_class(d->config, PCI_CLASS_SERIAL_SMBUS);
+
+ /* TODO? D31IP.SMIP in chipset configuration space */
+ pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
+
+ pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
+
+ /*
+ * update parameters based on
+ * paralell_hds[0]
+ * serial_hds[0]
+ * serial_hds[0]
+ * fdc
+ *
+ * Is there any OS that depends on them?
+ */
+
+ /* TODO smb_io_base */
+ pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
+ /* TODO bar0, bar1: 64bit BAR support*/
+ pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR,
+ ICH9_SMB_SMB_BASE_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
+ &ich9_smb_map_ioport);
+
+ pm_smbus_init(&d->qdev, &s->smb);
+ return 0;
+}
+
+i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
+{
+ PCIDevice *d =
+ pci_create_simple_multifunction(bus, devfn, true, "ICH9 SMB");
+ ICH9_SMBState *s = ich9_pci_to_smb(d);
+ return s->smb.smbus;
+}
+
+static PCIDeviceInfo ich9_smb_info = {
+ .qdev.name = "ICH9 SMB",
+ .qdev.desc = "ICH9 SMBUS Bridge",
+ .qdev.size = sizeof(ICH9_SMBState),
+ .qdev.vmsd = &vmstate_ich9_smbus,
+ .qdev.no_user = 1,
+ .init = ich9_smb_initfn,
+};
+
+static void ich9_smb_register(void)
+{
+ pci_qdev_register(&ich9_smb_info);
+}
+
+device_init(ich9_smb_register);
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 12/25] q35: Re-base q35 to 1.2
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (10 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-14 19:07 ` Blue Swirl
2012-09-13 20:12 ` [Qemu-devel] [PATCH 14/25] q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic Jason Baron
` (14 subsequent siblings)
26 siblings, 1 reply; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
Rebase q35 to 1.2 - memory api updates, acpi updates, qom...
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/acpi_ich9.c | 65 ++++----
hw/acpi_ich9.h | 9 +-
hw/pc.h | 2 +
hw/pc_piix.c | 4 +-
hw/pc_q35.c | 189 +++++++++++++++-------
hw/q35.c | 477 +++++++++++++++++++++++++++++++-------------------------
hw/q35.h | 97 +++++++++++-
hw/q35_smbus.c | 78 +++++----
8 files changed, 568 insertions(+), 353 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
index 59c0807..0d66109 100644
--- a/hw/acpi_ich9.c
+++ b/hw/acpi_ich9.c
@@ -18,6 +18,7 @@
/*
* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
* VA Linux Systems Japan K.K.
+ * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
*
* This is based on acpi.c.
*/
@@ -47,9 +48,9 @@ static void pm_update_sci(ICH9_LPCPmRegs *pm)
{
int sci_level, pm1a_sts;
- pm1a_sts = acpi_pm1_evt_get_sts(&pm->pm1a, pm->tmr.overflow_time);
+ pm1a_sts = acpi_pm1_evt_get_sts(&pm->acpi_regs);
- sci_level = (((pm1a_sts & pm->pm1a.en) &
+ sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) &
(ACPI_BITMASK_RT_CLOCK_ENABLE |
ACPI_BITMASK_POWER_BUTTON_ENABLE |
ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
@@ -57,14 +58,14 @@ static void pm_update_sci(ICH9_LPCPmRegs *pm)
qemu_set_irq(pm->irq, sci_level);
/* schedule a timer interruption if needed */
- acpi_pm_tmr_update(&pm->tmr,
- (pm->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
+ acpi_pm_tmr_update(&pm->acpi_regs,
+ (pm->acpi_regs.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
!(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
}
-static void ich9_pm_update_sci_fn(ACPIPMTimer *tmr)
+static void ich9_pm_update_sci_fn(ACPIREGS *regs)
{
- ICH9_LPCPmRegs *pm = container_of(tmr, ICH9_LPCPmRegs, tmr);
+ ICH9_LPCPmRegs *pm = container_of(regs, ICH9_LPCPmRegs, acpi_regs);
pm_update_sci(pm);
}
@@ -74,7 +75,7 @@ static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
switch (addr & ICH9_PMIO_MASK) {
case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
- acpi_gpe_ioport_writeb(&pm->gpe0, addr, val);
+ acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
break;
default:
break;
@@ -90,7 +91,7 @@ static uint32_t pm_ioport_readb(void *opaque, uint32_t addr)
switch (addr & ICH9_PMIO_MASK) {
case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
- val = acpi_gpe_ioport_readb(&pm->gpe0, addr);
+ val = acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
break;
default:
val = 0;
@@ -106,15 +107,15 @@ static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
switch (addr & ICH9_PMIO_MASK) {
case ICH9_PMIO_PM1_STS:
- acpi_pm1_evt_write_sts(&pm->pm1a, &pm->tmr, val);
+ acpi_pm1_evt_write_sts(&pm->acpi_regs, val);
pm_update_sci(pm);
break;
case ICH9_PMIO_PM1_EN:
- pm->pm1a.en = val;
+ pm->acpi_regs.pm1.evt.en = val;
pm_update_sci(pm);
break;
case ICH9_PMIO_PM1_CNT:
- acpi_pm1_cnt_write(&pm->pm1a, &pm->pm1_cnt, val);
+ acpi_pm1_cnt_write(&pm->acpi_regs, val, 0);
break;
default:
pm_ioport_write_fallback(opaque, addr, 2, val);
@@ -130,13 +131,13 @@ static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
switch (addr & ICH9_PMIO_MASK) {
case ICH9_PMIO_PM1_STS:
- val = acpi_pm1_evt_get_sts(&pm->pm1a, pm->tmr.overflow_time);
+ val = acpi_pm1_evt_get_sts(&pm->acpi_regs);
break;
case ICH9_PMIO_PM1_EN:
- val = pm->pm1a.en;
+ val = pm->acpi_regs.pm1.evt.en;
break;
case ICH9_PMIO_PM1_CNT:
- val = pm->pm1_cnt.cnt;
+ val = pm->acpi_regs.pm1.cnt.cnt;
break;
default:
val = pm_ioport_read_fallback(opaque, addr, 2);
@@ -168,7 +169,7 @@ static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
switch (addr & ICH9_PMIO_MASK) {
case ICH9_PMIO_PM1_TMR:
- val = acpi_pm_tmr_get(&pm->tmr);
+ val = acpi_pm_tmr_get(&pm->acpi_regs);
break;
case ICH9_PMIO_SMI_EN:
val = pm->smi_en;
@@ -238,7 +239,7 @@ void ich9_pm_iospace_update(ICH9_LPCPmRegs *pm, uint32_t pm_io_base)
register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_readl, pm);
pm->pm_io_base = pm_io_base;
- acpi_gpe_blk(&pm->gpe0, pm_io_base + ICH9_PMIO_GPE0_STS);
+ acpi_gpe_blk(&pm->acpi_regs, pm_io_base + ICH9_PMIO_GPE0_STS);
}
static int ich9_pm_post_load(void *opaque, int version_id)
@@ -268,13 +269,13 @@ const VMStateDescription vmstate_ich9_pm = {
.minimum_version_id_old = 1,
.post_load = ich9_pm_post_load,
.fields = (VMStateField[]) {
- VMSTATE_UINT16(pm1a.sts, ICH9_LPCPmRegs),
- VMSTATE_UINT16(pm1a.en, ICH9_LPCPmRegs),
- VMSTATE_UINT16(pm1_cnt.cnt, ICH9_LPCPmRegs),
- VMSTATE_TIMER(tmr.timer, ICH9_LPCPmRegs),
- VMSTATE_INT64(tmr.overflow_time, ICH9_LPCPmRegs),
- VMSTATE_GPE_ARRAY(gpe0.sts, ICH9_LPCPmRegs),
- VMSTATE_GPE_ARRAY(gpe0.en, ICH9_LPCPmRegs),
+ VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9_LPCPmRegs),
+ VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9_LPCPmRegs),
+ VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9_LPCPmRegs),
+ VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9_LPCPmRegs),
+ VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9_LPCPmRegs),
+ VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9_LPCPmRegs),
+ VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9_LPCPmRegs),
VMSTATE_UINT32(smi_en, ICH9_LPCPmRegs),
VMSTATE_UINT32(smi_sts, ICH9_LPCPmRegs),
VMSTATE_END_OF_LIST()
@@ -286,10 +287,10 @@ static void pm_reset(void *opaque)
ICH9_LPCPmRegs *pm = opaque;
ich9_pm_iospace_update(pm, 0);
- acpi_pm1_evt_reset(&pm->pm1a);
- acpi_pm1_cnt_reset(&pm->pm1_cnt);
- acpi_pm_tmr_reset(&pm->tmr);
- acpi_gpe_reset(&pm->gpe0);
+ acpi_pm1_evt_reset(&pm->acpi_regs);
+ acpi_pm1_cnt_reset(&pm->acpi_regs);
+ acpi_pm_tmr_reset(&pm->acpi_regs);
+ acpi_gpe_reset(&pm->acpi_regs);
pm_update_sci(pm);
}
@@ -297,17 +298,15 @@ static void pm_reset(void *opaque)
static void pm_powerdown(void *opaque, int irq, int power_failing)
{
ICH9_LPCPmRegs *pm = opaque;
- ACPIPM1EVT *pm1a = pm ? &pm->pm1a : NULL;
- ACPIPMTimer *tmr = pm ? &pm->tmr : NULL;
- acpi_pm1_evt_power_down(pm1a, tmr);
+ acpi_pm1_evt_power_down(&pm->acpi_regs);
}
void ich9_pm_init(ICH9_LPCPmRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
{
- acpi_pm_tmr_init(&pm->tmr, ich9_pm_update_sci_fn);
- acpi_pm1_cnt_init(&pm->pm1_cnt, cmos_s3);
- acpi_gpe_init(&pm->gpe0, ICH9_PMIO_GPE0_LEN);
+ acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn);
+ acpi_pm1_cnt_init(&pm->acpi_regs);
+ acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
pm->irq = sci_irq;
qemu_register_reset(pm_reset, pm);
diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h
index f55c0e9..9ff4c42 100644
--- a/hw/acpi_ich9.h
+++ b/hw/acpi_ich9.h
@@ -24,19 +24,12 @@
#include "acpi.h"
typedef struct ICH9_LPCPmRegs {
- ACPIPM1EVT pm1a;
-
/*
* In ich9 spec says that pm1_cnt register is 32bit width and
* that the upper 16bits are reserved and unused.
* PM1a_CNT_BLK = 2 in FADT so it is defined as uint16_t.
*/
- ACPIPM1CNT pm1_cnt;
-
- ACPIPMTimer tmr;
-
- ACPIGPE gpe0;
-
+ ACPIREGS acpi_regs;
uint32_t smi_en;
uint32_t smi_sts;
diff --git a/hw/pc.h b/hw/pc.h
index c78923c..125c1fd 100644
--- a/hw/pc.h
+++ b/hw/pc.h
@@ -69,6 +69,8 @@ int pic_read_irq(DeviceState *d);
int pic_get_output(DeviceState *d);
void pic_info(Monitor *mon);
void irq_info(Monitor *mon);
+void kvm_piix3_gsi_handler(void *opaque, int n, int level);
+void kvm_piix3_setup_irq_routing(bool pci_enabled);
/* Global System Interrupts */
diff --git a/hw/pc_piix.c b/hw/pc_piix.c
index 60c7166..57830ec 100644
--- a/hw/pc_piix.c
+++ b/hw/pc_piix.c
@@ -53,7 +53,7 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
-static void kvm_piix3_setup_irq_routing(bool pci_enabled)
+void kvm_piix3_setup_irq_routing(bool pci_enabled)
{
#ifdef CONFIG_KVM
KVMState *s = kvm_state;
@@ -82,7 +82,7 @@ static void kvm_piix3_setup_irq_routing(bool pci_enabled)
#endif /* CONFIG_KVM */
}
-static void kvm_piix3_gsi_handler(void *opaque, int n, int level)
+void kvm_piix3_gsi_handler(void *opaque, int n, int level)
{
GSIState *s = opaque;
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
index 4f75d97..9d58519 100644
--- a/hw/pc_q35.c
+++ b/hw/pc_q35.c
@@ -27,6 +27,7 @@
* Copyright (c) 2009, 2010
* Isaku Yamahata <yamahata at valinux co jp>
* VA Linux Systems Japan K.K.
+ * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
*
* This is based on pc.c, but heavily modified.
*
@@ -49,7 +50,6 @@
#include "fdc.h"
#include "pci.h"
#include "pci_bridge.h"
-#include "pci_p2pbr.h"
#include "ioh3420.h"
#include "xio3130_upstream.h"
#include "xio3130_downstream.h"
@@ -66,36 +66,16 @@
#include "watchdog.h"
#include "smbios.h"
#include "ide.h"
-#include "usb-uhci.h"
+#include "mc146818rtc.h"
+#include "xen.h"
+#include "kvm.h"
#include "q35.h"
+#include "exec-memory.h"
/* ICH9 AHCI has 6 ports */
#define MAX_SATA_PORTS 6
-#define I21154_REV 0x05
-#define I21154_PI 0x00
-
-static PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
- bool multifunction)
-{
- const PCIP2PBridgeInit init = {
- .bus = bus,
- .devfn = devfn,
- .multifunction = multifunction,
-
- .bus_name = bus_name,
- .map_irq = pci_swizzle_map_irq_fn,
- };
- const PCIP2PBridgeProp prop = {
- .vendor_id = PCI_VENDOR_ID_DEC,
- .device_id = PCI_DEVICE_ID_DEC_21154,
- .revision_id = I21154_REV,
- .prog_interface = I21154_PI,
- };
- return pci_p2pbr_create_simple(&init, &prop);
-}
-
static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
{
uint8_t dev;
@@ -104,7 +84,6 @@ static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
uint8_t chassis = 0;
uint16_t slot = 0;
uint8_t upstream_port;
- PCIESlot *s;
uint8_t fn;
PCIESlot *root_port;
PCIBus *root_port_bus;
@@ -116,11 +95,10 @@ static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
#define Q35_P2P_BRDIGE_DEV_MAX 32
#define Q35_P2P_BRDIGE_SUBBUS_BASE (ICH9_D2P_SECONDARY_DEFAULT + 1)
for (dev = Q35_P2P_BRDIGE_DEV_BASE; dev < Q35_P2P_BRDIGE_DEV_MAX; dev++) {
- PCIBridge *br;
sec_bus = Q35_P2P_BRDIGE_SUBBUS_BASE + dev - Q35_P2P_BRDIGE_DEV_BASE;
snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
- br = i21154_init(pci_bus, PCI_DEVFN(dev, 0), buf, true);
+ i21154_init(pci_bus, PCI_DEVFN(dev, 0), buf, true);
}
/* PCIe root port b0:d1:f0 in GMCH.
@@ -128,8 +106,8 @@ static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
*/
sec_bus = 32;
snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
- s = ioh3420_init(host_bus, PCI_DEVFN(GMCH_PCIE_DEV, GMCH_PCIE_FUNC), true,
- buf, pci_swizzle_map_irq_fn, port, chassis, slot);
+ ioh3420_init(host_bus, PCI_DEVFN(GMCH_PCIE_DEV, GMCH_PCIE_FUNC), true,
+ buf, pci_swizzle_map_irq_fn, port, chassis, slot);
/* more slots. ICH9 doesn't have those, but many slots are wanted. */
@@ -153,8 +131,8 @@ static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
slot++;
snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
- s = ioh3420_init(host_bus, PCI_DEVFN(23, fn), true,
- buf, pci_swizzle_map_irq_fn, port, chassis, slot);
+ ioh3420_init(host_bus, PCI_DEVFN(23, fn), true,
+ buf, pci_swizzle_map_irq_fn, port, chassis, slot);
}
/* PCIe root port b0:d24:f0 */
@@ -219,27 +197,38 @@ static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
slot++;
snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
- s = ioh3420_init(host_bus, PCI_DEVFN(ICH9_PCIE_DEV, fn), true,
- buf, pci_swizzle_map_irq_fn,
- port, chassis, slot);
+ ioh3420_init(host_bus, PCI_DEVFN(ICH9_PCIE_DEV, fn), true,
+ buf, pci_swizzle_map_irq_fn,
+ port, chassis, slot);
}
}
-static void pc_q35_init_early(qemu_irq *isa_irq, IsaIrqState *isa_irq_state,
+static void pc_q35_init_early(qemu_irq *gsi, GSIState *gsi_state,
DeviceState **gmch_host_p,
PCIBus **host_bus_p, PCIBus **pci_bus_p,
- PCIDevice **lpc_p)
+ PCIDevice **lpc_p, ISABus **isa_bus,
+ MemoryRegion *system_memory,
+ MemoryRegion *pci_address_space,
+ MemoryRegion *address_space_io,
+ MemoryRegion *ram_memory,
+ ram_addr_t below_4g_mem_size,
+ ram_addr_t above_4g_mem_size)
{
+ target_phys_addr_t pci_hole64_size;
DeviceState *gmch_host;
PCIBus *host_bus;
PCIBus *pci_bus;
PCIDevice *gmch_state;
PCIDevice *lpc;
+ GMCH_PCIState *gmps;
+ ICH9_LPCState *ich9_lpc;
/* create pci host bus */
- host_bus = gmch_host_init(&gmch_host, isa_irq, isa_irq_state->ioapic);
+ host_bus = gmch_host_init(&gmch_host, gsi, gsi_state->ioapic_irq,
+ pci_address_space, address_space_io);
gmch_state = gmch_init(gmch_host, host_bus);
+ gmps = GMCH_PCI_DEVICE(gmch_state);
/* create conventional pci bus: pcie2pci bridge */
pci_bus = ich9_d2pbr_init(host_bus, PCI_DEVFN(ICH9_D2P_BRIDGE_DEV,
@@ -252,10 +241,53 @@ static void pc_q35_init_early(qemu_irq *isa_irq, IsaIrqState *isa_irq_state,
/* create ISA bus */
lpc = gmch_lpc_init(gmch_host, host_bus);
+ gmps->ram_memory = ram_memory;
+ gmps->pci_address_space = pci_address_space;
+ gmps->system_memory = system_memory;
+ /* pci */
+ memory_region_init_alias(&gmps->pci_hole, "pci-hole",
+ gmps->pci_address_space,
+ below_4g_mem_size,
+ 0x100000000ULL - below_4g_mem_size);
+ memory_region_add_subregion(gmps->system_memory, below_4g_mem_size,
+ &gmps->pci_hole);
+ pci_hole64_size = (sizeof(target_phys_addr_t) == 4 ? 0 :
+ ((uint64_t)1 << 62));
+ memory_region_init_alias(&gmps->pci_hole_64bit, "pci-hole64",
+ gmps->pci_address_space,
+ 0x100000000ULL + above_4g_mem_size,
+ pci_hole64_size);
+ if (pci_hole64_size) {
+ memory_region_add_subregion(gmps->system_memory,
+ 0x100000000ULL + above_4g_mem_size,
+ &gmps->pci_hole_64bit);
+ }
+
+ /* smram */
+ memory_region_init_alias(&gmps->smram_region, "smram-region",
+ pci_address_space, 0xa0000, 0x20000);
+ memory_region_add_subregion_overlap(system_memory, 0xa0000,
+ &gmps->smram_region, 1);
+ memory_region_set_enabled(&gmps->smram_region, false);
+
*gmch_host_p = gmch_host;
*host_bus_p = host_bus;
*pci_bus_p = pci_bus;
*lpc_p = lpc;
+ ich9_lpc = ICH9_LPC_DEVICE(lpc);
+ *isa_bus = ich9_lpc->isa_bus;
+}
+
+
+/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
+ * BIOS will read it and start S3 resume at POST Entry */
+static void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
+{
+ ISADevice *s = opaque;
+
+ if (level) {
+ rtc_set_memory(s, 0xF, 0xFE);
+ }
}
static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,
@@ -309,18 +341,22 @@ static void pc_q35_init(ram_addr_t ram_size,
PCIBus *host_bus;
PCIBus *pci_bus;
PCIDevice *lpc;
- qemu_irq *isa_irq;
- IsaIrqState *isa_irq_state;
BusState *idebus[MAX_SATA_PORTS];
ISADevice *rtc_state;
+ ISADevice *floppy;
MemoryRegion *pci_memory;
MemoryRegion *rom_memory;
MemoryRegion *ram_memory;
+ GSIState *gsi_state;
+ ISABus *isa_bus;
+ int pci_enabled = 1;
+ qemu_irq *cpu_irq;
+ qemu_irq *gsi;
+ qemu_irq *i8259;
+ int i;
pc_cpus_init(cpu_model);
- /* FIXME: add kvm clock ? */
-
if (ram_size >= 0xe0000000) {
above_4g_mem_size = ram_size - 0xe0000000;
below_4g_mem_size = 0xe0000000;
@@ -330,37 +366,70 @@ static void pc_q35_init(ram_addr_t ram_size,
}
/* pci enabled */
- pci_memory = g_new(MemoryRegion, 1);
- memory_region_init(pci_memory, "pci", INT64_MAX);
- rom_memory = pci_memory;
+ if (pci_enabled) {
+ pci_memory = g_new(MemoryRegion, 1);
+ memory_region_init(pci_memory, "pci", INT64_MAX);
+ rom_memory = pci_memory;
+ } else {
+ pci_memory = NULL;
+ rom_memory = get_system_memory();
+ }
/* allocate ram and load rom/bios */
- pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
- initrd_filename, below_4g_mem_size, above_4g_mem_size,
- rom_memory, &ram_memory);
+ if (!xen_enabled()) {
+ pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
+ initrd_filename, below_4g_mem_size, above_4g_mem_size,
+ rom_memory, &ram_memory);
+ }
/* irq lines */
- isa_irq = pc_isa_irq(&isa_irq_state);
- ioapic_init(isa_irq_state);
+ gsi_state = g_malloc0(sizeof(*gsi_state));
+ if (kvm_irqchip_in_kernel()) {
+ kvm_piix3_setup_irq_routing(pci_enabled);
+ gsi = qemu_allocate_irqs(kvm_piix3_gsi_handler, gsi_state,
+ GSI_NUM_PINS);
+ } else {
+ gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
+ }
+
+ pc_q35_init_early(gsi, gsi_state,
+ &gmch_host, &host_bus, &pci_bus, &lpc, &isa_bus,
+ get_system_memory(), pci_memory, get_system_io(),
+ ram_memory, below_4g_mem_size, above_4g_mem_size);
+ isa_bus_irqs(isa_bus, gsi);
+
+ if (kvm_irqchip_in_kernel()) {
+ i8259 = kvm_i8259_init(isa_bus);
+ } else if (xen_enabled()) {
+ i8259 = xen_interrupt_controller_init();
+ } else {
+ cpu_irq = pc_allocate_cpu_irq();
+ i8259 = i8259_init(isa_bus, cpu_irq[0]);
+ }
+
+ for (i = 0; i < ISA_NUM_IRQS; i++) {
+ gsi_state->i8259_irq[i] = i8259[i];
+ }
+ if (pci_enabled) {
+ ioapic_init_gsi(gsi_state, NULL);
+ }
- pc_q35_init_early(isa_irq, isa_irq_state,
- &gmch_host, &host_bus, &pci_bus, &lpc);
- isa_bus_irqs(isa_irq);
- pc_register_ferr_irq(isa_get_irq(13));
+ pc_register_ferr_irq(gsi[13]);
/* init basic PC hardware */
- pc_basic_device_init(isa_irq, &rtc_state, false);
+ pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false);
pc_q35_init_late(idebus, rtc_state, gmch_host, host_bus, pci_bus, lpc);
pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
- idebus[0], idebus[1], rtc_state);
+ floppy, idebus[0], idebus[1], rtc_state);
/* the rest devices to which pci devfn is automatically assigned */
- pc_vga_init(host_bus);
- audio_init(isa_irq, pci_bus);
- pc_nic_init(pci_bus);
- pc_pci_device_init(pci_bus);
+ pc_vga_init(isa_bus, host_bus);
+ audio_init(isa_bus, pci_bus);
+ pc_nic_init(isa_bus, pci_bus);
+ if (pci_enabled)
+ pc_pci_device_init(pci_bus);
}
static QEMUMachine pc_q35_machine = {
diff --git a/hw/q35.c b/hw/q35.c
index 1776ac3..09e8bd7 100644
--- a/hw/q35.c
+++ b/hw/q35.c
@@ -25,6 +25,7 @@
* Copyright (c) 2009, 2010, 2011
* Isaku Yamahata <yamahata at valinux co jp>
* VA Linux Systems Japan K.K.
+ * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
*
* This is based on piix_pci.c, but heavily modified.
*
@@ -52,62 +53,16 @@
#include "pci.h"
#include "pcie_host.h"
#include "pci_bridge.h"
-#include "pci_p2pbr.h"
#include "q35.h"
#include "acpi.h"
#include "acpi_ich9.h"
#include "pam.h"
+#include "pci_internals.h"
+#include "exec-memory.h"
+#include "isa.h"
+#include "qemu-common.h"
-struct ICH9_LPCState;
-
-typedef struct ICH9_LPCIrqState {
- struct ICH9_LPCState *lpc;
- qemu_irq *pic;
- qemu_irq *ioapic;
-} ICH9_LPCIrqState;
-
-typedef struct GMCH_PCIHost {
- PCIExpressHost host;
-
- PCIDevice *dev;
- ICH9_LPCIrqState irq_state;
-} GMCH_PCIHost;
-
-typedef struct GMCH_PCIState {
- PCIDevice d;
- /*
- * GMCH_PCIHost *gmch_host;
- * In order to get GMCH_PCIHost
- * PCIDevice -> qdev -> parent_bus -> qdev -upcast-> GMCH_PCIHost
- */
-
- PAM pam;
-} GMCH_PCIState;
-
-typedef struct ICH9_LPCState {
- /* ICH9 LPC PCI to ISA bridge */
- PCIDevice d;
-
- /* (pci device, intx) -> pirq
- * In real chipset case, the unused slots are never used
- * as ICH9 supports only D25-D32 irq routing.
- * On the other hand in qemu case, any slot/function can be populated
- * via command line option.
- * So fallback interrupt routing for any devices in any slots is necessary.
- */
- uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
-
- APMState apm;
- ICH9_LPCPmRegs pm;
- uint32_t sci_level; /* track sci level */
-
- /* 10.1 Chipset Configuration registers(Memory Space)
- which is pointed by RCBA */
- uint8_t chip_config[ICH9_CC_SIZE];
- int rbca_index;
-} ICH9_LPCState;
-
/****************************************************************************
* GMCH PCI host
@@ -117,20 +72,20 @@ static int ich9_lpc_map_irq(void *opaque, PCIDevice *pci_dev, int intx);
static void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
static int ich9_lpc_sci_irq(ICH9_LPCState *lpc);
-static GMCH_PCIHost *gmch_pcihost_from_qdev(DeviceState *gmch_host_qdev)
-{
- SysBusDevice *sysdev = sysbus_from_qdev(gmch_host_qdev);
- PCIHostState *pci = FROM_SYSBUS(PCIHostState, sysdev);
- PCIExpressHost *pcie = DO_UPCAST(PCIExpressHost, pci, pci);
- return DO_UPCAST(GMCH_PCIHost, host, pcie);
-}
-
static int gmch_pcihost_initfn(SysBusDevice *dev)
{
- GMCH_PCIHost *s = gmch_pcihost_from_qdev(&dev->qdev);
+ PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev);
+ GMCH_PCIHost *s = GMCH_HOST_DEVICE(&dev->qdev);
- pci_host_conf_register_ioport(GMCH_HOST_BRIDGE_CONFIG_ADDR, &s->host.pci);
- pci_host_data_register_ioport(GMCH_HOST_BRIDGE_CONFIG_DATA, &s->host.pci);
+ memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci,
+ "pci-conf-idx", 4);
+ sysbus_add_io(dev, GMCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
+ sysbus_init_ioports(&pci->busdev, GMCH_HOST_BRIDGE_CONFIG_ADDR, 4);
+
+ memory_region_init_io(&pci->data_mem, &pci_host_data_le_ops, pci,
+ "pci-conf-data", 4);
+ sysbus_add_io(dev, GMCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
+ sysbus_init_ioports(&pci->busdev, GMCH_HOST_BRIDGE_CONFIG_DATA, 4);
if (pcie_host_init(&s->host) < 0) {
abort();
@@ -139,36 +94,46 @@ static int gmch_pcihost_initfn(SysBusDevice *dev)
return 0;
}
-static SysBusDeviceInfo gmch_pcihost_info = {
- .init = gmch_pcihost_initfn,
- .qdev.name = "gmch-pcihost",
- .qdev.size = sizeof(GMCH_PCIHost),
- .qdev.no_user = 1,
- .qdev.props = (Property[]) {
- {
- .name = "MCFG",
- .info = &qdev_prop_uint64,
- .offset = offsetof(GMCH_PCIHost, host.base_addr),
- .defval = (uint64_t[]){ GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT },
- },
- DEFINE_PROP_END_OF_LIST(),
- },
+static Property gmch_props[] = {
+ DEFINE_PROP_UINT64("MCFG", GMCH_PCIHost, host.base_addr,
+ GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void gmch_pcihost_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = gmch_pcihost_initfn;
+ dc->props = gmch_props;
+ dc->no_user = 1;
+}
+
+static TypeInfo gmch_pcihost_info = {
+ .name = TYPE_GMCH_HOST_DEVICE,
+ .parent = TYPE_PCIE_HOST_BRIDGE,
+ .instance_size = sizeof(GMCH_PCIHost),
+ .class_init = gmch_pcihost_class_init,
};
/* host bridge */
PCIBus *gmch_host_init(DeviceState **gmch_hostp,
- qemu_irq *pic, qemu_irq *ioapic)
+ qemu_irq *pic, qemu_irq *ioapic,
+ MemoryRegion *pci_address_space,
+ MemoryRegion *address_space_io)
{
DeviceState *dev;
GMCH_PCIHost *s;
PCIBus *b;
- dev = qdev_create(NULL, "gmch-pcihost");
- s = gmch_pcihost_from_qdev(dev);
+ dev = qdev_create(NULL, TYPE_GMCH_HOST_DEVICE);
+ s = GMCH_HOST_DEVICE(dev);
s->irq_state.pic = pic;
s->irq_state.ioapic = ioapic;
- b = pci_bus_new(dev, "pcie.0", 0);
+ b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0", pci_address_space,
+ address_space_io, 0);
pci_bus_irqs(b, ich9_lpc_set_irq, ich9_lpc_map_irq, &s->irq_state,
ICH9_LPC_NB_PIRQS);
s->host.pci.bus = b;
@@ -180,12 +145,8 @@ PCIBus *gmch_host_init(DeviceState **gmch_hostp,
/****************************************************************************
- * GMCH
+ * GMCH D0:F0
*/
-static GMCH_PCIState *gmch_from_pci(PCIDevice *gmch_pci)
-{
- return DO_UPCAST(GMCH_PCIState, d, gmch_pci);
-}
/* PCIE MMCFG */
static void gmch_update_pciexbar(GMCH_PCIState *gs)
@@ -193,7 +154,7 @@ static void gmch_update_pciexbar(GMCH_PCIState *gs)
PCIDevice *pci_dev = &gs->d;
BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
DeviceState *qdev = bus->parent;
- GMCH_PCIHost *s = gmch_pcihost_from_qdev(qdev);
+ GMCH_PCIHost *s = GMCH_HOST_DEVICE(qdev);
uint64_t pciexbar;
int enable;
@@ -234,27 +195,39 @@ static void gmch_update_pciexbar(GMCH_PCIState *gs)
static void gmch_update_pam(GMCH_PCIState *gs)
{
int i;
+
+ memory_region_transaction_begin();
for (i = 0; i <= PAM_IDX_MAX; i++) {
- pam_update(&gs->pam, i, gs->d.config[GMCH_HOST_BRIDGE_PAM0 + i]);
+ pam_update(&gs->pam_regions[0], i,
+ gs->d.config[GMCH_HOST_BRIDGE_PAM0 + i],
+ gs->ram_memory, gs->pci_address_space, gs->system_memory);
}
+ memory_region_transaction_commit();
}
/* SMRAM */
static void gmch_update_smram(GMCH_PCIState *gs)
{
- smram_update(&gs->pam, gs->d.config[GMCH_HOST_BRDIGE_SMRAM]);
+ memory_region_transaction_begin();
+ smram_update(&gs->smram_region, gs->d.config[GMCH_HOST_BRDIGE_SMRAM],
+ gs->smm_enabled);
+ memory_region_transaction_commit();
}
static void gmch_set_smm(int smm, void *arg)
{
GMCH_PCIState *gs = arg;
- smram_set_smm(&gs->pam, smm, gs->d.config[GMCH_HOST_BRDIGE_SMRAM]);
+
+ memory_region_transaction_begin();
+ smram_set_smm(&gs->smm_enabled, smm, gs->d.config[GMCH_HOST_BRDIGE_SMRAM],
+ &gs->smram_region);
+ memory_region_transaction_commit();
}
static void gmch_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len)
{
- GMCH_PCIState *gs = gmch_from_pci(d);
+ GMCH_PCIState *gs = GMCH_PCI_DEVICE(d);
/* XXX: implement SMRAM.D_LOCK */
pci_default_write_config(d, address, val, len);
@@ -297,15 +270,15 @@ static const VMStateDescription vmstate_gmch = {
.post_load = gmch_post_load,
.fields = (VMStateField []) {
VMSTATE_PCI_DEVICE(d, GMCH_PCIState),
- VMSTATE_UINT8(pam.smm_enabled, GMCH_PCIState),
+ VMSTATE_UINT8(smm_enabled, GMCH_PCIState),
VMSTATE_END_OF_LIST()
}
};
static void gmch_reset(DeviceState *qdev)
{
- PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
- GMCH_PCIState *gs = gmch_from_pci(d);
+ PCIDevice *d = PCI_DEVICE(qdev);
+ GMCH_PCIState *gs = GMCH_PCI_DEVICE(d);
pci_set_quad(d->config + GMCH_HOST_BRIDGE_PCIEXBAR,
GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
@@ -315,39 +288,46 @@ static void gmch_reset(DeviceState *qdev)
gmch_update(gs);
}
-static int gmch_initfn(PCIDevice *d)
+static int pci_gmch_initfn(PCIDevice *d)
{
- GMCH_PCIState *gs = gmch_from_pci(d);
-
- pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
- pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_Q35_MCH);
- pci_config_set_revision(d->config, GMCH_HOST_BRIDGE_REVISION_DEFUALT);
- pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
+ GMCH_PCIState *gs = GMCH_PCI_DEVICE(d);
cpu_smm_register(&gmch_set_smm, gs);
- pam_init_memory_mappings(&gs->pam);
return 0;
}
-static PCIDeviceInfo gmch_info = {
- .qdev.name = "gmch",
- .qdev.desc = "Host bridge",
- .qdev.size = sizeof(GMCH_PCIState),
- .qdev.vmsd = &vmstate_gmch,
- .qdev.no_user = 1,
- .init = gmch_initfn,
- .config_write = gmch_write_config,
- .qdev.reset = gmch_reset,
+static void pci_gmch_class_init(ObjectClass *klass, void *data)
+{
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ k->init = pci_gmch_initfn;
+ k->config_write = gmch_write_config;
+ dc->reset = gmch_reset;
+ dc->desc = "Host bridge";
+ dc->vmsd = &vmstate_gmch;
+ dc->no_user = 1;
+ k->vendor_id = PCI_VENDOR_ID_INTEL;
+ k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
+ k->revision = GMCH_HOST_BRIDGE_REVISION_DEFUALT;
+ k->class_id = PCI_CLASS_BRIDGE_HOST;
+}
+
+struct TypeInfo pci_gmch_info = {
+ .name = TYPE_GMCH_PCI_DEVICE,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(GMCH_PCIState),
+ .class_init = pci_gmch_class_init,
};
/* host bridge */
PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b)
{
- GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
+ GMCH_PCIHost *s = GMCH_HOST_DEVICE(gmch_host);
PCIDevice *d;
- d = pci_create_simple_multifunction(b, 0, false, "gmch");
+ d = pci_create_simple_multifunction(b, 0, false, TYPE_GMCH_PCI_DEVICE);
s->dev = d;
return d;
@@ -359,54 +339,135 @@ PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b)
#define I82801ba_SSVID_SVID 0
#define I82801ba_SSVID_SSID 0
-static PCIBridge *i82801ba11_init(PCIBus *bus, int devfn, const char *bus_name,
- bool multifunction)
+struct i82801b11_bridge {
+ PCIBridge br;
+};
+
+static int i82801b11_bridge_initfn(PCIDevice *d)
{
- const PCIP2PBridgeInit init = {
- .bus = bus,
- .devfn = devfn,
- .multifunction = multifunction,
+ int rc;
+
+ rc = pci_bridge_initfn(d);
+ if (rc < 0) {
+ return rc;
+ }
+
+ rc = pci_bridge_ssvid_init(d, I82801ba_SSVID_OFFSET,
+ I82801ba_SSVID_SVID, I82801ba_SSVID_SSID);
+ if (rc < 0) {
+ goto err_bridge;
+ }
+ return 0;
- .bus_name = bus_name,
- .map_irq = pci_swizzle_map_irq_fn,
- };
- const PCIP2PBridgeProp prop = {
- .vendor_id = PCI_VENDOR_ID_INTEL,
- .device_id = PCI_DEVICE_ID_INTEL_82801BA_11,
- .revision_id = ICH9_D2P_A2_REVISION,
- .prog_interface = PCI_CLASS_BRDIGE_PCI_INF_SUB,
+err_bridge:
+ pci_bridge_exitfn(d);
- .ssvid_cap = I82801ba_SSVID_OFFSET,
- .svid = I82801ba_SSVID_SVID,
- .ssid = I82801ba_SSVID_SSID,
- };
- return pci_p2pbr_create_simple(&init, &prop);
+ return rc;
}
+static void i82801b11_bridge_class_init(ObjectClass *klass, void *data)
+{
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->is_bridge = 1;
+ k->vendor_id = PCI_VENDOR_ID_INTEL;
+ k->device_id = PCI_DEVICE_ID_INTEL_82801BA_11;
+ k->revision = ICH9_D2P_A2_REVISION;
+ k->init = i82801b11_bridge_initfn;
+}
+
+static TypeInfo i82801b11_bridge_info = {
+ .name = "i82801b11-bridge",
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(struct i82801b11_bridge),
+ .class_init = i82801b11_bridge_class_init,
+};
+
PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus)
{
+ PCIDevice *d;
PCIBridge *br;
char buf[16];
+ DeviceState *qdev;
- snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
- br = i82801ba11_init(bus, devfn, buf, true);
- if (br == NULL) {
+ d = pci_create_multifunction(bus, devfn, true, "i82801b11-bridge");
+ if (!d) {
return NULL;
}
+ br = DO_UPCAST(PCIBridge, dev, d);
+ qdev = &br->dev.qdev;
+
+ snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
+ pci_bridge_map_irq(br, buf, pci_swizzle_map_irq_fn);
+ qdev_init_nofail(qdev);
+
return pci_bridge_get_sec_bus(br);
}
+/*****************************************************************************/
+/* i21154 pci bridge*/
+struct i21154_bridge {
+ PCIBridge br;
+};
-/*****************************************************************************/
-/* ICH9 LPC PCI to ISA bridge */
+static int i21154_bridge_initfn(PCIDevice *d)
+{
+ int rc;
-static void ich9_lpc_reset(DeviceState *qdev);
+ rc = pci_bridge_initfn(d);
+ if (rc < 0) {
+ return rc;
+ }
+
+ return 0;
+}
+
+#define I21154_REV 0x05
+#define I21154_PI 0x00
+
+static void i21154_bridge_class_init(ObjectClass *klass, void *data)
+{
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->is_bridge = 1;
+ k->vendor_id = PCI_VENDOR_ID_DEC;
+ k->device_id = PCI_DEVICE_ID_DEC_21154;
+ k->revision = I21154_REV;
+ k->init = i21154_bridge_initfn;
+}
+
+static TypeInfo i21154_bridge_info = {
+ .name = "i21154-bridge",
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(struct i21154_bridge),
+ .class_init = i21154_bridge_class_init,
+};
-static ICH9_LPCState *ich9_lpc_from_pci(PCIDevice *lpc_pci)
+PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
+ bool multifunction)
{
- return DO_UPCAST(ICH9_LPCState, d, lpc_pci);
+ PCIDevice *d;
+ PCIBridge *br;
+ DeviceState *qdev;
+
+ d = pci_create_multifunction(bus, devfn, multifunction, "i21154-bridge");
+ if (!d) {
+ return NULL;
+ }
+ br = DO_UPCAST(PCIBridge, dev, d);
+ qdev = &br->dev.qdev;
+
+ pci_bridge_map_irq(br, bus_name, pci_swizzle_map_irq_fn);
+ qdev_init_nofail(qdev);
+
+ return br;
}
+/*****************************************************************************/
+/* ICH9 LPC PCI to ISA bridge */
+
+static void ich9_lpc_reset(DeviceState *qdev);
+
/* chipset configuration register
* to access chipset configuration registers, pci_[sg]et_{byte, word, long}
* are used.
@@ -485,7 +546,7 @@ static void ich9_cc_reset(ICH9_LPCState *lpc)
ich9_cc_update(lpc);
}
-static void ich9_cc_addr_len(uint32_t *addr, int *len)
+static void ich9_cc_addr_len(uint64_t *addr, unsigned *len)
{
*addr &= ICH9_CC_ADDR_MASK;
if (*addr + *len >= ICH9_CC_SIZE) {
@@ -494,56 +555,27 @@ static void ich9_cc_addr_len(uint32_t *addr, int *len)
}
/* val: little endian */
-static void ich9_cc_write(ICH9_LPCState *lpc, uint32_t addr,
- uint32_t val, int len)
+static void ich9_cc_write(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned len)
{
+ ICH9_LPCState *lpc = (ICH9_LPCState *)opaque;
+
ich9_cc_addr_len(&addr, &len);
memcpy(lpc->chip_config + addr, &val, len);
}
/* return value: little endian */
-static uint32_t ich9_cc_read(ICH9_LPCState *lpc, uint32_t addr, int len)
+static uint64_t ich9_cc_read(void *opaque, target_phys_addr_t addr,
+ unsigned len)
{
+ ICH9_LPCState *lpc = (ICH9_LPCState *)opaque;
+
uint32_t val = 0;
ich9_cc_addr_len(&addr, &len);
memcpy(&val, lpc->chip_config + addr, len);
return val;
}
-#define ICH9_CC_MMIO_WRITE(type, len) \
- static void ich9_cc_mmio_write ## type \
- (void *opaque, target_phys_addr_t addr, uint32_t val) \
- { \
- ich9_cc_write(opaque, addr, val, len); \
- }
-
-#define ICH9_CC_MMIO_READ(type, len) \
- static uint32_t ich9_cc_mmio_read ## type \
- (void *opaque, target_phys_addr_t addr) \
- { \
- return ich9_cc_read(opaque, addr, len); \
- }
-
-ICH9_CC_MMIO_WRITE(b, 1)
-ICH9_CC_MMIO_WRITE(w, 2)
-ICH9_CC_MMIO_WRITE(l, 4)
-
-ICH9_CC_MMIO_READ(b, 1)
-ICH9_CC_MMIO_READ(w, 2)
-ICH9_CC_MMIO_READ(l, 4)
-
-static CPUWriteMemoryFunc * const ich9_cc_mmio_write[] = {
- ich9_cc_mmio_writeb,
- ich9_cc_mmio_writew,
- ich9_cc_mmio_writel,
-};
-
-static CPUReadMemoryFunc * const ich9_cc_mmio_read[] = {
- ich9_cc_mmio_readb,
- ich9_cc_mmio_readw,
- ich9_cc_mmio_readl,
-};
-
/* IRQ routing */
/* */
static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis)
@@ -702,8 +734,8 @@ static void ich9_set_sci(void *opaque, int irq_num, int level)
void ich9_lpc_pm_init(DeviceState *gmch_host, PCIDevice *lpc_pci,
qemu_irq cmos_s3)
{
- GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
- ICH9_LPCState *lpc = ich9_lpc_from_pci(lpc_pci);
+ GMCH_PCIHost *s = GMCH_HOST_DEVICE(gmch_host);
+ ICH9_LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
qemu_irq *sci_irq;
sci_irq = qemu_allocate_irqs(ich9_set_sci, &s->irq_state, 1);
@@ -713,12 +745,14 @@ void ich9_lpc_pm_init(DeviceState *gmch_host, PCIDevice *lpc_pci,
}
/* APM */
+
+
static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
{
ICH9_LPCState *lpc = arg;
/* ACPI specs 3.0, 4.7.2.5 */
- acpi_pm1_cnt_update(&lpc->pm.pm1_cnt,
+ acpi_pm1_cnt_update(&lpc->pm.acpi_regs,
val == ICH9_APM_ACPI_ENABLE,
val == ICH9_APM_ACPI_DISABLE);
@@ -744,12 +778,12 @@ static void ich9_lpc_rcba_update(ICH9_LPCState *lpc, uint32_t rbca_old)
uint32_t rbca = pci_get_long(lpc->d.config + ICH9_LPC_RCBA);
if (rbca_old & ICH9_LPC_RCBA_EN) {
- cpu_register_physical_memory(rbca_old & ICH9_LPC_RCBA_BA_MASK,
- ICH9_CC_SIZE, IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &lpc->rbca_mem);
}
if (rbca & ICH9_LPC_RCBA_EN) {
- cpu_register_physical_memory(rbca & ICH9_LPC_RCBA_BA_MASK,
- ICH9_CC_SIZE, lpc->rbca_index);
+ memory_region_add_subregion_overlap(get_system_memory(),
+ rbca & ICH9_LPC_RCBA_BA_MASK,
+ &lpc->rbca_mem, 1);
}
}
@@ -765,7 +799,7 @@ static int ich9_lpc_post_load(void *opaque, int version_id)
static void ich9_lpc_config_write(PCIDevice *d,
uint32_t addr, uint32_t val, int len)
{
- ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
+ ICH9_LPCState *lpc = ICH9_LPC_DEVICE(d);
uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA);
pci_default_write_config(d, addr, val, len);
@@ -779,8 +813,8 @@ static void ich9_lpc_config_write(PCIDevice *d,
static void ich9_lpc_reset(DeviceState *qdev)
{
- PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
- ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
+ PCIDevice *d = PCI_DEVICE(qdev);
+ ICH9_LPCState *lpc = ICH9_LPC_DEVICE(d);
uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA);
int i;
@@ -805,22 +839,26 @@ static void ich9_lpc_reset(DeviceState *qdev)
lpc->sci_level = 0;
}
+static const MemoryRegionOps rbca_mmio_ops = {
+ .read = ich9_cc_read,
+ .write = ich9_cc_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
static int ich9_lpc_initfn(PCIDevice *d)
{
- ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
+ ICH9_LPCState *lpc = ICH9_LPC_DEVICE(d);
+ ISABus *isa_bus;
- isa_bus_new(&d->qdev);
- pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
- pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_ICH9_8); /* ICH9 LPC */
- pci_config_set_revision(d->config, ICH9_A2_LPC_REVISION);
- pci_config_set_class(d->config, PCI_CLASS_BRIDGE_ISA);
+ isa_bus = isa_bus_new(&d->qdev, get_system_io());
pci_set_long(d->wmask + ICH9_LPC_PMBASE,
ICH9_LPC_PMBASE_BASE_ADDRESS_MASK);
- lpc->rbca_index = cpu_register_io_memory(ich9_cc_mmio_read,
- ich9_cc_mmio_write,
- lpc, DEVICE_LITTLE_ENDIAN);
+ memory_region_init_io(&lpc->rbca_mem, &rbca_mmio_ops, lpc,
+ "lpc-rbca-mmio", ICH9_CC_SIZE);
+
+ lpc->isa_bus = isa_bus;
ich9_cc_init(lpc);
apm_init(&lpc->apm, ich9_apm_ctrl_changed, lpc);
@@ -845,33 +883,50 @@ static const VMStateDescription vmstate_ich9_lpc = {
PCIDevice *gmch_lpc_init(DeviceState *gmch_host, PCIBus *bus)
{
- GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
+ GMCH_PCIHost *s = GMCH_HOST_DEVICE(gmch_host);
PCIDevice *d;
ICH9_LPCState *lpc;
d = pci_create_simple_multifunction(bus, PCI_DEVFN(ICH9_LPC_DEV,
ICH9_LPC_FUNC),
- true, "ICH9 LPC");
- lpc = ich9_lpc_from_pci(d);
+ true, TYPE_ICH9_LPC_DEVICE);
+ lpc = ICH9_LPC_DEVICE(d);
s->irq_state.lpc = lpc;
return &lpc->d;
}
-static PCIDeviceInfo ich9_lpc_info = {
- .qdev.name = "ICH9 LPC",
- .qdev.desc = "ICH9 LPC bridge",
- .qdev.size = sizeof(ICH9_LPCState),
- .qdev.vmsd = &vmstate_ich9_lpc,
- .qdev.no_user = 1,
- .init = ich9_lpc_initfn,
- .config_write = ich9_lpc_config_write,
- .qdev.reset = ich9_lpc_reset,
+static void ich9_lpc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ dc->reset = ich9_lpc_reset;
+ k->init = ich9_lpc_initfn;
+ dc->vmsd = &vmstate_ich9_lpc;
+ dc->no_user = 1;
+ k->config_write = ich9_lpc_config_write;
+ dc->desc = "ICH9 LPC bridge";
+ k->vendor_id = PCI_VENDOR_ID_INTEL;
+ k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8;
+ k->revision = ICH9_A2_LPC_REVISION;
+ k->class_id = PCI_CLASS_BRIDGE_ISA;
+
+}
+
+static TypeInfo ich9_lpc_info = {
+ .name = TYPE_ICH9_LPC_DEVICE,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(struct ICH9_LPCState),
+ .class_init = ich9_lpc_class_init,
};
static void q35_register(void)
{
- sysbus_register_withprop(&gmch_pcihost_info);
- pci_qdev_register(&gmch_info);
- pci_qdev_register(&ich9_lpc_info);
+ type_register_static(&pci_gmch_info);
+ type_register_static(&gmch_pcihost_info);
+ type_register_static(&i82801b11_bridge_info);
+ type_register_static(&i21154_bridge_info);
+ type_register_static(&ich9_lpc_info);
}
-device_init(q35_register);
+
+type_init(q35_register);
diff --git a/hw/q35.h b/hw/q35.h
index be2e96b..030386e 100644
--- a/hw/q35.h
+++ b/hw/q35.h
@@ -21,19 +21,109 @@
#ifndef HW_Q35_H
#define HW_Q35_H
+#include "hw.h"
+#include "range.h"
+#include "isa.h"
#include "sysbus.h"
+#include "pc.h"
+#include "apm.h"
+#include "apic.h"
+#include "pci.h"
+#include "pcie_host.h"
+#include "pci_bridge.h"
+#include "q35.h"
+#include "acpi.h"
#include "acpi_ich9.h"
+#include "pam.h"
+#include "pci_internals.h"
+
+
+#define ICH9_CC_SIZE (16 * 1024) /* 16KB */
+
+#define TYPE_GMCH_HOST_DEVICE "gmch-pcihost"
+#define GMCH_HOST_DEVICE(obj) \
+ OBJECT_CHECK(GMCH_PCIHost, (obj), TYPE_GMCH_HOST_DEVICE)
+
+#define TYPE_GMCH_PCI_DEVICE "gmch"
+#define GMCH_PCI_DEVICE(obj) \
+ OBJECT_CHECK(GMCH_PCIState, (obj), TYPE_GMCH_PCI_DEVICE)
+
+#define TYPE_ICH9_LPC_DEVICE "ICH9 LPC"
+#define ICH9_LPC_DEVICE(obj) \
+ OBJECT_CHECK(ICH9_LPCState, (obj), TYPE_ICH9_LPC_DEVICE)
+
+struct ICH9_LPCState;
+
+typedef struct ICH9_LPCIrqState {
+ struct ICH9_LPCState *lpc;
+ qemu_irq *pic;
+ qemu_irq *ioapic;
+} ICH9_LPCIrqState;
+
+typedef struct GMCH_PCIHost {
+ PCIExpressHost host;
+
+ PCIDevice *dev;
+ ICH9_LPCIrqState irq_state;
+} GMCH_PCIHost;
+
+typedef struct GMCH_PCIState {
+ PCIDevice d;
+ /*
+ * GMCH_PCIHost *gmch_host;
+ * In order to get GMCH_PCIHost
+ * PCIDevice -> qdev -> parent_bus -> qdev -upcast-> GMCH_PCIHost
+ */
+ MemoryRegion *ram_memory;
+ MemoryRegion *pci_address_space;
+ MemoryRegion *system_memory;
+ PAMMemoryRegion pam_regions[13];
+ MemoryRegion smram_region;
+ MemoryRegion pci_hole;
+ MemoryRegion pci_hole_64bit;
+ uint8_t smm_enabled;
+} GMCH_PCIState;
+
+typedef struct ICH9_LPCState {
+ /* ICH9 LPC PCI to ISA bridge */
+ PCIDevice d;
+
+ /* (pci device, intx) -> pirq
+ * In real chipset case, the unused slots are never used
+ * as ICH9 supports only D25-D32 irq routing.
+ * On the other hand in qemu case, any slot/function can be populated
+ * via command line option.
+ * So fallback interrupt routing for any devices in any slots is necessary.
+ */
+ uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
+
+ APMState apm;
+ ICH9_LPCPmRegs pm;
+ uint32_t sci_level; /* track sci level */
+
+ /* 10.1 Chipset Configuration registers(Memory Space)
+ which is pointed by RCBA */
+ uint8_t chip_config[ICH9_CC_SIZE];
+ /* isa bus */
+ ISABus *isa_bus;
+ MemoryRegion rbca_mem;
+} ICH9_LPCState;
-PCIBus *gmch_host_init(DeviceState **gmch_hostp,
- qemu_irq *pic, qemu_irq *ioapic);
+
+
+PCIBus *gmch_host_init(DeviceState **gmch_hostp,
+ qemu_irq *pic, qemu_irq *ioapic,
+ MemoryRegion *pci_address_space,
+ MemoryRegion *address_space_io);
PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b);
PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus);
PCIDevice *gmch_lpc_init(DeviceState *gmch_host, PCIBus *bus);
void ich9_lpc_pm_init(DeviceState *gmch_host, PCIDevice *pci_lpc,
qemu_irq cmos_s3);
-
i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
+PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
+ bool multifunction);
#define Q35_MASK(bit, ms_bit, ls_bit) \
((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
@@ -124,7 +214,6 @@ i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
*/
/* ICH9: Chipset Configuration Registers */
-#define ICH9_CC_SIZE (16 * 1024) /* 16KB */
#define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
#define ICH9_CC
diff --git a/hw/q35_smbus.c b/hw/q35_smbus.c
index fe445ac..0ee404e 100644
--- a/hw/q35_smbus.c
+++ b/hw/q35_smbus.c
@@ -18,6 +18,7 @@
/*
* Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
* VA Linux Systems Japan K.K.
+ * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
*
* This is based on acpi.c, but heavily rewritten.
*/
@@ -35,6 +36,7 @@ typedef struct ICH9_SMBState {
PCIDevice dev;
PMSMBus smb;
+ MemoryRegion mem_bar;
} ICH9_SMBState;
static ICH9_SMBState *ich9_pci_to_smb(PCIDevice* pci_dev)
@@ -53,7 +55,8 @@ static const VMStateDescription vmstate_ich9_smbus = {
}
};
-static void ich9_smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
+static void ich9_smb_ioport_writeb(void *opaque, target_phys_addr_t addr,
+ uint64_t val, unsigned size)
{
ICH9_SMBState *s = opaque;
uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
@@ -64,7 +67,8 @@ static void ich9_smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
}
}
-static uint32_t ich9_smb_ioport_readb(void *opaque, uint32_t addr)
+static uint64_t ich9_smb_ioport_readb(void *opaque, target_phys_addr_t addr,
+ unsigned size)
{
ICH9_SMBState *s = opaque;
uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
@@ -77,32 +81,22 @@ static uint32_t ich9_smb_ioport_readb(void *opaque, uint32_t addr)
return 0xff;
}
-static void ich9_smb_map_ioport(PCIDevice *dev, int region_num,
- uint64_t addr, uint64_t size, int type)
-{
- ICH9_SMBState *s = ich9_pci_to_smb(dev);
-
- assert(size == ICH9_SMB_SMB_BASE_SIZE);
- assert(type == PCI_BASE_ADDRESS_SPACE_IO);
-
- register_ioport_write(addr, 64, 1, ich9_smb_ioport_writeb, s);
- register_ioport_read(addr, 64, 1, ich9_smb_ioport_readb, s);
-}
+static const MemoryRegionOps lpc_smb_mmio_ops = {
+ .read = ich9_smb_ioport_readb,
+ .write = ich9_smb_ioport_writeb,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
-static int ich9_smb_initfn(PCIDevice *d)
+static int ich9_smbus_initfn(PCIDevice *d)
{
ICH9_SMBState *s = ich9_pci_to_smb(d);
- pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
- pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_ICH9_6);
-
pci_set_word(d->wmask + PCI_STATUS,
- PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
-
- pci_config_set_revision(d->config, ICH9_A2_SMB_REVISION);
- pci_config_set_prog_interface(d->config, ICH9_SMB_PI);
- pci_config_set_class(d->config, PCI_CLASS_SERIAL_SMBUS);
-
+ PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
/* TODO? D31IP.SMIP in chipset configuration space */
pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
@@ -121,14 +115,30 @@ static int ich9_smb_initfn(PCIDevice *d)
/* TODO smb_io_base */
pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
/* TODO bar0, bar1: 64bit BAR support*/
- pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR,
- ICH9_SMB_SMB_BASE_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
- &ich9_smb_map_ioport);
+ memory_region_init_io(&s->mem_bar, &lpc_smb_mmio_ops, s, "ich9-smbus-bar",
+ ICH9_SMB_SMB_BASE_SIZE);
+ pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
+ &s->mem_bar);
pm_smbus_init(&d->qdev, &s->smb);
return 0;
}
+static void ich9_smb_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->vendor_id = PCI_VENDOR_ID_INTEL;
+ k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6;
+ k->revision = ICH9_A2_SMB_REVISION;
+ k->class_id = PCI_CLASS_SERIAL_SMBUS;
+ dc->no_user = 1;
+ dc->vmsd = &vmstate_ich9_smbus;
+ dc->desc = "ICH9 SMBUS Bridge";
+ k->init = ich9_smbus_initfn;
+}
+
i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
{
PCIDevice *d =
@@ -137,18 +147,16 @@ i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
return s->smb.smbus;
}
-static PCIDeviceInfo ich9_smb_info = {
- .qdev.name = "ICH9 SMB",
- .qdev.desc = "ICH9 SMBUS Bridge",
- .qdev.size = sizeof(ICH9_SMBState),
- .qdev.vmsd = &vmstate_ich9_smbus,
- .qdev.no_user = 1,
- .init = ich9_smb_initfn,
+static TypeInfo ich9_smb_info = {
+ .name = "ICH9 SMB",
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(ICH9_SMBState),
+ .class_init = ich9_smb_class_init,
};
static void ich9_smb_register(void)
{
- pci_qdev_register(&ich9_smb_info);
+ type_register_static(&ich9_smb_info);
}
-device_init(ich9_smb_register);
+type_init(ich9_smb_register);
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 14/25] q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (11 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 12/25] q35: Re-base q35 to 1.2 Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 13/25] q35: Suppress SMM BIOS initialization under KVM Jason Baron
` (13 subsequent siblings)
26 siblings, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
From: Jan Kiszka <jan.kiszka@siemens.com>
Avoid passing a non-PCI IRQ to ich9_gsi_to_pirq. It's wrong and triggers
an assertion.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/q35.c | 6 ++++--
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/q35.c b/hw/q35.c
index 09e8bd7..8b6a2e5 100644
--- a/hw/q35.c
+++ b/hw/q35.c
@@ -657,9 +657,11 @@ static void ich9_lpc_update_apic(ICH9_LPCIrqState *irq_state, int gsi)
{
GMCH_PCIHost *s = container_of(irq_state, GMCH_PCIHost, irq_state);
ICH9_LPCState *lpc = irq_state->lpc;
- int level;
+ int level = 0;
- level = pci_bus_get_irq_level(s->host.pci.bus, ich9_gsi_to_pirq(gsi));
+ if (gsi >= ICH9_LPC_PIC_NUM_PINS) {
+ level |= pci_bus_get_irq_level(s->host.pci.bus, ich9_gsi_to_pirq(gsi));
+ }
if (gsi == ich9_lpc_sci_irq(lpc)) {
level |= lpc->sci_level;
}
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 13/25] q35: Suppress SMM BIOS initialization under KVM
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (12 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 14/25] q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 15/25] q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and PCI_STATUS_DETECTED_PARITY from w1cmask Jason Baron
` (12 subsequent siblings)
26 siblings, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
From: Jan Kiszka <jan.kiszka@siemens.com>
Same as for i44fx: KVM does not support SMM yet. Signal it initialized
to Seabios to avoid failures.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/acpi_ich9.c | 7 +++++++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
index 0d66109..570ce0c 100644
--- a/hw/acpi_ich9.c
+++ b/hw/acpi_ich9.c
@@ -28,6 +28,7 @@
#include "qemu-timer.h"
#include "sysemu.h"
#include "acpi.h"
+#include "kvm.h"
#include "q35.h"
@@ -292,6 +293,12 @@ static void pm_reset(void *opaque)
acpi_pm_tmr_reset(&pm->acpi_regs);
acpi_gpe_reset(&pm->acpi_regs);
+ if (kvm_enabled()) {
+ /* Mark SMM as already inited to prevent SMM from running. KVM does not
+ * support SMM mode. */
+ pm->smi_en |= ICH9_PMIO_SMI_EN_APMC_EN;
+ }
+
pm_update_sci(pm);
}
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 15/25] q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and PCI_STATUS_DETECTED_PARITY from w1cmask
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (13 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 13/25] q35: Suppress SMM BIOS initialization under KVM Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 16/25] pci: Add class 0xc05 as 'SMBus' Jason Baron
` (11 subsequent siblings)
26 siblings, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
From: Jan Kiszka <jan.kiszka@siemens.com>
Both bits are added to the write-1-to-clear mask by default. As the
smbus device does not allow writes at all, we have to remove it from
that mask, also to avoid triggering a runtime assertion.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/q35_smbus.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/hw/q35_smbus.c b/hw/q35_smbus.c
index 0ee404e..42dfcb1 100644
--- a/hw/q35_smbus.c
+++ b/hw/q35_smbus.c
@@ -97,6 +97,10 @@ static int ich9_smbus_initfn(PCIDevice *d)
pci_set_word(d->wmask + PCI_STATUS,
PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
+ pci_set_word(d->w1cmask + PCI_STATUS,
+ pci_get_word(d->w1cmask + PCI_STATUS) &
+ ~(PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY));
+
/* TODO? D31IP.SMIP in chipset configuration space */
pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 16/25] pci: Add class 0xc05 as 'SMBus'
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (14 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 15/25] q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and PCI_STATUS_DETECTED_PARITY from w1cmask Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-14 7:04 ` Paolo Bonzini
2012-09-13 20:12 ` [Qemu-devel] [PATCH 17/25] q35: Add kvmclock support Jason Baron
` (10 subsequent siblings)
26 siblings, 1 reply; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
From: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pci.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 55e4ad3..3727afa 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1203,6 +1203,7 @@ static const pci_class_desc pci_class_descriptions[] =
{ 0x0c02, "SSA controller", "ssa"},
{ 0x0c03, "USB controller", "usb"},
{ 0x0c04, "Fibre channel controller", "fibre-channel"},
+ { 0x0c05, "SMBus"},
{ 0, NULL}
};
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 17/25] q35: Add kvmclock support
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (15 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 16/25] pci: Add class 0xc05 as 'SMBus' Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 19/25] ahci: add migration support Jason Baron
` (9 subsequent siblings)
26 siblings, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
From: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pc_q35.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
index 9d58519..b8c1196 100644
--- a/hw/pc_q35.c
+++ b/hw/pc_q35.c
@@ -69,6 +69,7 @@
#include "mc146818rtc.h"
#include "xen.h"
#include "kvm.h"
+#include "kvm/clock.h"
#include "q35.h"
#include "exec-memory.h"
@@ -357,6 +358,8 @@ static void pc_q35_init(ram_addr_t ram_size,
pc_cpus_init(cpu_model);
+ kvmclock_create();
+
if (ram_size >= 0xe0000000) {
above_4g_mem_size = ram_size - 0xe0000000;
below_4g_mem_size = 0xe0000000;
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 19/25] ahci: add migration support
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (16 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 17/25] q35: Add kvmclock support Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-14 8:38 ` Juan Quintela
2012-09-13 20:12 ` [Qemu-devel] [PATCH 18/25] q35: Fix irr initialization for slots 25..31 Jason Baron
` (8 subsequent siblings)
26 siblings, 1 reply; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: kwolf, aliguori, alex.williamson, mst, jan.kiszka, quintela,
agraf, armbru, yamahata, juzhang, kevin, avi, mkletzan,
i.mitsyanko, lcapitulino, afaerber
Add support for ahci migration. This patch builds upon the patches originally
posted by Andreas Färber.
These patches have been tested by migrating Windows 7 and Fedora 16 guests on
both piix with ahci attached and on q35 (which has a built-in ahci controller).
Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Alexander Graf <agraf@suse.de>
Cc: Jason Baron <jbaron@redhat.com>
Cc: Kevin Wolf <kwolf@redhat.com>
Cc: Juan Quintela <quintela@redhat.com>
Cc: Igor Mitsyanko <i.mitsyanko@samsung.com>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
v3:
-map command list base addr and fis base addr at destination
-drop port_no
-make use of VMSTATE_STRUCT_VARRAY_POINTER_INT32
hw/ide/ahci.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
hw/ide/ahci.h | 10 +++++++++
hw/ide/ich.c | 11 +++++++--
3 files changed, 81 insertions(+), 4 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 9561210..3d41771 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -1203,6 +1203,65 @@ void ahci_reset(AHCIState *s)
}
}
+static const VMStateDescription vmstate_ahci_device = {
+ .name = "ahci port",
+ .version_id = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_IDE_BUS(port, AHCIDevice),
+ VMSTATE_UINT32(port_state, AHCIDevice),
+ VMSTATE_UINT32(finished, AHCIDevice),
+ VMSTATE_UINT32(port_regs.lst_addr, AHCIDevice),
+ VMSTATE_UINT32(port_regs.lst_addr_hi, AHCIDevice),
+ VMSTATE_UINT32(port_regs.fis_addr, AHCIDevice),
+ VMSTATE_UINT32(port_regs.fis_addr_hi, AHCIDevice),
+ VMSTATE_UINT32(port_regs.irq_stat, AHCIDevice),
+ VMSTATE_UINT32(port_regs.irq_mask, AHCIDevice),
+ VMSTATE_UINT32(port_regs.cmd, AHCIDevice),
+ VMSTATE_UINT32(port_regs.tfdata, AHCIDevice),
+ VMSTATE_UINT32(port_regs.sig, AHCIDevice),
+ VMSTATE_UINT32(port_regs.scr_stat, AHCIDevice),
+ VMSTATE_UINT32(port_regs.scr_ctl, AHCIDevice),
+ VMSTATE_UINT32(port_regs.scr_err, AHCIDevice),
+ VMSTATE_UINT32(port_regs.scr_act, AHCIDevice),
+ VMSTATE_UINT32(port_regs.cmd_issue, AHCIDevice),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+static int ahci_state_post_load(void *opaque, int version_id)
+{
+ int i;
+ AHCIState *s = opaque;
+
+ for (i = 0; i < s->ports; i++) {
+ AHCIPortRegs *pr = &s->dev[i].port_regs;
+
+ map_page(&s->dev[i].lst,
+ ((uint64_t)pr->lst_addr_hi << 32) | pr->lst_addr, 1024);
+ map_page(&s->dev[i].res_fis,
+ ((uint64_t)pr->fis_addr_hi << 32) | pr->fis_addr, 256);
+ }
+
+ return 0;
+}
+
+const VMStateDescription vmstate_ahci = {
+ .name = "ahci",
+ .version_id = 1,
+ .post_load = ahci_state_post_load,
+ .fields = (VMStateField []) {
+ VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports,
+ vmstate_ahci_device, AHCIDevice),
+ VMSTATE_UINT32(control_regs.cap, AHCIState),
+ VMSTATE_UINT32(control_regs.ghc, AHCIState),
+ VMSTATE_UINT32(control_regs.irqstatus, AHCIState),
+ VMSTATE_UINT32(control_regs.impl, AHCIState),
+ VMSTATE_UINT32(control_regs.version, AHCIState),
+ VMSTATE_UINT32(idp_index, AHCIState),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
typedef struct SysbusAHCIState {
SysBusDevice busdev;
AHCIState ahci;
@@ -1211,7 +1270,10 @@ typedef struct SysbusAHCIState {
static const VMStateDescription vmstate_sysbus_ahci = {
.name = "sysbus-ahci",
- .unmigratable = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_AHCI(ahci, AHCIPCIState),
+ VMSTATE_END_OF_LIST()
+ },
};
static void sysbus_ahci_reset(DeviceState *dev)
diff --git a/hw/ide/ahci.h b/hw/ide/ahci.h
index 1200a56..7719dbf 100644
--- a/hw/ide/ahci.h
+++ b/hw/ide/ahci.h
@@ -307,6 +307,16 @@ typedef struct AHCIPCIState {
AHCIState ahci;
} AHCIPCIState;
+extern const VMStateDescription vmstate_ahci;
+
+#define VMSTATE_AHCI(_field, _state) { \
+ .name = (stringify(_field)), \
+ .size = sizeof(AHCIState), \
+ .vmsd = &vmstate_ahci, \
+ .flags = VMS_STRUCT, \
+ .offset = vmstate_offset_value(_state, _field, AHCIState), \
+}
+
typedef struct NCQFrame {
uint8_t fis_type;
uint8_t c;
diff --git a/hw/ide/ich.c b/hw/ide/ich.c
index 272b773..ae6f56f 100644
--- a/hw/ide/ich.c
+++ b/hw/ide/ich.c
@@ -79,9 +79,14 @@
#define ICH9_IDP_INDEX 0x10
#define ICH9_IDP_INDEX_LOG2 0x04
-static const VMStateDescription vmstate_ahci = {
+static const VMStateDescription vmstate_ich9_ahci = {
.name = "ahci",
- .unmigratable = 1,
+ .version_id = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_PCI_DEVICE(card, AHCIPCIState),
+ VMSTATE_AHCI(ahci, AHCIPCIState),
+ VMSTATE_END_OF_LIST()
+ },
};
static void pci_ich9_reset(DeviceState *dev)
@@ -152,7 +157,7 @@ static void ich_ahci_class_init(ObjectClass *klass, void *data)
k->device_id = PCI_DEVICE_ID_INTEL_82801IR;
k->revision = 0x02;
k->class_id = PCI_CLASS_STORAGE_SATA;
- dc->vmsd = &vmstate_ahci;
+ dc->vmsd = &vmstate_ich9_ahci;
dc->reset = pci_ich9_reset;
}
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 18/25] q35: Fix irr initialization for slots 25..31
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (17 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 19/25] ahci: add migration support Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-14 7:05 ` Paolo Bonzini
2012-09-13 20:12 ` [Qemu-devel] [PATCH 20/25] pcie: drop version_id field for live migration Jason Baron
` (7 subsequent siblings)
26 siblings, 1 reply; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
From: Isaku Yamahata <yamahata@valinux.co.jp>
This was totally off: The CC registers are 16 bit (stored as little
endian), their offsets run in reverse order, and D26IR as well as D25IR
have 4 bytes offset to their successors.
Reported-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/q35.c | 29 ++++++++++++++++++++---------
1 files changed, 20 insertions(+), 9 deletions(-)
diff --git a/hw/q35.c b/hw/q35.c
index 8b6a2e5..295344e 100644
--- a/hw/q35.c
+++ b/hw/q35.c
@@ -474,7 +474,7 @@ static void ich9_lpc_reset(DeviceState *qdev);
* Although it's not pci configuration space, it's little endian as Intel.
*/
-static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
+static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir)
{
int intx;
for (intx = 0; intx < PCI_NUM_PINS; intx++) {
@@ -485,15 +485,26 @@ static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
static void ich9_cc_update(ICH9_LPCState *lpc)
{
int slot;
- int reg_offset;
- int intx;
+ int pci_intx;
+
+ const int reg_offsets[] = {
+ ICH9_CC_D25IR,
+ ICH9_CC_D26IR,
+ ICH9_CC_D27IR,
+ ICH9_CC_D28IR,
+ ICH9_CC_D29IR,
+ ICH9_CC_D30IR,
+ ICH9_CC_D31IR,
+ };
+ const int *offset;
/* D{25 - 31}IR, but D30IR is read only to 0. */
- for (slot = 25, reg_offset = 0; slot < 32; slot++, reg_offset++) {
- if (slot != 30) {
- ich9_cc_update_ir(lpc->irr[slot],
- lpc->chip_config[ICH9_CC_D31IR + reg_offset]);
+ for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) {
+ if (slot == 30) {
+ continue;
}
+ ich9_cc_update_ir(lpc->irr[slot],
+ pci_get_word(lpc->chip_config + *offset));
}
/*
@@ -502,8 +513,8 @@ static void ich9_cc_update(ICH9_LPCState *lpc)
* are connected to pirq lines. Our choice is PIRQ[E-H].
* INT[A-D] are connected to PIRQ[E-H]
*/
- for (intx = 0; intx < PCI_NUM_PINS; intx++) {
- lpc->irr[30][intx] = intx + 4;
+ for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) {
+ lpc->irr[30][pci_intx] = pci_intx + 4;
}
}
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 20/25] pcie: drop version_id field for live migration
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (18 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 18/25] q35: Fix irr initialization for slots 25..31 Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 21/25] pcie_aer: clear cmask for Advanced Error Interrupt Message Number Jason Baron
` (6 subsequent siblings)
26 siblings, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
While testing q35 live migration, I found that the migration would abort with
the following error: "Unknown savevm section type 76".
The error is due to this check failing in 'vmstate_load_state()':
while(field->name) {
if ((field->field_exists &&
field->field_exists(opaque, version_id)) ||
(!field->field_exists &&
field->version_id <= version_id)) {
The VMSTATE_PCIE_DEVICE() currently has a 'version_id' set to 2. However,
'version_id' in the above check is 1. And thus we fail to load the pcie device
field. Further the code returns to 'qemu_loadvm_state()' which produces the
error that I saw.
I'm proposing to fix this by simply dropping the 'version_id' field from
VMSTATE_PCIE_DEVICE(). VMSTATE_PCI_DEVICE() defines no such field and further
the vmstate_pcie_device that VMSTATE_PCI_DEVICE() refers to is already
versioned. Thus, any versioning issues could be detected at the vmsd level.
Taking a step back, I think that the 'field->version_id' should be compared
against a saved version number for the field not the 'version_id'. Futhermore,
once vmstate_load_state() is called recursively on another vmsd, the check of:
if (version_id > vmsd->version_id) {
return -EINVAL;
}
Will never fail since version_id is always equal to vmsd->version_id. So I'm
wondering why we aren't storing the vmsd version id of the source in the
migration stream?
This patch also renames the 'name' field of vmstate_pcie_device from:
PCIDevice -> PCIEDevice to differentiate it from vmstate_pci_device.
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pci.c | 2 +-
hw/pcie.h | 1 -
2 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 3727afa..5386a4f 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -439,7 +439,7 @@ const VMStateDescription vmstate_pci_device = {
};
const VMStateDescription vmstate_pcie_device = {
- .name = "PCIDevice",
+ .name = "PCIEDevice",
.version_id = 2,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
diff --git a/hw/pcie.h b/hw/pcie.h
index b8ab0c7..4889194 100644
--- a/hw/pcie.h
+++ b/hw/pcie.h
@@ -133,7 +133,6 @@ extern const VMStateDescription vmstate_pcie_device;
#define VMSTATE_PCIE_DEVICE(_field, _state) { \
.name = (stringify(_field)), \
- .version_id = 2, \
.size = sizeof(PCIDevice), \
.vmsd = &vmstate_pcie_device, \
.flags = VMS_STRUCT, \
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 22/25] ahci: properly reset PxCMD on HBA reset
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (20 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 21/25] pcie_aer: clear cmask for Advanced Error Interrupt Message Number Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 23/25] q35: add acpi-based pci hotplug Jason Baron
` (4 subsequent siblings)
26 siblings, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
While testing q35, I found that windows 7 (specifically, windows 7 ultimate
with sp1 x64), wouldn't install because it can't find the cdrom or disk drive.
The failure message is: 'A required cd/dvd device driver is missing. If you
have a driver floppy disk, CD, DVD, or USB flash drive, please insert it now.'
This can also be reproduced on piix by adding an ahci controller, and
observing that windows 7 does not see any devices behind it.
The problem is that when windows issues a HBA reset, qemu does not reset the
individual ports' PxCMD register. Windows 7 then reads back the PxCMD register
and presumably assumes that the ahci controller has already been initialized.
Windows then never sets up the PxIE register to enable interrupts, and thus it
never gets irqs back when it sends ata device inquiry commands.
This change brings qemu into ahci 1.3 specification compliance.
Section 10.4.3 HBA Reset:
"
When GHC.HR is set to ‘1’, GHC.AE, GHC.IE, the IS register, and all port
register fields (except PxFB/PxFBU/PxCLB/PxCLBU) that are not HwInit in the
HBA’s register memory space are reset.
"
I've also re-tested Fedora 16 and 17 to verify that they continue to work with
this change.
Signed-off-by: Jason Baron <jbaron@redhat.com>
changes in v2:
-From Kevin Wolf:
-continue to set PORT_CMD_SPIN_UP, PORT_CMD_POWER_ON on reset
---
hw/ide/ahci.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
index 3d41771..97a0fa9 100644
--- a/hw/ide/ahci.c
+++ b/hw/ide/ahci.c
@@ -1175,7 +1175,6 @@ void ahci_init(AHCIState *s, DeviceState *qdev, DMAContext *dma, int ports)
ad->port_no = i;
ad->port.dma = &ad->dma;
ad->port.dma->ops = &ahci_dma_ops;
- ad->port_regs.cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON;
}
}
@@ -1199,6 +1198,7 @@ void ahci_reset(AHCIState *s)
pr->irq_stat = 0;
pr->irq_mask = 0;
pr->scr_ctl = 0;
+ pr->cmd = PORT_CMD_SPIN_UP | PORT_CMD_POWER_ON;
ahci_reset_port(s, i);
}
}
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 21/25] pcie_aer: clear cmask for Advanced Error Interrupt Message Number
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (19 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 20/25] pcie: drop version_id field for live migration Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 22/25] ahci: properly reset PxCMD on HBA reset Jason Baron
` (5 subsequent siblings)
26 siblings, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
The Advanced Error Interrupt Message Number (bits 31:27 of the Root
Error Status Register) is updated when the number of msi messages assigned to a
device changes. Migration of windows 7 on q35 chipset failed because the check
in get_pci_config_device() fails due to cmask being set on these bits. Its valid
to update these bits and we must restore this state across migration.
Signed-off-by: Jason Baron <jbaron@redhat.com>
v2:
- Based on Michael Tsirkin's feedback:
-updated changelog 'wmask' -> 'cmask'
-Cleaned up comments
-Make cmask set more readable
---
hw/pcie_aer.c | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/hw/pcie_aer.c b/hw/pcie_aer.c
index 3b6981c..b04c164 100644
--- a/hw/pcie_aer.c
+++ b/hw/pcie_aer.c
@@ -738,6 +738,11 @@ void pcie_aer_root_init(PCIDevice *dev)
PCI_ERR_ROOT_CMD_EN_MASK);
pci_set_long(dev->w1cmask + pos + PCI_ERR_ROOT_STATUS,
PCI_ERR_ROOT_STATUS_REPORT_MASK);
+ /* PCI_ERR_ROOT_IRQ is RO but devices change it using a
+ * device-specific method.
+ */
+ pci_set_long(dev->cmask + pos + PCI_ERR_ROOT_STATUS,
+ ~PCI_ERR_ROOT_IRQ);
}
void pcie_aer_root_reset(PCIDevice *dev)
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 23/25] q35: add acpi-based pci hotplug.
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (21 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 22/25] ahci: properly reset PxCMD on HBA reset Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-14 18:56 ` Blue Swirl
2012-09-13 20:12 ` [Qemu-devel] [PATCH 24/25] Add a fallback bios file search, if -L fails Jason Baron
` (3 subsequent siblings)
26 siblings, 1 reply; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
Add piix style acpi hotplug to q35.
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/acpi_ich9.c | 173 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-
hw/acpi_ich9.h | 10 +++
2 files changed, 182 insertions(+), 1 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
index 570ce0c..ba463a0 100644
--- a/hw/acpi_ich9.c
+++ b/hw/acpi_ich9.c
@@ -41,6 +41,13 @@ do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
#define ICH9_DEBUG(fmt, ...) do { } while (0)
#endif
+#define PCI_UP_BASE 0xae00
+#define PCI_DOWN_BASE 0xae04
+#define PCI_EJ_BASE 0xae08
+#define PCI_RMV_BASE 0xae0c
+#define ICH9_PCI_HOTPLUG_STATUS 2
+
+
static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
uint32_t val);
static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len);
@@ -55,7 +62,10 @@ static void pm_update_sci(ICH9_LPCPmRegs *pm)
(ACPI_BITMASK_RT_CLOCK_ENABLE |
ACPI_BITMASK_POWER_BUTTON_ENABLE |
ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
- ACPI_BITMASK_TIMER_ENABLE)) != 0);
+ ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
+ (((pm->acpi_regs.gpe.sts[0] & pm->acpi_regs.gpe.en[0])
+ & ICH9_PCI_HOTPLUG_STATUS) != 0);
+
qemu_set_irq(pm->irq, sci_level);
/* schedule a timer interruption if needed */
@@ -77,6 +87,7 @@ static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
switch (addr & ICH9_PMIO_MASK) {
case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
+ pm_update_sci(pm);
break;
default:
break;
@@ -283,6 +294,65 @@ const VMStateDescription vmstate_ich9_pm = {
}
};
+static void acpi_ich9_eject_slot(ICH9_LPCPmRegs *opaque, unsigned slots)
+{
+ BusChild *kid, *next;
+ ICH9_LPCPmRegs *pm = opaque;
+ ICH9_LPCState *lpc = container_of(pm, ICH9_LPCState, pm);
+ PCIDevice *s = PCI_DEVICE(lpc);
+ BusState *bus = qdev_get_parent_bus(&s->qdev);
+ int slot = ffs(slots) - 1;
+ bool slot_free = true;
+
+ /* Mark request as complete */
+ pm->pci0_status.down &= ~(1U << slot);
+
+ QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
+ DeviceState *qdev = kid->child;
+ PCIDevice *dev = PCI_DEVICE(qdev);
+ PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
+ if (PCI_SLOT(dev->devfn) == slot) {
+ if (pc->no_hotplug) {
+ slot_free = false;
+ } else {
+ qdev_free(qdev);
+ }
+ }
+ }
+ if (slot_free) {
+ pm->pci0_slot_device_present &= ~(1U << slot);
+ }
+}
+
+static void acpi_ich9_update_hotplug(ICH9_LPCPmRegs *pm)
+{
+ ICH9_LPCState *lpc = container_of(pm, ICH9_LPCState, pm);
+ PCIDevice *dev = PCI_DEVICE(lpc);
+ BusState *bus = qdev_get_parent_bus(&dev->qdev);
+ BusChild *kid, *next;
+
+ /* Execute any pending removes during reset */
+ while (pm->pci0_status.down) {
+ acpi_ich9_eject_slot(pm, pm->pci0_status.down);
+ }
+
+ pm->pci0_hotplug_enable = ~0;
+ pm->pci0_slot_device_present = 0;
+
+ QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
+ DeviceState *qdev = kid->child;
+ PCIDevice *pdev = PCI_DEVICE(qdev);
+ PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev);
+ int slot = PCI_SLOT(pdev->devfn);
+
+ if (pc->no_hotplug) {
+ pm->pci0_hotplug_enable &= ~(1U << slot);
+ }
+
+ pm->pci0_slot_device_present |= (1U << slot);
+ }
+}
+
static void pm_reset(void *opaque)
{
ICH9_LPCPmRegs *pm = opaque;
@@ -300,6 +370,7 @@ static void pm_reset(void *opaque)
}
pm_update_sci(pm);
+ acpi_ich9_update_hotplug(pm);
}
static void pm_powerdown(void *opaque, int irq, int power_failing)
@@ -309,6 +380,104 @@ static void pm_powerdown(void *opaque, int irq, int power_failing)
acpi_pm1_evt_power_down(&pm->acpi_regs);
}
+static uint32_t pci_up_read(void *opaque, uint32_t addr)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+ uint32_t val;
+
+ /* Manufacture an "up" value to cause a device check on any hotplug
+ * slot with a device. Extra device checks are harmless. */
+ val = pm->pci0_slot_device_present & pm->pci0_hotplug_enable;
+
+ ICH9_DEBUG("pci_up_read %x\n", val);
+ return val;
+}
+
+static uint32_t pci_down_read(void *opaque, uint32_t addr)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+ uint32_t val = pm->pci0_status.down;
+
+ ICH9_DEBUG("pci_down_read %x\n", val);
+ return val;
+}
+
+static uint32_t pci_features_read(void *opaque, uint32_t addr)
+{
+ /* No feature defined yet */
+ ICH9_DEBUG("pci_features_read %x\n", 0);
+ return 0;
+}
+
+static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ acpi_ich9_eject_slot(opaque, val);
+
+ ICH9_DEBUG("pciej write %x <== %d\n", addr, val);
+}
+
+static uint32_t pcirmv_read(void *opaque, uint32_t addr)
+{
+ ICH9_LPCPmRegs *pm = opaque;
+
+ return pm->pci0_hotplug_enable;
+}
+
+static void enable_device(ICH9_LPCPmRegs *pm, int slot)
+{
+ pm->acpi_regs.gpe.sts[0] |= ICH9_PCI_HOTPLUG_STATUS;
+ pm->pci0_slot_device_present |= (1U << slot);
+}
+
+static void disable_device(ICH9_LPCPmRegs *pm, int slot)
+{
+ pm->acpi_regs.gpe.sts[0] |= ICH9_PCI_HOTPLUG_STATUS;
+ pm->pci0_status.down |= (1U << slot);
+}
+
+static int ich9_device_hotplug(DeviceState *qdev, PCIDevice *dev,
+ PCIHotplugState state)
+{
+ int slot = PCI_SLOT(dev->devfn);
+ ICH9_LPCState *lpc = DO_UPCAST(ICH9_LPCState, d,
+ PCI_DEVICE(qdev));
+ ICH9_LPCPmRegs *pm = &lpc->pm;
+
+ /* Don't send event when device is enabled during qemu machine creation:
+ * it is present on boot, no hotplug event is necessary. We do send an
+ * event when the device is disabled later. */
+ if (state == PCI_COLDPLUG_ENABLED) {
+ pm->pci0_slot_device_present |= (1U << slot);
+ return 0;
+ }
+
+ if (state == PCI_HOTPLUG_ENABLED) {
+ enable_device(pm, slot);
+ } else {
+ disable_device(pm, slot);
+ }
+
+ pm_update_sci(pm);
+
+ return 0;
+}
+
+static void ich9_acpi_system_hot_add_init(ICH9_LPCPmRegs *s)
+{
+ ICH9_LPCState *lpc = container_of(s, ICH9_LPCState, pm);
+ PCIDevice *pdev = PCI_DEVICE(lpc);
+
+ register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s);
+ register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s);
+
+ register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s);
+ register_ioport_read(PCI_EJ_BASE, 4, 4, pci_features_read, s);
+
+ register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s);
+
+ pci_bus_hotplug(pdev->bus, ich9_device_hotplug, &pdev->qdev);
+}
+
void ich9_pm_init(ICH9_LPCPmRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
{
acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn);
@@ -318,4 +487,6 @@ void ich9_pm_init(ICH9_LPCPmRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
pm->irq = sci_irq;
qemu_register_reset(pm_reset, pm);
qemu_system_powerdown = *qemu_allocate_irqs(pm_powerdown, pm, 1);
+
+ ich9_acpi_system_hot_add_init(pm);
}
diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h
index 9ff4c42..434e221 100644
--- a/hw/acpi_ich9.h
+++ b/hw/acpi_ich9.h
@@ -23,6 +23,11 @@
#include "acpi.h"
+struct pci_status {
+ uint32_t up; /* deprecated, maintained for migration compatibility */
+ uint32_t down;
+};
+
typedef struct ICH9_LPCPmRegs {
/*
* In ich9 spec says that pm1_cnt register is 32bit width and
@@ -36,6 +41,11 @@ typedef struct ICH9_LPCPmRegs {
qemu_irq irq; /* SCI */
uint32_t pm_io_base;
+
+ /* for pci hotplug */
+ struct pci_status pci0_status;
+ uint32_t pci0_hotplug_enable;
+ uint32_t pci0_slot_device_present;
} ICH9_LPCPmRegs;
void ich9_pm_init(ICH9_LPCPmRegs *pm,
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 25/25] q35: automatically load the q35 dsdt table
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (23 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 24/25] Add a fallback bios file search, if -L fails Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-14 7:08 ` Paolo Bonzini
2012-09-13 22:29 ` [Qemu-devel] [PATCH 00/25] q35 series take #1 Alexander Graf
2012-09-14 15:14 ` Isaku Yamahata
26 siblings, 1 reply; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
Automatically, locate the required q35 dsdt table on load. Otherwise we error
out. This could be done in the bios, but its harder to produce a good error
message.
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
hw/pc_q35.c | 26 ++++++++++++++++++++++++++
1 files changed, 26 insertions(+), 0 deletions(-)
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
index b8c1196..08ae62b 100644
--- a/hw/pc_q35.c
+++ b/hw/pc_q35.c
@@ -329,6 +329,25 @@ static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,
8, NULL, 0);
}
+static int find_and_load_dsdt(const char *dsdt_name)
+{
+ char *filename;
+ char buf[256];
+
+ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dsdt_name);
+ if (!filename) {
+ return -1;
+ }
+
+ snprintf(buf, 256, "file=%s", filename);
+ if (acpi_table_add(buf) < 0) {
+ fprintf(stderr, "Wrong acpi table provided\n");
+ return -1;
+ }
+
+ return 0;
+}
+
/* PC hardware initialisation */
static void pc_q35_init(ram_addr_t ram_size,
const char *boot_device,
@@ -356,6 +375,13 @@ static void pc_q35_init(ram_addr_t ram_size,
qemu_irq *i8259;
int i;
+ /* let's first see if we can find the proper dsdt */
+ if (find_and_load_dsdt("q35-acpi-dsdt.aml")) {
+ fprintf(stderr, "Couldn't find q35 dsdt table!\n"
+ "Try updating your bios.\n");
+ exit(1);
+ }
+
pc_cpus_init(cpu_model);
kvmclock_create();
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* [Qemu-devel] [PATCH 24/25] Add a fallback bios file search, if -L fails.
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (22 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 23/25] q35: add acpi-based pci hotplug Jason Baron
@ 2012-09-13 20:12 ` Jason Baron
2012-09-14 7:09 ` Paolo Bonzini
` (2 more replies)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 25/25] q35: automatically load the q35 dsdt table Jason Baron
` (2 subsequent siblings)
26 siblings, 3 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-13 20:12 UTC (permalink / raw)
To: qemu-devel
Cc: aliguori, alex.williamson, mst, jan.kiszka, agraf, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
If -L <dir> is specified, and qemu does not find the bios file in <dir>, then
the search fails. Add infrastructure such that the search will continue in
the default paths, if not found in the -L path.
Signed-off-by: Jason Baron <jbaron@redhat.com>
---
vl.c | 28 +++++++++++++++++++++-------
1 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/vl.c b/vl.c
index 7c577fa..656a210 100644
--- a/vl.c
+++ b/vl.c
@@ -177,6 +177,7 @@ int main(int argc, char **argv)
#define MAX_VIRTIO_CONSOLES 1
static const char *data_dir;
+static const char *data_dir_fallback;
const char *bios_name = NULL;
enum vga_retrace_method vga_retrace_method = VGA_RETRACE_DUMB;
DisplayType display_type = DT_DEFAULT;
@@ -1872,12 +1873,15 @@ static int balloon_parse(const char *arg)
return -1;
}
-char *qemu_find_file(int type, const char *name)
+static char *__qemu_find_file(int type, const char *name, const char *dir)
{
int len;
const char *subdir;
char *buf;
+ if (!dir)
+ return NULL;
+
/* Try the name as a straight path first */
if (access(name, R_OK) == 0) {
return g_strdup(name);
@@ -1892,9 +1896,9 @@ char *qemu_find_file(int type, const char *name)
default:
abort();
}
- len = strlen(data_dir) + strlen(name) + strlen(subdir) + 2;
+ len = strlen(dir) + strlen(name) + strlen(subdir) + 2;
buf = g_malloc0(len);
- snprintf(buf, len, "%s/%s%s", data_dir, subdir, name);
+ snprintf(buf, len, "%s/%s%s", dir, subdir, name);
if (access(buf, R_OK)) {
g_free(buf);
return NULL;
@@ -1902,6 +1906,18 @@ char *qemu_find_file(int type, const char *name)
return buf;
}
+char *qemu_find_file(int type, const char *name)
+{
+ char *filename;
+
+ filename = __qemu_find_file(type, name, data_dir);
+ if (!filename) {
+ filename = __qemu_find_file(type, name, data_dir_fallback);
+ }
+
+ return filename;
+}
+
static int device_help_func(QemuOpts *opts, void *opaque)
{
return qdev_device_help(opts);
@@ -3338,11 +3354,9 @@ int main(int argc, char **argv, char **envp)
/* If no data_dir is specified then try to find it relative to the
executable path. */
- if (!data_dir) {
- data_dir = os_find_datadir(argv[0]);
- }
+ data_dir_fallback = os_find_datadir(argv[0]);
/* If all else fails use the install path specified when building. */
- if (!data_dir) {
+ if (!data_dir_fallback) {
data_dir = CONFIG_QEMU_DATADIR;
}
--
1.7.1
^ permalink raw reply related [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (24 preceding siblings ...)
2012-09-13 20:12 ` [Qemu-devel] [PATCH 25/25] q35: automatically load the q35 dsdt table Jason Baron
@ 2012-09-13 22:29 ` Alexander Graf
2012-09-14 13:50 ` Jason Baron
2012-09-14 15:14 ` Isaku Yamahata
26 siblings, 1 reply; 74+ messages in thread
From: Alexander Graf @ 2012-09-13 22:29 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, alex.williamson, mst, jan.kiszka, qemu-devel, armbru,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
On 13.09.2012, at 22:12, Jason Baron wrote:
> Hi,
>
> Qemu bits for q35 support, I'm posting the seabios changes separately. The
> patches require '-M pc_q35' and -L 'seabios dir with q35 changes' on the
> qemu command line. Hopefully, we can make it the default for x86 at some future
> point when we feel comfortable with it.
Without having had a real look at the code in detail yet, how did you design the PCI-ISA bridge (LPC device)? I'm asking mostly because Mac OS X unconditionally accesses that device's PCI config space to find the base address of the HPET.
If it's not modeled at all right now, that would certainly be nice to have before we make the machine the default. Until then I would mark it simply as experimental and declare it unstable wrt version coherence.
Alex
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator
2012-09-13 20:12 ` [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator Jason Baron
@ 2012-09-14 7:02 ` Paolo Bonzini
2012-09-14 7:37 ` Gerd Hoffmann
` (2 subsequent siblings)
3 siblings, 0 replies; 74+ messages in thread
From: Paolo Bonzini @ 2012-09-14 7:02 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
Il 13/09/2012 22:12, Jason Baron ha scritto:
> +typedef struct ICH9_LPCIrqState {
> + struct ICH9_LPCState *lpc;
Please add DEFINE_PROP_PTR property for this field in gmch_pcihost_info,
so we know this ought to become a link<ICH9_LPCState> later.
> + qemu_irq *pic;
> + qemu_irq *ioapic;
> +} ICH9_LPCIrqState;
> +
Paolo
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 16/25] pci: Add class 0xc05 as 'SMBus'
2012-09-13 20:12 ` [Qemu-devel] [PATCH 16/25] pci: Add class 0xc05 as 'SMBus' Jason Baron
@ 2012-09-14 7:04 ` Paolo Bonzini
2012-09-14 14:24 ` Jason Baron
0 siblings, 1 reply; 74+ messages in thread
From: Paolo Bonzini @ 2012-09-14 7:04 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
Il 13/09/2012 22:12, Jason Baron ha scritto:
> From: Jan Kiszka <jan.kiszka@siemens.com>
>
> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/pci.c | 1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/hw/pci.c b/hw/pci.c
> index 55e4ad3..3727afa 100644
> --- a/hw/pci.c
> +++ b/hw/pci.c
> @@ -1203,6 +1203,7 @@ static const pci_class_desc pci_class_descriptions[] =
> { 0x0c02, "SSA controller", "ssa"},
> { 0x0c03, "USB controller", "usb"},
> { 0x0c04, "Fibre channel controller", "fibre-channel"},
> + { 0x0c05, "SMBus"},
> { 0, NULL}
> };
>
>
You could move here the corresponding hunk of patch 8/25.
Paolo
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 18/25] q35: Fix irr initialization for slots 25..31
2012-09-13 20:12 ` [Qemu-devel] [PATCH 18/25] q35: Fix irr initialization for slots 25..31 Jason Baron
@ 2012-09-14 7:05 ` Paolo Bonzini
2012-09-14 14:28 ` Jason Baron
0 siblings, 1 reply; 74+ messages in thread
From: Paolo Bonzini @ 2012-09-14 7:05 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
Il 13/09/2012 22:12, Jason Baron ha scritto:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> This was totally off: The CC registers are 16 bit (stored as little
> endian), their offsets run in reverse order, and D26IR as well as D25IR
> have 4 bytes offset to their successors.
>
> Reported-by: Jan Kiszka <jan.kiszka@siemens.com>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/q35.c | 29 ++++++++++++++++++++---------
> 1 files changed, 20 insertions(+), 9 deletions(-)
>
> diff --git a/hw/q35.c b/hw/q35.c
> index 8b6a2e5..295344e 100644
> --- a/hw/q35.c
> +++ b/hw/q35.c
> @@ -474,7 +474,7 @@ static void ich9_lpc_reset(DeviceState *qdev);
> * Although it's not pci configuration space, it's little endian as Intel.
> */
>
> -static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
> +static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir)
> {
> int intx;
> for (intx = 0; intx < PCI_NUM_PINS; intx++) {
> @@ -485,15 +485,26 @@ static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
> static void ich9_cc_update(ICH9_LPCState *lpc)
> {
> int slot;
> - int reg_offset;
> - int intx;
> + int pci_intx;
> +
> + const int reg_offsets[] = {
> + ICH9_CC_D25IR,
> + ICH9_CC_D26IR,
> + ICH9_CC_D27IR,
> + ICH9_CC_D28IR,
> + ICH9_CC_D29IR,
> + ICH9_CC_D30IR,
> + ICH9_CC_D31IR,
> + };
> + const int *offset;
>
> /* D{25 - 31}IR, but D30IR is read only to 0. */
> - for (slot = 25, reg_offset = 0; slot < 32; slot++, reg_offset++) {
> - if (slot != 30) {
> - ich9_cc_update_ir(lpc->irr[slot],
> - lpc->chip_config[ICH9_CC_D31IR + reg_offset]);
> + for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) {
> + if (slot == 30) {
> + continue;
> }
> + ich9_cc_update_ir(lpc->irr[slot],
> + pci_get_word(lpc->chip_config + *offset));
> }
>
> /*
> @@ -502,8 +513,8 @@ static void ich9_cc_update(ICH9_LPCState *lpc)
> * are connected to pirq lines. Our choice is PIRQ[E-H].
> * INT[A-D] are connected to PIRQ[E-H]
> */
> - for (intx = 0; intx < PCI_NUM_PINS; intx++) {
> - lpc->irr[30][intx] = intx + 4;
> + for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) {
> + lpc->irr[30][pci_intx] = pci_intx + 4;
> }
> }
>
>
I guess this patch and patch 12 could/should be squashed in patch 11
(the one that introduces q35.c)?
Paolo
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 25/25] q35: automatically load the q35 dsdt table
2012-09-13 20:12 ` [Qemu-devel] [PATCH 25/25] q35: automatically load the q35 dsdt table Jason Baron
@ 2012-09-14 7:08 ` Paolo Bonzini
2012-09-14 7:25 ` Gerd Hoffmann
0 siblings, 1 reply; 74+ messages in thread
From: Paolo Bonzini @ 2012-09-14 7:08 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
Il 13/09/2012 22:12, Jason Baron ha scritto:
> Automatically, locate the required q35 dsdt table on load. Otherwise we error
> out. This could be done in the bios, but its harder to produce a good error
> message.
>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/pc_q35.c | 26 ++++++++++++++++++++++++++
> 1 files changed, 26 insertions(+), 0 deletions(-)
>
> diff --git a/hw/pc_q35.c b/hw/pc_q35.c
> index b8c1196..08ae62b 100644
> --- a/hw/pc_q35.c
> +++ b/hw/pc_q35.c
> @@ -329,6 +329,25 @@ static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,
> 8, NULL, 0);
> }
>
> +static int find_and_load_dsdt(const char *dsdt_name)
> +{
> + char *filename;
> + char buf[256];
> +
> + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dsdt_name);
> + if (!filename) {
> + return -1;
> + }
> +
> + snprintf(buf, 256, "file=%s", filename);
> + if (acpi_table_add(buf) < 0) {
> + fprintf(stderr, "Wrong acpi table provided\n");
> + return -1;
> + }
> +
> + return 0;
> +}
> +
> /* PC hardware initialisation */
> static void pc_q35_init(ram_addr_t ram_size,
> const char *boot_device,
> @@ -356,6 +375,13 @@ static void pc_q35_init(ram_addr_t ram_size,
> qemu_irq *i8259;
> int i;
>
> + /* let's first see if we can find the proper dsdt */
> + if (find_and_load_dsdt("q35-acpi-dsdt.aml")) {
> + fprintf(stderr, "Couldn't find q35 dsdt table!\n"
> + "Try updating your bios.\n");
> + exit(1);
> + }
> +
> pc_cpus_init(cpu_model);
>
> kvmclock_create();
>
Should we take the PIIX4 DSDT into the QEMU tree, and do the same thing
for PIIX4?
Paolo
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 24/25] Add a fallback bios file search, if -L fails.
2012-09-13 20:12 ` [Qemu-devel] [PATCH 24/25] Add a fallback bios file search, if -L fails Jason Baron
@ 2012-09-14 7:09 ` Paolo Bonzini
2012-09-14 10:54 ` Peter Maydell
2012-09-14 19:15 ` Blue Swirl
2 siblings, 0 replies; 74+ messages in thread
From: Paolo Bonzini @ 2012-09-14 7:09 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
Il 13/09/2012 22:12, Jason Baron ha scritto:
> If -L <dir> is specified, and qemu does not find the bios file in <dir>, then
> the search fails. Add infrastructure such that the search will continue in
> the default paths, if not found in the -L path.
>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
What is this useful for?
> +static char *__qemu_find_file(int type, const char *name, const char *dir)
No __ names in userspace, use qemu_find_file_in_dir.
Paolo
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 25/25] q35: automatically load the q35 dsdt table
2012-09-14 7:08 ` Paolo Bonzini
@ 2012-09-14 7:25 ` Gerd Hoffmann
2012-09-14 7:34 ` Paolo Bonzini
0 siblings, 1 reply; 74+ messages in thread
From: Gerd Hoffmann @ 2012-09-14 7:25 UTC (permalink / raw)
To: Paolo Bonzini
Cc: aliguori, alex.williamson, mst, jan.kiszka, Jason Baron,
qemu-devel, agraf, yamahata, juzhang, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru
On 09/14/12 09:08, Paolo Bonzini wrote:
> Il 13/09/2012 22:12, Jason Baron ha scritto:
>> Automatically, locate the required q35 dsdt table on load. Otherwise we error
>> out. This could be done in the bios, but its harder to produce a good error
>> message.
>> /* PC hardware initialisation */
>> static void pc_q35_init(ram_addr_t ram_size,
>> const char *boot_device,
>> @@ -356,6 +375,13 @@ static void pc_q35_init(ram_addr_t ram_size,
>> qemu_irq *i8259;
>> int i;
>>
>> + /* let's first see if we can find the proper dsdt */
>> + if (find_and_load_dsdt("q35-acpi-dsdt.aml")) {
>> + fprintf(stderr, "Couldn't find q35 dsdt table!\n"
>> + "Try updating your bios.\n");
>> + exit(1);
>> + }
>> +
>> pc_cpus_init(cpu_model);
>>
>> kvmclock_create();
>>
>
> Should we take the PIIX4 DSDT into the QEMU tree, and do the same thing
> for PIIX4?
We should surely have both at the same place. Dunno what the best place
is, we have interactions with both seabios code and acpi tables and qemu
+ acpi tables.
I'd tend to put them into seabios.git, add a config option to select
piix/q35, then go build two bios binaries.
cheers,
Gerd
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 25/25] q35: automatically load the q35 dsdt table
2012-09-14 7:25 ` Gerd Hoffmann
@ 2012-09-14 7:34 ` Paolo Bonzini
0 siblings, 0 replies; 74+ messages in thread
From: Paolo Bonzini @ 2012-09-14 7:34 UTC (permalink / raw)
To: Gerd Hoffmann
Cc: aliguori, alex.williamson, mst, jan.kiszka, Jason Baron,
qemu-devel, agraf, yamahata, juzhang, kevin, avi, mkletzan,
lcapitulino, afaerber, armbru
Il 14/09/2012 09:25, Gerd Hoffmann ha scritto:
>> >
>> > Should we take the PIIX4 DSDT into the QEMU tree, and do the same thing
>> > for PIIX4?
> We should surely have both at the same place. Dunno what the best place
> is, we have interactions with both seabios code and acpi tables and qemu
> + acpi tables.
>
> I'd tend to put them into seabios.git, add a config option to select
> piix/q35, then go build two bios binaries.
Let's discuss it in the SeaBIOS mailing list.
Paolo
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator
2012-09-13 20:12 ` [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator Jason Baron
2012-09-14 7:02 ` Paolo Bonzini
@ 2012-09-14 7:37 ` Gerd Hoffmann
2012-09-14 14:11 ` Jason Baron
2012-09-18 21:28 ` Alex Williamson
2012-09-14 12:26 ` Michael S. Tsirkin
2012-09-15 18:14 ` Michael S. Tsirkin
3 siblings, 2 replies; 74+ messages in thread
From: Gerd Hoffmann @ 2012-09-14 7:37 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On 09/13/12 22:12, Jason Baron wrote:
> + if (ram_size >= 0xe0000000) {
> + above_4g_mem_size = ram_size - 0xe0000000;
> + below_4g_mem_size = 0xe0000000;
We should make the hole larger to get more pci i/o address space below
4G, especially as q35 needs a good chunk of it for mmconfig.
I think at least 0xc0000000, maybe even 0xb0000000. The later would
allow to place mmconfig @ 0xb0000000, one big 512MB pci bar @ 0xc0000000
(think gfx card pass-through) and all the remaining little stuff above
0xe0000000.
cheers,
Gerd
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 19/25] ahci: add migration support
2012-09-13 20:12 ` [Qemu-devel] [PATCH 19/25] ahci: add migration support Jason Baron
@ 2012-09-14 8:38 ` Juan Quintela
0 siblings, 0 replies; 74+ messages in thread
From: Juan Quintela @ 2012-09-14 8:38 UTC (permalink / raw)
To: Jason Baron
Cc: kwolf, aliguori, alex.williamson, mst, jan.kiszka, qemu-devel,
agraf, yamahata, juzhang, kevin, avi, mkletzan, i.mitsyanko,
lcapitulino, afaerber, armbru
Jason Baron <jbaron@redhat.com> wrote:
> Add support for ahci migration. This patch builds upon the patches originally
> posted by Andreas Färber.
>
> These patches have been tested by migrating Windows 7 and Fedora 16 guests on
> both piix with ahci attached and on q35 (which has a built-in ahci controller).
> +const VMStateDescription vmstate_ahci = {
> + .name = "ahci",
> + .version_id = 1,
> + .post_load = ahci_state_post_load,
> + .fields = (VMStateField []) {
+ VMSTATE_INT32_EQUAL(ports, AHCIState),
> + VMSTATE_STRUCT_VARRAY_POINTER_INT32(dev, AHCIState, ports,
> + vmstate_ahci_device, AHCIDevice),
> + VMSTATE_UINT32(control_regs.cap, AHCIState),
> + VMSTATE_UINT32(control_regs.ghc, AHCIState),
> + VMSTATE_UINT32(control_regs.irqstatus, AHCIState),
> + VMSTATE_UINT32(control_regs.impl, AHCIState),
> + VMSTATE_UINT32(control_regs.version, AHCIState),
> + VMSTATE_UINT32(idp_index, AHCIState),
> + VMSTATE_END_OF_LIST()
> + },
> +};
> +
Only comment that I have is if we can add that bit on the vmstate
transition. That way we can detect when the number of ports between the
two instances are different.
You can change it to; (it checks that ports received is less ore equal
than original value):
+ VMSTATE_INT32_LE(ports, AHCIState),
If the code will work if we transfer less ports that are active. I have
no clue which one makes more sense from the ahci point of view.
Thanks, Juan.
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 24/25] Add a fallback bios file search, if -L fails.
2012-09-13 20:12 ` [Qemu-devel] [PATCH 24/25] Add a fallback bios file search, if -L fails Jason Baron
2012-09-14 7:09 ` Paolo Bonzini
@ 2012-09-14 10:54 ` Peter Maydell
2012-09-14 19:15 ` Blue Swirl
2 siblings, 0 replies; 74+ messages in thread
From: Peter Maydell @ 2012-09-14 10:54 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On 13 September 2012 21:12, Jason Baron <jbaron@redhat.com> wrote:
> If -L <dir> is specified, and qemu does not find the bios file in <dir>, then
> the search fails. Add infrastructure such that the search will continue in
> the default paths, if not found in the -L path.
> @@ -1872,12 +1873,15 @@ static int balloon_parse(const char *arg)
> return -1;
> }
>
> -char *qemu_find_file(int type, const char *name)
> +static char *__qemu_find_file(int type, const char *name, const char *dir)
> {
> int len;
> const char *subdir;
> char *buf;
>
> + if (!dir)
> + return NULL;
> +
> /* Try the name as a straight path first */
> if (access(name, R_OK) == 0) {
> return g_strdup(name);
This means that every try with a different directory will
check the name as a straight path again, which is a bit
pointless. The "just try the name" code shouldn't be in
this function (which as Paolo suggests should be named
qemu_find_file_in_dir()), it should be pulled out into
your new qemu_find_file(), which will then look like:
* try as plain pathname
* try in directory 1
* try in directory 2
-- PMM
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator
2012-09-13 20:12 ` [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator Jason Baron
2012-09-14 7:02 ` Paolo Bonzini
2012-09-14 7:37 ` Gerd Hoffmann
@ 2012-09-14 12:26 ` Michael S. Tsirkin
2012-09-14 15:20 ` Jason Baron
2012-09-15 18:14 ` Michael S. Tsirkin
3 siblings, 1 reply; 74+ messages in thread
From: Michael S. Tsirkin @ 2012-09-14 12:26 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, alex.williamson, jan.kiszka, qemu-devel, agraf,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On Thu, Sep 13, 2012 at 04:12:42PM -0400, Jason Baron wrote:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> pc q35 based chipset emulator to support pci express natively.
>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
I think it's best to smash the following patch into this one
otherwise review becomes painful. Some short notes:
> ---
> hw/acpi_ich9.c | 315 ++++++++++++++++++
> hw/acpi_ich9.h | 53 +++
> hw/i386/Makefile.objs | 1 +
> hw/pc_q35.c | 378 +++++++++++++++++++++
> hw/pci_ids.h | 14 +
> hw/q35.c | 877 +++++++++++++++++++++++++++++++++++++++++++++++++
> hw/q35.h | 272 +++++++++++++++
> hw/q35_smbus.c | 154 +++++++++
> 8 files changed, 2064 insertions(+), 0 deletions(-)
> create mode 100644 hw/acpi_ich9.c
> create mode 100644 hw/acpi_ich9.h
> create mode 100644 hw/pc_q35.c
> create mode 100644 hw/q35.c
> create mode 100644 hw/q35.h
> create mode 100644 hw/q35_smbus.c
>
> diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
> new file mode 100644
> index 0000000..59c0807
> --- /dev/null
> +++ b/hw/acpi_ich9.c
> @@ -0,0 +1,315 @@
> +/*
> + * ACPI implementation
> + *
> + * Copyright (c) 2006 Fabrice Bellard
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License version 2 as published by the Free Software Foundation.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>
> + */
> +/*
> + * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + *
Probably two headers should be combined.
> + * This is based on acpi.c.
This should probably go into commit log instead.
> + */
..
> diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h
> new file mode 100644
> index 0000000..f55c0e9
> --- /dev/null
> +++ b/hw/acpi_ich9.h
> @@ -0,0 +1,53 @@
> +/*
> + * QEMU GMCH/ICH9 LPC PM Emulation
> + *
> + * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>
> + */
> +
> +#ifndef HW_ACPI_ICH9_H
> +#define HW_ACPI_ICH9_H
> +
> +#include "acpi.h"
> +
> +typedef struct ICH9_LPCPmRegs {
This naming scheme conflicts with qemu coding style.
Pls use Ich9LpcPmRegs or something.
Same comment applies everywhere.
--
MST
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
2012-09-13 22:29 ` [Qemu-devel] [PATCH 00/25] q35 series take #1 Alexander Graf
@ 2012-09-14 13:50 ` Jason Baron
2012-09-14 13:56 ` Alexander Graf
0 siblings, 1 reply; 74+ messages in thread
From: Jason Baron @ 2012-09-14 13:50 UTC (permalink / raw)
To: Alexander Graf
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, armbru, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber
On Fri, Sep 14, 2012 at 12:29:17AM +0200, Alexander Graf wrote:
> On 13.09.2012, at 22:12, Jason Baron wrote:
>
> > Hi,
> >
> > Qemu bits for q35 support, I'm posting the seabios changes separately. The
> > patches require '-M pc_q35' and -L 'seabios dir with q35 changes' on the
> > qemu command line. Hopefully, we can make it the default for x86 at some future
> > point when we feel comfortable with it.
>
> Without having had a real look at the code in detail yet, how did you design the PCI-ISA bridge (LPC device)? I'm asking mostly because Mac OS X unconditionally accesses that device's PCI config space to find the base address of the HPET.
>
The LPC device is inherits from TYPE_PCI_DEVICE, and has modeling for
configuring pmbase (where the power management io region resides) and
for configuring pirq irq routing. It does not have the addr for the
HPET. I'll have to check the spec and see where it resides.
> If it's not modeled at all right now, that would certainly be nice to have before we make the machine the default. Until then I would mark it simply as experimental and declare it unstable wrt version coherence.
>
ok, I haven't played with Mac OS X yet on q35, but its something I would
really like to have working - my focus has been on linux and windows
guests.
Thanks,
-Jason
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
2012-09-14 13:50 ` Jason Baron
@ 2012-09-14 13:56 ` Alexander Graf
2012-09-14 14:08 ` Jason Baron
0 siblings, 1 reply; 74+ messages in thread
From: Alexander Graf @ 2012-09-14 13:56 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, armbru, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber
On 14.09.2012, at 15:50, Jason Baron wrote:
> On Fri, Sep 14, 2012 at 12:29:17AM +0200, Alexander Graf wrote:
>> On 13.09.2012, at 22:12, Jason Baron wrote:
>>
>>> Hi,
>>>
>>> Qemu bits for q35 support, I'm posting the seabios changes separately. The
>>> patches require '-M pc_q35' and -L 'seabios dir with q35 changes' on the
>>> qemu command line. Hopefully, we can make it the default for x86 at some future
>>> point when we feel comfortable with it.
>>
>> Without having had a real look at the code in detail yet, how did you design the PCI-ISA bridge (LPC device)? I'm asking mostly because Mac OS X unconditionally accesses that device's PCI config space to find the base address of the HPET.
>>
>
> The LPC device is inherits from TYPE_PCI_DEVICE, and has modeling for
> configuring pmbase (where the power management io region resides) and
> for configuring pirq irq routing. It does not have the addr for the
> HPET. I'll have to check the spec and see where it resides.
I have a patch that creates a fake lpc device with the correct regions to make osx happy:
http://svn.exactcode.de/t2/trunk/package/emulators/kvm/03-qemu-lpc.patch.disable
That might be useful as a starting point :).
Alex
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
2012-09-14 13:56 ` Alexander Graf
@ 2012-09-14 14:08 ` Jason Baron
2012-09-14 14:12 ` Alexander Graf
0 siblings, 1 reply; 74+ messages in thread
From: Jason Baron @ 2012-09-14 14:08 UTC (permalink / raw)
To: Alexander Graf
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, armbru, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber
On Fri, Sep 14, 2012 at 03:56:17PM +0200, Alexander Graf wrote:
> On 14.09.2012, at 15:50, Jason Baron wrote:
>
> > On Fri, Sep 14, 2012 at 12:29:17AM +0200, Alexander Graf wrote:
> >> On 13.09.2012, at 22:12, Jason Baron wrote:
> >>
> >>> Hi,
> >>>
> >>> Qemu bits for q35 support, I'm posting the seabios changes separately. The
> >>> patches require '-M pc_q35' and -L 'seabios dir with q35 changes' on the
> >>> qemu command line. Hopefully, we can make it the default for x86 at some future
> >>> point when we feel comfortable with it.
> >>
> >> Without having had a real look at the code in detail yet, how did you design the PCI-ISA bridge (LPC device)? I'm asking mostly because Mac OS X unconditionally accesses that device's PCI config space to find the base address of the HPET.
> >>
> >
> > The LPC device is inherits from TYPE_PCI_DEVICE, and has modeling for
> > configuring pmbase (where the power management io region resides) and
> > for configuring pirq irq routing. It does not have the addr for the
> > HPET. I'll have to check the spec and see where it resides.
>
> I have a patch that creates a fake lpc device with the correct regions to make osx happy:
>
> http://svn.exactcode.de/t2/trunk/package/emulators/kvm/03-qemu-lpc.patch.disable
>
> That might be useful as a starting point :).
>
cool! I'll pull in the bits I'm missing.
Thanks,
-Jason
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator
2012-09-14 7:37 ` Gerd Hoffmann
@ 2012-09-14 14:11 ` Jason Baron
2012-09-18 21:28 ` Alex Williamson
1 sibling, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-14 14:11 UTC (permalink / raw)
To: Gerd Hoffmann
Cc: aliguori, alex.williamson, mst, jan.kiszka, qemu-devel, agraf,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On Fri, Sep 14, 2012 at 09:37:03AM +0200, Gerd Hoffmann wrote:
> On 09/13/12 22:12, Jason Baron wrote:
> > + if (ram_size >= 0xe0000000) {
> > + above_4g_mem_size = ram_size - 0xe0000000;
> > + below_4g_mem_size = 0xe0000000;
>
> We should make the hole larger to get more pci i/o address space below
> 4G, especially as q35 needs a good chunk of it for mmconfig.
>
> I think at least 0xc0000000, maybe even 0xb0000000. The later would
> allow to place mmconfig @ 0xb0000000, one big 512MB pci bar @ 0xc0000000
> (think gfx card pass-through) and all the remaining little stuff above
> 0xe0000000.
>
> cheers,
> Gerd
>
>
Ok, I had played with increasing the pci hole (and corresponding dsdt
table changes), I can try going to a bigger size as you suggest.
Thanks,
-Jason
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
2012-09-14 14:08 ` Jason Baron
@ 2012-09-14 14:12 ` Alexander Graf
2012-09-14 15:37 ` Kevin Wolf
0 siblings, 1 reply; 74+ messages in thread
From: Alexander Graf @ 2012-09-14 14:12 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, armbru, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber
On 14.09.2012, at 16:08, Jason Baron wrote:
> On Fri, Sep 14, 2012 at 03:56:17PM +0200, Alexander Graf wrote:
>> On 14.09.2012, at 15:50, Jason Baron wrote:
>>
>>> On Fri, Sep 14, 2012 at 12:29:17AM +0200, Alexander Graf wrote:
>>>> On 13.09.2012, at 22:12, Jason Baron wrote:
>>>>
>>>>> Hi,
>>>>>
>>>>> Qemu bits for q35 support, I'm posting the seabios changes separately. The
>>>>> patches require '-M pc_q35' and -L 'seabios dir with q35 changes' on the
>>>>> qemu command line. Hopefully, we can make it the default for x86 at some future
>>>>> point when we feel comfortable with it.
>>>>
>>>> Without having had a real look at the code in detail yet, how did you design the PCI-ISA bridge (LPC device)? I'm asking mostly because Mac OS X unconditionally accesses that device's PCI config space to find the base address of the HPET.
>>>>
>>>
>>> The LPC device is inherits from TYPE_PCI_DEVICE, and has modeling for
>>> configuring pmbase (where the power management io region resides) and
>>> for configuring pirq irq routing. It does not have the addr for the
>>> HPET. I'll have to check the spec and see where it resides.
>>
>> I have a patch that creates a fake lpc device with the correct regions to make osx happy:
>>
>> http://svn.exactcode.de/t2/trunk/package/emulators/kvm/03-qemu-lpc.patch.disable
>>
>> That might be useful as a starting point :).
>>
>
> cool! I'll pull in the bits I'm missing.
Please make sure to put it at the exact same pci location as it is on real hardware. OSX directly pokes its config space, without searching for it on the bus :).
Alex
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 16/25] pci: Add class 0xc05 as 'SMBus'
2012-09-14 7:04 ` Paolo Bonzini
@ 2012-09-14 14:24 ` Jason Baron
0 siblings, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-14 14:24 UTC (permalink / raw)
To: Paolo Bonzini
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On Fri, Sep 14, 2012 at 09:04:06AM +0200, Paolo Bonzini wrote:
> Il 13/09/2012 22:12, Jason Baron ha scritto:
> > From: Jan Kiszka <jan.kiszka@siemens.com>
> >
> > Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> > Signed-off-by: Jason Baron <jbaron@redhat.com>
> > ---
> > hw/pci.c | 1 +
> > 1 files changed, 1 insertions(+), 0 deletions(-)
> >
> > diff --git a/hw/pci.c b/hw/pci.c
> > index 55e4ad3..3727afa 100644
> > --- a/hw/pci.c
> > +++ b/hw/pci.c
> > @@ -1203,6 +1203,7 @@ static const pci_class_desc pci_class_descriptions[] =
> > { 0x0c02, "SSA controller", "ssa"},
> > { 0x0c03, "USB controller", "usb"},
> > { 0x0c04, "Fibre channel controller", "fibre-channel"},
> > + { 0x0c05, "SMBus"},
> > { 0, NULL}
> > };
> >
> >
>
> You could move here the corresponding hunk of patch 8/25.
>
> Paolo
ok.
Thanks,
-Jason
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 18/25] q35: Fix irr initialization for slots 25..31
2012-09-14 7:05 ` Paolo Bonzini
@ 2012-09-14 14:28 ` Jason Baron
0 siblings, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-14 14:28 UTC (permalink / raw)
To: Paolo Bonzini
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On Fri, Sep 14, 2012 at 09:05:10AM +0200, Paolo Bonzini wrote:
> Il 13/09/2012 22:12, Jason Baron ha scritto:
> > From: Isaku Yamahata <yamahata@valinux.co.jp>
> >
> > This was totally off: The CC registers are 16 bit (stored as little
> > endian), their offsets run in reverse order, and D26IR as well as D25IR
> > have 4 bytes offset to their successors.
> >
> > Reported-by: Jan Kiszka <jan.kiszka@siemens.com>
> > Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> > Signed-off-by: Jason Baron <jbaron@redhat.com>
> > ---
> > hw/q35.c | 29 ++++++++++++++++++++---------
> > 1 files changed, 20 insertions(+), 9 deletions(-)
> >
> > diff --git a/hw/q35.c b/hw/q35.c
> > index 8b6a2e5..295344e 100644
> > --- a/hw/q35.c
> > +++ b/hw/q35.c
> > @@ -474,7 +474,7 @@ static void ich9_lpc_reset(DeviceState *qdev);
> > * Although it's not pci configuration space, it's little endian as Intel.
> > */
> >
> > -static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
> > +static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir)
> > {
> > int intx;
> > for (intx = 0; intx < PCI_NUM_PINS; intx++) {
> > @@ -485,15 +485,26 @@ static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint32_t ir)
> > static void ich9_cc_update(ICH9_LPCState *lpc)
> > {
> > int slot;
> > - int reg_offset;
> > - int intx;
> > + int pci_intx;
> > +
> > + const int reg_offsets[] = {
> > + ICH9_CC_D25IR,
> > + ICH9_CC_D26IR,
> > + ICH9_CC_D27IR,
> > + ICH9_CC_D28IR,
> > + ICH9_CC_D29IR,
> > + ICH9_CC_D30IR,
> > + ICH9_CC_D31IR,
> > + };
> > + const int *offset;
> >
> > /* D{25 - 31}IR, but D30IR is read only to 0. */
> > - for (slot = 25, reg_offset = 0; slot < 32; slot++, reg_offset++) {
> > - if (slot != 30) {
> > - ich9_cc_update_ir(lpc->irr[slot],
> > - lpc->chip_config[ICH9_CC_D31IR + reg_offset]);
> > + for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) {
> > + if (slot == 30) {
> > + continue;
> > }
> > + ich9_cc_update_ir(lpc->irr[slot],
> > + pci_get_word(lpc->chip_config + *offset));
> > }
> >
> > /*
> > @@ -502,8 +513,8 @@ static void ich9_cc_update(ICH9_LPCState *lpc)
> > * are connected to pirq lines. Our choice is PIRQ[E-H].
> > * INT[A-D] are connected to PIRQ[E-H]
> > */
> > - for (intx = 0; intx < PCI_NUM_PINS; intx++) {
> > - lpc->irr[30][intx] = intx + 4;
> > + for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) {
> > + lpc->irr[30][pci_intx] = pci_intx + 4;
> > }
> > }
> >
> >
>
> I guess this patch and patch 12 could/should be squashed in patch 11
> (the one that introduces q35.c)?
>
> Paolo
Michael Tsirkin also suggested combining them. I kept them separate to
make it clear what Yamahata had written, and the re-base I had done. I
agree it would be cleaner to combine. That said, Michael also suggested
not adding the initial one to the build so its still bi-sectable, I
think that could be a reasonable option too.
Thanks,
-Jason
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
` (25 preceding siblings ...)
2012-09-13 22:29 ` [Qemu-devel] [PATCH 00/25] q35 series take #1 Alexander Graf
@ 2012-09-14 15:14 ` Isaku Yamahata
2012-09-14 15:23 ` Jason Baron
2012-09-15 18:02 ` Michael S. Tsirkin
26 siblings, 2 replies; 74+ messages in thread
From: Isaku Yamahata @ 2012-09-14 15:14 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, alex.williamson, mst, jan.kiszka, qemu-devel, agraf,
juzhang, kevin, avi, mkletzan, lcapitulino, afaerber, armbru
On Thu, Sep 13, 2012 at 04:12:34PM -0400, Jason Baron wrote:
> 2) hotplug
> I've added piix acpi style hotplug to ich9.
What's the point of this?
Its design is ad-hoc and shpc/pcie hotplug are available.
--
yamahata
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator
2012-09-14 12:26 ` Michael S. Tsirkin
@ 2012-09-14 15:20 ` Jason Baron
0 siblings, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-14 15:20 UTC (permalink / raw)
To: Michael S. Tsirkin
Cc: aliguori, alex.williamson, jan.kiszka, qemu-devel, agraf,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On Fri, Sep 14, 2012 at 03:26:30PM +0300, Michael S. Tsirkin wrote:
> I think it's best to smash the following patch into this one
> otherwise review becomes painful. Some short notes:
>
ok.
> > ---
> > hw/acpi_ich9.c | 315 ++++++++++++++++++
> > hw/acpi_ich9.h | 53 +++
> > hw/i386/Makefile.objs | 1 +
> > hw/pc_q35.c | 378 +++++++++++++++++++++
> > hw/pci_ids.h | 14 +
> > hw/q35.c | 877 +++++++++++++++++++++++++++++++++++++++++++++++++
> > hw/q35.h | 272 +++++++++++++++
> > hw/q35_smbus.c | 154 +++++++++
> > 8 files changed, 2064 insertions(+), 0 deletions(-)
> > create mode 100644 hw/acpi_ich9.c
> > create mode 100644 hw/acpi_ich9.h
> > create mode 100644 hw/pc_q35.c
> > create mode 100644 hw/q35.c
> > create mode 100644 hw/q35.h
> > create mode 100644 hw/q35_smbus.c
> >
> > diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
> > new file mode 100644
> > index 0000000..59c0807
> > --- /dev/null
> > +++ b/hw/acpi_ich9.c
> > @@ -0,0 +1,315 @@
> > +/*
> > + * ACPI implementation
> > + *
> > + * Copyright (c) 2006 Fabrice Bellard
> > + *
> > + * This library is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU Lesser General Public
> > + * License version 2 as published by the Free Software Foundation.
> > + *
> > + * This library is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + * Lesser General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU Lesser General Public
> > + * License along with this library; if not, see <http://www.gnu.org/licenses/>
> > + */
> > +/*
> > + * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> > + * VA Linux Systems Japan K.K.
> > + *
>
> Probably two headers should be combined.
>
> > + * This is based on acpi.c.
>
> This should probably go into commit log instead.
>
> > + */
>
ok.
>
> ..
>
> > diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h
> > new file mode 100644
> > index 0000000..f55c0e9
> > --- /dev/null
> > +++ b/hw/acpi_ich9.h
> > @@ -0,0 +1,53 @@
> > +/*
> > + * QEMU GMCH/ICH9 LPC PM Emulation
> > + *
> > + * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> > + * VA Linux Systems Japan K.K.
> > + *
> > + * This library is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU Lesser General Public
> > + * License as published by the Free Software Foundation; either
> > + * version 2 of the License, or (at your option) any later version.
> > + *
> > + * This library is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> > + * Lesser General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU Lesser General Public
> > + * License along with this library; if not, see <http://www.gnu.org/licenses/>
> > + */
> > +
> > +#ifndef HW_ACPI_ICH9_H
> > +#define HW_ACPI_ICH9_H
> > +
> > +#include "acpi.h"
> > +
> > +typedef struct ICH9_LPCPmRegs {
>
> This naming scheme conflicts with qemu coding style.
> Pls use Ich9LpcPmRegs or something.
> Same comment applies everywhere.
>
Ok, I'll also have to fix up some of the data structure naming in q35.h.
Thanks,
-Jason
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
2012-09-14 15:14 ` Isaku Yamahata
@ 2012-09-14 15:23 ` Jason Baron
2012-09-14 17:34 ` Isaku Yamahata
2012-09-15 18:02 ` Michael S. Tsirkin
1 sibling, 1 reply; 74+ messages in thread
From: Jason Baron @ 2012-09-14 15:23 UTC (permalink / raw)
To: Isaku Yamahata
Cc: aliguori, alex.williamson, mst, jan.kiszka, qemu-devel, agraf,
juzhang, kevin, avi, mkletzan, lcapitulino, afaerber, armbru
On Sat, Sep 15, 2012 at 12:14:01AM +0900, Isaku Yamahata wrote:
> On Thu, Sep 13, 2012 at 04:12:34PM -0400, Jason Baron wrote:
> > 2) hotplug
> > I've added piix acpi style hotplug to ich9.
>
> What's the point of this?
> Its design is ad-hoc and shpc/pcie hotplug are available.
The point was to get to feature parity with piix. I'm not sure how hard
pcie hotplug is to implement really. I was thinking that we could
replace the piix hotplug style with pcie hotplug, once that was
implemented...
thanks,
-Jason
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
2012-09-14 14:12 ` Alexander Graf
@ 2012-09-14 15:37 ` Kevin Wolf
0 siblings, 0 replies; 74+ messages in thread
From: Kevin Wolf @ 2012-09-14 15:37 UTC (permalink / raw)
To: Alexander Graf
Cc: aliguori, alex.williamson, mst, jan.kiszka, Jason Baron,
qemu-devel, armbru, yamahata, juzhang, kevin, avi, mkletzan,
lcapitulino, afaerber
Am 14.09.2012 16:12, schrieb Alexander Graf:
>
> On 14.09.2012, at 16:08, Jason Baron wrote:
>
>> On Fri, Sep 14, 2012 at 03:56:17PM +0200, Alexander Graf wrote:
>>> On 14.09.2012, at 15:50, Jason Baron wrote:
>>>
>>>> On Fri, Sep 14, 2012 at 12:29:17AM +0200, Alexander Graf wrote:
>>>>> On 13.09.2012, at 22:12, Jason Baron wrote:
>>>>>
>>>>>> Hi,
>>>>>>
>>>>>> Qemu bits for q35 support, I'm posting the seabios changes separately. The
>>>>>> patches require '-M pc_q35' and -L 'seabios dir with q35 changes' on the
>>>>>> qemu command line. Hopefully, we can make it the default for x86 at some future
>>>>>> point when we feel comfortable with it.
>>>>>
>>>>> Without having had a real look at the code in detail yet, how did you design the PCI-ISA bridge (LPC device)? I'm asking mostly because Mac OS X unconditionally accesses that device's PCI config space to find the base address of the HPET.
>>>>>
>>>>
>>>> The LPC device is inherits from TYPE_PCI_DEVICE, and has modeling for
>>>> configuring pmbase (where the power management io region resides) and
>>>> for configuring pirq irq routing. It does not have the addr for the
>>>> HPET. I'll have to check the spec and see where it resides.
>>>
>>> I have a patch that creates a fake lpc device with the correct regions to make osx happy:
>>>
>>> http://svn.exactcode.de/t2/trunk/package/emulators/kvm/03-qemu-lpc.patch.disable
>>>
>>> That might be useful as a starting point :).
>>>
>>
>> cool! I'll pull in the bits I'm missing.
>
> Please make sure to put it at the exact same pci location as it is on real hardware. OSX directly pokes its config space, without searching for it on the bus :).
Sounds like writing a qtest case that checks this would be a good idea
if you want to keep this working long term. Not many people test OS X
guests.
Kevin
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 02/25] pci: add opaque argument to pci_map_irq_fn
2012-09-13 20:12 ` [Qemu-devel] [PATCH 02/25] pci: add opaque argument to pci_map_irq_fn Jason Baron
@ 2012-09-14 16:32 ` Alex Williamson
0 siblings, 0 replies; 74+ messages in thread
From: Alex Williamson @ 2012-09-14 16:32 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, mst, jan.kiszka, qemu-devel, agraf, yamahata, juzhang,
kevin, avi, mkletzan, lcapitulino, afaerber, armbru
On Thu, 2012-09-13 at 16:12 -0400, Jason Baron wrote:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> Pass opaque argument to pci_map_irq_fn like pci_set_irq_fn.
> ICH9 irq routing is not static, but configurable by chipset configuration
> registers, so the corresponding irq mapping function of pci_map_irq_fn
> needs to know the pointer to ich9.
>
> [jbaron@redhat.com: minor tweaks]
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/apb_pci.c | 4 ++--
> hw/bonito.c | 2 +-
> hw/dec_pci.c | 2 +-
> hw/grackle_pci.c | 2 +-
> hw/gt64xxx.c | 2 +-
> hw/pci.c | 4 ++--
> hw/pci.h | 2 +-
> hw/pci_bridge_dev.c | 2 +-
> hw/piix_pci.c | 2 +-
> hw/ppc4xx_pci.c | 2 +-
> hw/ppce500_pci.c | 2 +-
> hw/prep_pci.c | 2 +-
> hw/sh_pci.c | 2 +-
> hw/unin_pci.c | 2 +-
> hw/versatile_pci.c | 2 +-
> hw/xen.h | 2 +-
> xen-all.c | 2 +-
> xen-stub.c | 2 +-
> 18 files changed, 20 insertions(+), 20 deletions(-)
Missed alpha here
diff --git a/hw/alpha_dp264.c b/hw/alpha_dp264.c
index 9eb939f..71b0790 100644
--- a/hw/alpha_dp264.c
+++ b/hw/alpha_dp264.c
@@ -33,7 +33,7 @@ static uint64_t cpu_alpha_superpage_to_phys(void *opaque, uint
(3) The interrupt number assigned by the kernel.
The following function is concerned with (1) only. */
-static int clipper_pci_map_irq(PCIDevice *d, int irq_num)
+static int clipper_pci_map_irq(void *opaque, PCIDevice *d, int irq_num)
{
int slot = d->devfn >> 3;
^ permalink raw reply related [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
2012-09-14 15:23 ` Jason Baron
@ 2012-09-14 17:34 ` Isaku Yamahata
2012-09-14 19:01 ` Jason Baron
0 siblings, 1 reply; 74+ messages in thread
From: Isaku Yamahata @ 2012-09-14 17:34 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, alex.williamson, mst, jan.kiszka, qemu-devel, agraf,
juzhang, kevin, avi, mkletzan, lcapitulino, afaerber, armbru
On Fri, Sep 14, 2012 at 11:23:29AM -0400, Jason Baron wrote:
> On Sat, Sep 15, 2012 at 12:14:01AM +0900, Isaku Yamahata wrote:
> > On Thu, Sep 13, 2012 at 04:12:34PM -0400, Jason Baron wrote:
> > > 2) hotplug
> > > I've added piix acpi style hotplug to ich9.
> >
> > What's the point of this?
> > Its design is ad-hoc and shpc/pcie hotplug are available.
>
> The point was to get to feature parity with piix. I'm not sure how hard
> pcie hotplug is to implement really. I was thinking that we could
> replace the piix hotplug style with pcie hotplug, once that was
> implemented...
shpc/pcie hotplug emulators are already available in qemu.
hw/shpc.c, hw/pcie.c and hw/xio3130_downstream.c.
thanks,
--
yamahata
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 07/25] pc/piix_pci: factor out smram/pam logic
2012-09-13 20:12 ` [Qemu-devel] [PATCH 07/25] pc/piix_pci: factor out smram/pam logic Jason Baron
@ 2012-09-14 18:52 ` Blue Swirl
0 siblings, 0 replies; 74+ messages in thread
From: Blue Swirl @ 2012-09-14 18:52 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On Thu, Sep 13, 2012 at 8:12 PM, Jason Baron <jbaron@redhat.com> wrote:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> Factor out smram/pam logic for later use.
> Which will be used by q35 too.
>
> [jbaron@redhat.com: changes for updated memory API]
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/i386/Makefile.objs | 1 +
> hw/pam.c | 121 +++++++++++++++++++++++++++++++++++++++++++++++++
> hw/pam.h | 98 +++++++++++++++++++++++++++++++++++++++
> hw/piix_pci.c | 65 ++++----------------------
> 4 files changed, 230 insertions(+), 55 deletions(-)
> create mode 100644 hw/pam.c
> create mode 100644 hw/pam.h
>
> diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs
> index 8c764bb..2f0c172 100644
> --- a/hw/i386/Makefile.objs
> +++ b/hw/i386/Makefile.objs
> @@ -6,6 +6,7 @@ obj-y += pci-hotplug.o smbios.o wdt_ib700.o
> obj-y += debugcon.o multiboot.o
> obj-y += pc_piix.o
> obj-y += pc_sysfw.o
> +obj-y += pam.o
> obj-$(CONFIG_XEN) += xen_platform.o xen_apic.o
> obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen-host-pci-device.o
> obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
> diff --git a/hw/pam.c b/hw/pam.c
> new file mode 100644
> index 0000000..11afeb3
> --- /dev/null
> +++ b/hw/pam.c
> @@ -0,0 +1,121 @@
> +/*
> + * QEMU i440FX/PIIX3 PCI Bridge Emulation
> + *
> + * Copyright (c) 2006 Fabrice Bellard
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + *
> + * Split out from piix_pci.c
> + * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + * Copyright (c) 2012 Jason Baron <jbaron@redhat.com>
> + *
> + */
> +
> +#include "sysemu.h"
> +#include "pam.h"
> +
> +void smram_update(MemoryRegion *smram_region, uint8_t smram,
> + uint8_t smm_enabled)
> +{
> + bool smram_enabled;
> +
> + smram_enabled = ((smm_enabled && (smram & SMRAM_G_SMRAME)) ||
> + (smram & SMRAM_D_OPEN));
> + memory_region_set_enabled(smram_region, !smram_enabled);
> +}
> +
> +void smram_set_smm(uint8_t *host_smm_enabled, int smm, uint8_t smram,
> + MemoryRegion *smram_region)
> +{
> + uint8_t smm_enabled = (smm != 0);
> + if (*host_smm_enabled != smm_enabled) {
> + *host_smm_enabled = smm_enabled;
> + smram_update(smram_region, smram, *host_smm_enabled);
> + }
> +}
> +
> +static void pam_update_seg(PAMMemoryRegion *mem, uint32_t start, uint32_t size,
> + MemoryRegion *ram_memory,
> + MemoryRegion *pci_address_space,
> + MemoryRegion *system_memory, uint8_t attr)
> +{
> + if (mem->initialized) {
> + memory_region_del_subregion(system_memory, &mem->mem);
> + memory_region_destroy(&mem->mem);
> + }
> +
> + // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
Please delete or convert to C89 comment style.
> + switch (attr) {
> + case PAM_ATTR_WE | PAM_ATTR_RE:
> + /* RAM */
> + memory_region_init_alias(&mem->mem, "pam-ram", ram_memory,
> + start, size);
> + break;
> + case PAM_ATTR_RE:
> + /* ROM (XXX: not quite correct) */
> + memory_region_init_alias(&mem->mem, "pam-rom", ram_memory,
> + start, size);
> + memory_region_set_readonly(&mem->mem, true);
> + break;
> + case PAM_ATTR_WE:
> + case 0:
> + /* XXX: should distinguish read/write cases */
> + memory_region_init_alias(&mem->mem, "pam-pci", pci_address_space,
> + start, size);
> + break;
> + default:
> + abort();
> + break;
> + }
> + memory_region_add_subregion_overlap(system_memory, start, &mem->mem, 1);
> + mem->initialized = true;
> +
> +}
> +
> +static uint8_t pam_attr(uint8_t val, int hi)
> +{
> + return (val >> ((!!hi) * 4)) & PAM_ATTR_MASK;
> +}
> +
> +void pam_update(PAMMemoryRegion *mem, int idx, uint8_t val,
> + MemoryRegion *ram_memory, MemoryRegion *pci_address_space,
> + MemoryRegion *system_memory)
> +{
> + uint32_t phys_addr;
> + int map_idx;
> +
> + assert(0 <= idx && idx <= PAM_IDX_MAX);
> +
> + if (idx == 0) {
> + pam_update_seg(&mem[0], PAM_BIOS_BASE, PAM_BIOS_SIZE, ram_memory,
> + pci_address_space, system_memory, pam_attr(val, 1));
> + return;
> + }
> +
> + map_idx = (idx - 1) * 2;
> +
> + phys_addr = PAM_EXPAN_BASE + PAM_EXPAN_SIZE * map_idx;
> + pam_update_seg(&mem[map_idx + 1], phys_addr, PAM_EXPAN_SIZE, ram_memory,
> + pci_address_space, system_memory, pam_attr(val, 0));
> +
> + phys_addr += PAM_EXPAN_SIZE;
> + pam_update_seg(&mem[map_idx + 2], phys_addr, PAM_EXPAN_SIZE, ram_memory,
> + pci_address_space, system_memory, pam_attr(val, 1));
> +}
> diff --git a/hw/pam.h b/hw/pam.h
> new file mode 100644
> index 0000000..ce89a2a
> --- /dev/null
> +++ b/hw/pam.h
> @@ -0,0 +1,98 @@
> +#ifndef QEMU_PAM_H
> +#define QEMU_PAM_H
> +
> +/*
> + * Copyright (c) 2006 Fabrice Bellard
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +/*
> + * Split out from piix_pci.c
> + * Copyright (c) 2011 Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + * Copyright (c) 2012 Jason Baron <jbaron@redhat.com>
> + *
> + * SMRAM memory area and PAM memory area in Legacy address range for PC.
> + * PAM: Programmable Attribute Map registers
> + *
> + * 0xa0000 - 0xbffff compatible SMRAM
> + *
> + * 0xc0000 - 0xc3fff Expansion area memory segments
> + * 0xc4000 - 0xc7fff
> + * 0xc8000 - 0xcbfff
> + * 0xcc000 - 0xcffff
> + * 0xd0000 - 0xd7fff
> + * 0xd8000 - 0xdbfff
> + * 0xdc000 - 0xdffff
> + * 0xe0000 - 0xe3fff Extended System BIOS Area Memory Segments
> + * 0xe4000 - 0xe7fff
> + * 0xe8000 - 0xebfff
> + * 0xec000 - 0xeffff
> + *
> + * 0xf0000 - 0xfffff System BIOS Area Memory Segments
> + */
> +
> +#include "qemu-common.h"
> +#include "memory.h"
> +
> +#define SMRAM_C_BASE 0xa0000
> +#define SMRAM_C_END 0xc0000
> +#define SMRAM_C_SIZE 0x20000
> +
> +
> +#define PAM_EXPAN_BASE 0xc0000
> +#define PAM_EXPAN_SIZE 0x04000
> +
> +#define PAM_EXBIOS_BASE 0xe0000
> +#define PAM_EXBIOS_SIZE 0x04000
> +
> +#define PAM_BIOS_BASE 0xf0000
> +#define PAM_BIOS_END 0xfffff
> +/* 64KB: Intel 3 series express chipset family p. 58*/
> +#define PAM_BIOS_SIZE 0x10000
> +
> +/* PAM registers: log nibble and high nibble*/
> +#define PAM_ATTR_WE ((uint8_t)2)
> +#define PAM_ATTR_RE ((uint8_t)1)
> +#define PAM_ATTR_MASK ((uint8_t)3)
> +
> +#define PAM_IDX_MAX 6 /* pam0 - pam6 */
> +
> +/* SMRAM register */
> +#define SMRAM_D_OPEN ((uint8_t)(1 << 6))
> +#define SMRAM_D_CLS ((uint8_t)(1 << 5))
> +#define SMRAM_D_LCK ((uint8_t)(1 << 4))
> +#define SMRAM_G_SMRAME ((uint8_t)(1 << 3))
> +#define SMRAM_C_BASE_SEG_MASK ((uint8_t)0x7)
> +#define SMRAM_C_BASE_SEG ((uint8_t)0x2) /* hardwired to b010 */
> +
> +typedef struct PAMMemoryRegion {
> + MemoryRegion mem;
> + bool initialized;
> +} PAMMemoryRegion;
> +
> +void smram_update(MemoryRegion *smram_region, uint8_t smram,
> + uint8_t smm_enabled);
> +void smram_set_smm(uint8_t *host_smm_enabled, int smm, uint8_t smram,
> + MemoryRegion *smram_region);
> +void pam_update(PAMMemoryRegion *mem, int idx, uint8_t val,
> + MemoryRegion *ram_memory, MemoryRegion *pci_address_space,
> + MemoryRegion *system_memory);
> +
> +#endif /* QEMU_PAM_H */
> diff --git a/hw/piix_pci.c b/hw/piix_pci.c
> index 376a287..4861cf6 100644
> --- a/hw/piix_pci.c
> +++ b/hw/piix_pci.c
> @@ -30,6 +30,7 @@
> #include "sysbus.h"
> #include "range.h"
> #include "xen.h"
> +#include "pam.h"
>
> /*
> * I440FX chipset data sheet.
> @@ -68,11 +69,6 @@ typedef struct PIIX3State {
> int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
> } PIIX3State;
>
> -typedef struct PAMMemoryRegion {
> - MemoryRegion mem;
> - bool initialized;
> -} PAMMemoryRegion;
> -
> struct PCII440FXState {
> PCIDevice dev;
> MemoryRegion *system_memory;
> @@ -105,56 +101,16 @@ static int pci_slot_get_pirq(void *opaque, PCIDevice *pci_dev, int pci_intx)
> return (pci_intx + slot_addend) & 3;
> }
>
> -static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r,
> - PAMMemoryRegion *mem)
> -{
> - if (mem->initialized) {
> - memory_region_del_subregion(d->system_memory, &mem->mem);
> - memory_region_destroy(&mem->mem);
> - }
> -
> - // printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
> - switch(r) {
> - case 3:
> - /* RAM */
> - memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory,
> - start, end - start);
> - break;
> - case 1:
> - /* ROM (XXX: not quite correct) */
> - memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory,
> - start, end - start);
> - memory_region_set_readonly(&mem->mem, true);
> - break;
> - case 2:
> - case 0:
> - /* XXX: should distinguish read/write cases */
> - memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space,
> - start, end - start);
> - break;
> - }
> - memory_region_add_subregion_overlap(d->system_memory,
> - start, &mem->mem, 1);
> - mem->initialized = true;
> -}
> -
> static void i440fx_update_memory_mappings(PCII440FXState *d)
> {
> - int i, r;
> - uint32_t smram;
> - bool smram_enabled;
> + int i;
>
> memory_region_transaction_begin();
> - update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
> - &d->pam_regions[0]);
> - for(i = 0; i < 12; i++) {
> - r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3;
> - update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r,
> - &d->pam_regions[i+1]);
> + for (i = 0; i <= PAM_IDX_MAX; i++) {
> + pam_update(&d->pam_regions[0], i, d->dev.config[I440FX_PAM + i],
> + d->ram_memory, d->pci_address_space, d->system_memory);
> }
> - smram = d->dev.config[I440FX_SMRAM];
> - smram_enabled = (d->smm_enabled && (smram & 0x08)) || (smram & 0x40);
> - memory_region_set_enabled(&d->smram_region, !smram_enabled);
> + smram_update(&d->smram_region, d->dev.config[I440FX_SMRAM], d->smm_enabled);
> memory_region_transaction_commit();
> }
>
> @@ -162,11 +118,10 @@ static void i440fx_set_smm(int val, void *arg)
> {
> PCII440FXState *d = arg;
>
> - val = (val != 0);
> - if (d->smm_enabled != val) {
> - d->smm_enabled = val;
> - i440fx_update_memory_mappings(d);
> - }
> + memory_region_transaction_begin();
> + smram_set_smm(&d->smm_enabled, val, d->dev.config[I440FX_SMRAM],
> + &d->smram_region);
> + memory_region_transaction_commit();
> }
>
>
> --
> 1.7.1
>
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 23/25] q35: add acpi-based pci hotplug.
2012-09-13 20:12 ` [Qemu-devel] [PATCH 23/25] q35: add acpi-based pci hotplug Jason Baron
@ 2012-09-14 18:56 ` Blue Swirl
0 siblings, 0 replies; 74+ messages in thread
From: Blue Swirl @ 2012-09-14 18:56 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On Thu, Sep 13, 2012 at 8:12 PM, Jason Baron <jbaron@redhat.com> wrote:
> Add piix style acpi hotplug to q35.
>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/acpi_ich9.c | 173 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-
> hw/acpi_ich9.h | 10 +++
> 2 files changed, 182 insertions(+), 1 deletions(-)
>
> diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
> index 570ce0c..ba463a0 100644
> --- a/hw/acpi_ich9.c
> +++ b/hw/acpi_ich9.c
> @@ -41,6 +41,13 @@ do { printf("%s "fmt, __func__, ## __VA_ARGS__); } while (0)
> #define ICH9_DEBUG(fmt, ...) do { } while (0)
> #endif
>
> +#define PCI_UP_BASE 0xae00
> +#define PCI_DOWN_BASE 0xae04
> +#define PCI_EJ_BASE 0xae08
> +#define PCI_RMV_BASE 0xae0c
> +#define ICH9_PCI_HOTPLUG_STATUS 2
> +
> +
> static void pm_ioport_write_fallback(void *opaque, uint32_t addr, int len,
> uint32_t val);
> static uint32_t pm_ioport_read_fallback(void *opaque, uint32_t addr, int len);
> @@ -55,7 +62,10 @@ static void pm_update_sci(ICH9_LPCPmRegs *pm)
> (ACPI_BITMASK_RT_CLOCK_ENABLE |
> ACPI_BITMASK_POWER_BUTTON_ENABLE |
> ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
> - ACPI_BITMASK_TIMER_ENABLE)) != 0);
> + ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
> + (((pm->acpi_regs.gpe.sts[0] & pm->acpi_regs.gpe.en[0])
> + & ICH9_PCI_HOTPLUG_STATUS) != 0);
> +
> qemu_set_irq(pm->irq, sci_level);
>
> /* schedule a timer interruption if needed */
> @@ -77,6 +87,7 @@ static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
> switch (addr & ICH9_PMIO_MASK) {
> case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
> acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
> + pm_update_sci(pm);
> break;
> default:
> break;
> @@ -283,6 +294,65 @@ const VMStateDescription vmstate_ich9_pm = {
> }
> };
>
> +static void acpi_ich9_eject_slot(ICH9_LPCPmRegs *opaque, unsigned slots)
> +{
> + BusChild *kid, *next;
> + ICH9_LPCPmRegs *pm = opaque;
> + ICH9_LPCState *lpc = container_of(pm, ICH9_LPCState, pm);
> + PCIDevice *s = PCI_DEVICE(lpc);
> + BusState *bus = qdev_get_parent_bus(&s->qdev);
> + int slot = ffs(slots) - 1;
> + bool slot_free = true;
> +
> + /* Mark request as complete */
> + pm->pci0_status.down &= ~(1U << slot);
> +
> + QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
> + DeviceState *qdev = kid->child;
> + PCIDevice *dev = PCI_DEVICE(qdev);
> + PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
> + if (PCI_SLOT(dev->devfn) == slot) {
> + if (pc->no_hotplug) {
> + slot_free = false;
> + } else {
> + qdev_free(qdev);
> + }
> + }
> + }
> + if (slot_free) {
> + pm->pci0_slot_device_present &= ~(1U << slot);
> + }
> +}
> +
> +static void acpi_ich9_update_hotplug(ICH9_LPCPmRegs *pm)
> +{
> + ICH9_LPCState *lpc = container_of(pm, ICH9_LPCState, pm);
> + PCIDevice *dev = PCI_DEVICE(lpc);
> + BusState *bus = qdev_get_parent_bus(&dev->qdev);
> + BusChild *kid, *next;
> +
> + /* Execute any pending removes during reset */
> + while (pm->pci0_status.down) {
> + acpi_ich9_eject_slot(pm, pm->pci0_status.down);
> + }
> +
> + pm->pci0_hotplug_enable = ~0;
> + pm->pci0_slot_device_present = 0;
> +
> + QTAILQ_FOREACH_SAFE(kid, &bus->children, sibling, next) {
> + DeviceState *qdev = kid->child;
> + PCIDevice *pdev = PCI_DEVICE(qdev);
> + PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pdev);
> + int slot = PCI_SLOT(pdev->devfn);
> +
> + if (pc->no_hotplug) {
> + pm->pci0_hotplug_enable &= ~(1U << slot);
> + }
> +
> + pm->pci0_slot_device_present |= (1U << slot);
> + }
> +}
> +
> static void pm_reset(void *opaque)
> {
> ICH9_LPCPmRegs *pm = opaque;
> @@ -300,6 +370,7 @@ static void pm_reset(void *opaque)
> }
>
> pm_update_sci(pm);
> + acpi_ich9_update_hotplug(pm);
> }
>
> static void pm_powerdown(void *opaque, int irq, int power_failing)
> @@ -309,6 +380,104 @@ static void pm_powerdown(void *opaque, int irq, int power_failing)
> acpi_pm1_evt_power_down(&pm->acpi_regs);
> }
>
> +static uint32_t pci_up_read(void *opaque, uint32_t addr)
> +{
> + ICH9_LPCPmRegs *pm = opaque;
> + uint32_t val;
> +
> + /* Manufacture an "up" value to cause a device check on any hotplug
> + * slot with a device. Extra device checks are harmless. */
> + val = pm->pci0_slot_device_present & pm->pci0_hotplug_enable;
> +
> + ICH9_DEBUG("pci_up_read %x\n", val);
> + return val;
> +}
> +
> +static uint32_t pci_down_read(void *opaque, uint32_t addr)
> +{
> + ICH9_LPCPmRegs *pm = opaque;
> + uint32_t val = pm->pci0_status.down;
> +
> + ICH9_DEBUG("pci_down_read %x\n", val);
> + return val;
> +}
> +
> +static uint32_t pci_features_read(void *opaque, uint32_t addr)
> +{
> + /* No feature defined yet */
> + ICH9_DEBUG("pci_features_read %x\n", 0);
> + return 0;
> +}
> +
> +static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
> +{
> + acpi_ich9_eject_slot(opaque, val);
> +
> + ICH9_DEBUG("pciej write %x <== %d\n", addr, val);
> +}
> +
> +static uint32_t pcirmv_read(void *opaque, uint32_t addr)
> +{
> + ICH9_LPCPmRegs *pm = opaque;
> +
> + return pm->pci0_hotplug_enable;
> +}
> +
> +static void enable_device(ICH9_LPCPmRegs *pm, int slot)
> +{
> + pm->acpi_regs.gpe.sts[0] |= ICH9_PCI_HOTPLUG_STATUS;
> + pm->pci0_slot_device_present |= (1U << slot);
> +}
> +
> +static void disable_device(ICH9_LPCPmRegs *pm, int slot)
> +{
> + pm->acpi_regs.gpe.sts[0] |= ICH9_PCI_HOTPLUG_STATUS;
> + pm->pci0_status.down |= (1U << slot);
> +}
> +
> +static int ich9_device_hotplug(DeviceState *qdev, PCIDevice *dev,
> + PCIHotplugState state)
> +{
> + int slot = PCI_SLOT(dev->devfn);
> + ICH9_LPCState *lpc = DO_UPCAST(ICH9_LPCState, d,
> + PCI_DEVICE(qdev));
> + ICH9_LPCPmRegs *pm = &lpc->pm;
> +
> + /* Don't send event when device is enabled during qemu machine creation:
> + * it is present on boot, no hotplug event is necessary. We do send an
> + * event when the device is disabled later. */
> + if (state == PCI_COLDPLUG_ENABLED) {
> + pm->pci0_slot_device_present |= (1U << slot);
> + return 0;
> + }
> +
> + if (state == PCI_HOTPLUG_ENABLED) {
> + enable_device(pm, slot);
> + } else {
> + disable_device(pm, slot);
> + }
> +
> + pm_update_sci(pm);
> +
> + return 0;
> +}
> +
> +static void ich9_acpi_system_hot_add_init(ICH9_LPCPmRegs *s)
> +{
> + ICH9_LPCState *lpc = container_of(s, ICH9_LPCState, pm);
> + PCIDevice *pdev = PCI_DEVICE(lpc);
> +
> + register_ioport_read(PCI_UP_BASE, 4, 4, pci_up_read, s);
Please convert these to MemoryRegionPortio.
> + register_ioport_read(PCI_DOWN_BASE, 4, 4, pci_down_read, s);
> +
> + register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, s);
> + register_ioport_read(PCI_EJ_BASE, 4, 4, pci_features_read, s);
> +
> + register_ioport_read(PCI_RMV_BASE, 4, 4, pcirmv_read, s);
> +
> + pci_bus_hotplug(pdev->bus, ich9_device_hotplug, &pdev->qdev);
> +}
> +
> void ich9_pm_init(ICH9_LPCPmRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
> {
> acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn);
> @@ -318,4 +487,6 @@ void ich9_pm_init(ICH9_LPCPmRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
> pm->irq = sci_irq;
> qemu_register_reset(pm_reset, pm);
> qemu_system_powerdown = *qemu_allocate_irqs(pm_powerdown, pm, 1);
> +
> + ich9_acpi_system_hot_add_init(pm);
> }
> diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h
> index 9ff4c42..434e221 100644
> --- a/hw/acpi_ich9.h
> +++ b/hw/acpi_ich9.h
> @@ -23,6 +23,11 @@
>
> #include "acpi.h"
>
> +struct pci_status {
PCIStatus, typedef missing
> + uint32_t up; /* deprecated, maintained for migration compatibility */
> + uint32_t down;
> +};
> +
> typedef struct ICH9_LPCPmRegs {
> /*
> * In ich9 spec says that pm1_cnt register is 32bit width and
> @@ -36,6 +41,11 @@ typedef struct ICH9_LPCPmRegs {
> qemu_irq irq; /* SCI */
>
> uint32_t pm_io_base;
> +
> + /* for pci hotplug */
> + struct pci_status pci0_status;
> + uint32_t pci0_hotplug_enable;
> + uint32_t pci0_slot_device_present;
> } ICH9_LPCPmRegs;
>
> void ich9_pm_init(ICH9_LPCPmRegs *pm,
> --
> 1.7.1
>
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
2012-09-14 17:34 ` Isaku Yamahata
@ 2012-09-14 19:01 ` Jason Baron
2012-09-15 0:24 ` Isaku Yamahata
2012-09-15 17:40 ` Michael S. Tsirkin
0 siblings, 2 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-14 19:01 UTC (permalink / raw)
To: Isaku Yamahata
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On Sat, Sep 15, 2012 at 02:34:18AM +0900, Isaku Yamahata wrote:
> On Fri, Sep 14, 2012 at 11:23:29AM -0400, Jason Baron wrote:
> > On Sat, Sep 15, 2012 at 12:14:01AM +0900, Isaku Yamahata wrote:
> > > On Thu, Sep 13, 2012 at 04:12:34PM -0400, Jason Baron wrote:
> > > > 2) hotplug
> > > > I've added piix acpi style hotplug to ich9.
> > >
> > > What's the point of this?
> > > Its design is ad-hoc and shpc/pcie hotplug are available.
> >
> > The point was to get to feature parity with piix. I'm not sure how hard
> > pcie hotplug is to implement really. I was thinking that we could
> > replace the piix hotplug style with pcie hotplug, once that was
> > implemented...
>
> shpc/pcie hotplug emulators are already available in qemu.
> hw/shpc.c, hw/pcie.c and hw/xio3130_downstream.c.
>
> thanks,
> --
> yamahata
>
ok, yes pcie hotplug seems to work :) I guess I got confused b/c I
thought devices would show up on the host bus. So the host bus in q35
simply doesn't support hotplug?
Also, the way I'm doing hotplug is by specifying a 'bus=pcie.n' param.
Without the 'bus=pcie.n' param, i get:
Bus 'pcie.0' does not support hotplugging
We probably then need to enhance 'device_add' to find a reasonable
default bus for the device on hotplug?
Thanks,
-Jason
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 12/25] q35: Re-base q35 to 1.2
2012-09-13 20:12 ` [Qemu-devel] [PATCH 12/25] q35: Re-base q35 to 1.2 Jason Baron
@ 2012-09-14 19:07 ` Blue Swirl
0 siblings, 0 replies; 74+ messages in thread
From: Blue Swirl @ 2012-09-14 19:07 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On Thu, Sep 13, 2012 at 8:12 PM, Jason Baron <jbaron@redhat.com> wrote:
> Rebase q35 to 1.2 - memory api updates, acpi updates, qom...
>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/acpi_ich9.c | 65 ++++----
> hw/acpi_ich9.h | 9 +-
> hw/pc.h | 2 +
> hw/pc_piix.c | 4 +-
> hw/pc_q35.c | 189 +++++++++++++++-------
> hw/q35.c | 477 +++++++++++++++++++++++++++++++-------------------------
> hw/q35.h | 97 +++++++++++-
> hw/q35_smbus.c | 78 +++++----
> 8 files changed, 568 insertions(+), 353 deletions(-)
>
> diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
> index 59c0807..0d66109 100644
> --- a/hw/acpi_ich9.c
> +++ b/hw/acpi_ich9.c
> @@ -18,6 +18,7 @@
> /*
> * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> * VA Linux Systems Japan K.K.
> + * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> *
> * This is based on acpi.c.
> */
> @@ -47,9 +48,9 @@ static void pm_update_sci(ICH9_LPCPmRegs *pm)
> {
> int sci_level, pm1a_sts;
>
> - pm1a_sts = acpi_pm1_evt_get_sts(&pm->pm1a, pm->tmr.overflow_time);
> + pm1a_sts = acpi_pm1_evt_get_sts(&pm->acpi_regs);
>
> - sci_level = (((pm1a_sts & pm->pm1a.en) &
> + sci_level = (((pm1a_sts & pm->acpi_regs.pm1.evt.en) &
> (ACPI_BITMASK_RT_CLOCK_ENABLE |
> ACPI_BITMASK_POWER_BUTTON_ENABLE |
> ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
> @@ -57,14 +58,14 @@ static void pm_update_sci(ICH9_LPCPmRegs *pm)
> qemu_set_irq(pm->irq, sci_level);
>
> /* schedule a timer interruption if needed */
> - acpi_pm_tmr_update(&pm->tmr,
> - (pm->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
> + acpi_pm_tmr_update(&pm->acpi_regs,
> + (pm->acpi_regs.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
> !(pm1a_sts & ACPI_BITMASK_TIMER_STATUS));
> }
>
> -static void ich9_pm_update_sci_fn(ACPIPMTimer *tmr)
> +static void ich9_pm_update_sci_fn(ACPIREGS *regs)
> {
> - ICH9_LPCPmRegs *pm = container_of(tmr, ICH9_LPCPmRegs, tmr);
> + ICH9_LPCPmRegs *pm = container_of(regs, ICH9_LPCPmRegs, acpi_regs);
> pm_update_sci(pm);
> }
>
> @@ -74,7 +75,7 @@ static void pm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
>
> switch (addr & ICH9_PMIO_MASK) {
> case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
> - acpi_gpe_ioport_writeb(&pm->gpe0, addr, val);
> + acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
> break;
> default:
> break;
> @@ -90,7 +91,7 @@ static uint32_t pm_ioport_readb(void *opaque, uint32_t addr)
>
> switch (addr & ICH9_PMIO_MASK) {
> case ICH9_PMIO_GPE0_STS ... (ICH9_PMIO_GPE0_STS + ICH9_PMIO_GPE0_LEN - 1):
> - val = acpi_gpe_ioport_readb(&pm->gpe0, addr);
> + val = acpi_gpe_ioport_readb(&pm->acpi_regs, addr);
> break;
> default:
> val = 0;
> @@ -106,15 +107,15 @@ static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
>
> switch (addr & ICH9_PMIO_MASK) {
> case ICH9_PMIO_PM1_STS:
> - acpi_pm1_evt_write_sts(&pm->pm1a, &pm->tmr, val);
> + acpi_pm1_evt_write_sts(&pm->acpi_regs, val);
> pm_update_sci(pm);
> break;
> case ICH9_PMIO_PM1_EN:
> - pm->pm1a.en = val;
> + pm->acpi_regs.pm1.evt.en = val;
> pm_update_sci(pm);
> break;
> case ICH9_PMIO_PM1_CNT:
> - acpi_pm1_cnt_write(&pm->pm1a, &pm->pm1_cnt, val);
> + acpi_pm1_cnt_write(&pm->acpi_regs, val, 0);
> break;
> default:
> pm_ioport_write_fallback(opaque, addr, 2, val);
> @@ -130,13 +131,13 @@ static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
>
> switch (addr & ICH9_PMIO_MASK) {
> case ICH9_PMIO_PM1_STS:
> - val = acpi_pm1_evt_get_sts(&pm->pm1a, pm->tmr.overflow_time);
> + val = acpi_pm1_evt_get_sts(&pm->acpi_regs);
> break;
> case ICH9_PMIO_PM1_EN:
> - val = pm->pm1a.en;
> + val = pm->acpi_regs.pm1.evt.en;
> break;
> case ICH9_PMIO_PM1_CNT:
> - val = pm->pm1_cnt.cnt;
> + val = pm->acpi_regs.pm1.cnt.cnt;
> break;
> default:
> val = pm_ioport_read_fallback(opaque, addr, 2);
> @@ -168,7 +169,7 @@ static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
>
> switch (addr & ICH9_PMIO_MASK) {
> case ICH9_PMIO_PM1_TMR:
> - val = acpi_pm_tmr_get(&pm->tmr);
> + val = acpi_pm_tmr_get(&pm->acpi_regs);
> break;
> case ICH9_PMIO_SMI_EN:
> val = pm->smi_en;
> @@ -238,7 +239,7 @@ void ich9_pm_iospace_update(ICH9_LPCPmRegs *pm, uint32_t pm_io_base)
> register_ioport_read(pm_io_base, ICH9_PMIO_SIZE, 4, pm_ioport_readl, pm);
>
> pm->pm_io_base = pm_io_base;
> - acpi_gpe_blk(&pm->gpe0, pm_io_base + ICH9_PMIO_GPE0_STS);
> + acpi_gpe_blk(&pm->acpi_regs, pm_io_base + ICH9_PMIO_GPE0_STS);
> }
>
> static int ich9_pm_post_load(void *opaque, int version_id)
> @@ -268,13 +269,13 @@ const VMStateDescription vmstate_ich9_pm = {
> .minimum_version_id_old = 1,
> .post_load = ich9_pm_post_load,
> .fields = (VMStateField[]) {
> - VMSTATE_UINT16(pm1a.sts, ICH9_LPCPmRegs),
> - VMSTATE_UINT16(pm1a.en, ICH9_LPCPmRegs),
> - VMSTATE_UINT16(pm1_cnt.cnt, ICH9_LPCPmRegs),
> - VMSTATE_TIMER(tmr.timer, ICH9_LPCPmRegs),
> - VMSTATE_INT64(tmr.overflow_time, ICH9_LPCPmRegs),
> - VMSTATE_GPE_ARRAY(gpe0.sts, ICH9_LPCPmRegs),
> - VMSTATE_GPE_ARRAY(gpe0.en, ICH9_LPCPmRegs),
> + VMSTATE_UINT16(acpi_regs.pm1.evt.sts, ICH9_LPCPmRegs),
> + VMSTATE_UINT16(acpi_regs.pm1.evt.en, ICH9_LPCPmRegs),
> + VMSTATE_UINT16(acpi_regs.pm1.cnt.cnt, ICH9_LPCPmRegs),
> + VMSTATE_TIMER(acpi_regs.tmr.timer, ICH9_LPCPmRegs),
> + VMSTATE_INT64(acpi_regs.tmr.overflow_time, ICH9_LPCPmRegs),
> + VMSTATE_GPE_ARRAY(acpi_regs.gpe.sts, ICH9_LPCPmRegs),
> + VMSTATE_GPE_ARRAY(acpi_regs.gpe.en, ICH9_LPCPmRegs),
> VMSTATE_UINT32(smi_en, ICH9_LPCPmRegs),
> VMSTATE_UINT32(smi_sts, ICH9_LPCPmRegs),
> VMSTATE_END_OF_LIST()
> @@ -286,10 +287,10 @@ static void pm_reset(void *opaque)
> ICH9_LPCPmRegs *pm = opaque;
> ich9_pm_iospace_update(pm, 0);
>
> - acpi_pm1_evt_reset(&pm->pm1a);
> - acpi_pm1_cnt_reset(&pm->pm1_cnt);
> - acpi_pm_tmr_reset(&pm->tmr);
> - acpi_gpe_reset(&pm->gpe0);
> + acpi_pm1_evt_reset(&pm->acpi_regs);
> + acpi_pm1_cnt_reset(&pm->acpi_regs);
> + acpi_pm_tmr_reset(&pm->acpi_regs);
> + acpi_gpe_reset(&pm->acpi_regs);
>
> pm_update_sci(pm);
> }
> @@ -297,17 +298,15 @@ static void pm_reset(void *opaque)
> static void pm_powerdown(void *opaque, int irq, int power_failing)
> {
> ICH9_LPCPmRegs *pm = opaque;
> - ACPIPM1EVT *pm1a = pm ? &pm->pm1a : NULL;
> - ACPIPMTimer *tmr = pm ? &pm->tmr : NULL;
>
> - acpi_pm1_evt_power_down(pm1a, tmr);
> + acpi_pm1_evt_power_down(&pm->acpi_regs);
> }
>
> void ich9_pm_init(ICH9_LPCPmRegs *pm, qemu_irq sci_irq, qemu_irq cmos_s3)
> {
> - acpi_pm_tmr_init(&pm->tmr, ich9_pm_update_sci_fn);
> - acpi_pm1_cnt_init(&pm->pm1_cnt, cmos_s3);
> - acpi_gpe_init(&pm->gpe0, ICH9_PMIO_GPE0_LEN);
> + acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn);
> + acpi_pm1_cnt_init(&pm->acpi_regs);
> + acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);
>
> pm->irq = sci_irq;
> qemu_register_reset(pm_reset, pm);
> diff --git a/hw/acpi_ich9.h b/hw/acpi_ich9.h
> index f55c0e9..9ff4c42 100644
> --- a/hw/acpi_ich9.h
> +++ b/hw/acpi_ich9.h
> @@ -24,19 +24,12 @@
> #include "acpi.h"
>
> typedef struct ICH9_LPCPmRegs {
> - ACPIPM1EVT pm1a;
> -
> /*
> * In ich9 spec says that pm1_cnt register is 32bit width and
> * that the upper 16bits are reserved and unused.
> * PM1a_CNT_BLK = 2 in FADT so it is defined as uint16_t.
> */
> - ACPIPM1CNT pm1_cnt;
> -
> - ACPIPMTimer tmr;
> -
> - ACPIGPE gpe0;
> -
> + ACPIREGS acpi_regs;
> uint32_t smi_en;
> uint32_t smi_sts;
>
> diff --git a/hw/pc.h b/hw/pc.h
> index c78923c..125c1fd 100644
> --- a/hw/pc.h
> +++ b/hw/pc.h
> @@ -69,6 +69,8 @@ int pic_read_irq(DeviceState *d);
> int pic_get_output(DeviceState *d);
> void pic_info(Monitor *mon);
> void irq_info(Monitor *mon);
> +void kvm_piix3_gsi_handler(void *opaque, int n, int level);
> +void kvm_piix3_setup_irq_routing(bool pci_enabled);
>
> /* Global System Interrupts */
>
> diff --git a/hw/pc_piix.c b/hw/pc_piix.c
> index 60c7166..57830ec 100644
> --- a/hw/pc_piix.c
> +++ b/hw/pc_piix.c
> @@ -53,7 +53,7 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
> static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
> static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
>
> -static void kvm_piix3_setup_irq_routing(bool pci_enabled)
> +void kvm_piix3_setup_irq_routing(bool pci_enabled)
> {
> #ifdef CONFIG_KVM
> KVMState *s = kvm_state;
> @@ -82,7 +82,7 @@ static void kvm_piix3_setup_irq_routing(bool pci_enabled)
> #endif /* CONFIG_KVM */
> }
>
> -static void kvm_piix3_gsi_handler(void *opaque, int n, int level)
> +void kvm_piix3_gsi_handler(void *opaque, int n, int level)
> {
> GSIState *s = opaque;
>
> diff --git a/hw/pc_q35.c b/hw/pc_q35.c
> index 4f75d97..9d58519 100644
> --- a/hw/pc_q35.c
> +++ b/hw/pc_q35.c
> @@ -27,6 +27,7 @@
> * Copyright (c) 2009, 2010
> * Isaku Yamahata <yamahata at valinux co jp>
> * VA Linux Systems Japan K.K.
> + * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> *
> * This is based on pc.c, but heavily modified.
> *
> @@ -49,7 +50,6 @@
> #include "fdc.h"
> #include "pci.h"
> #include "pci_bridge.h"
> -#include "pci_p2pbr.h"
> #include "ioh3420.h"
> #include "xio3130_upstream.h"
> #include "xio3130_downstream.h"
> @@ -66,36 +66,16 @@
> #include "watchdog.h"
> #include "smbios.h"
> #include "ide.h"
> -#include "usb-uhci.h"
> +#include "mc146818rtc.h"
> +#include "xen.h"
> +#include "kvm.h"
>
> #include "q35.h"
> +#include "exec-memory.h"
>
> /* ICH9 AHCI has 6 ports */
> #define MAX_SATA_PORTS 6
>
> -#define I21154_REV 0x05
> -#define I21154_PI 0x00
> -
> -static PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
> - bool multifunction)
> -{
> - const PCIP2PBridgeInit init = {
> - .bus = bus,
> - .devfn = devfn,
> - .multifunction = multifunction,
> -
> - .bus_name = bus_name,
> - .map_irq = pci_swizzle_map_irq_fn,
> - };
> - const PCIP2PBridgeProp prop = {
> - .vendor_id = PCI_VENDOR_ID_DEC,
> - .device_id = PCI_DEVICE_ID_DEC_21154,
> - .revision_id = I21154_REV,
> - .prog_interface = I21154_PI,
> - };
> - return pci_p2pbr_create_simple(&init, &prop);
> -}
> -
> static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
> {
> uint8_t dev;
> @@ -104,7 +84,6 @@ static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
> uint8_t chassis = 0;
> uint16_t slot = 0;
> uint8_t upstream_port;
> - PCIESlot *s;
> uint8_t fn;
> PCIESlot *root_port;
> PCIBus *root_port_bus;
> @@ -116,11 +95,10 @@ static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
> #define Q35_P2P_BRDIGE_DEV_MAX 32
> #define Q35_P2P_BRDIGE_SUBBUS_BASE (ICH9_D2P_SECONDARY_DEFAULT + 1)
> for (dev = Q35_P2P_BRDIGE_DEV_BASE; dev < Q35_P2P_BRDIGE_DEV_MAX; dev++) {
> - PCIBridge *br;
> sec_bus = Q35_P2P_BRDIGE_SUBBUS_BASE + dev - Q35_P2P_BRDIGE_DEV_BASE;
>
> snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
> - br = i21154_init(pci_bus, PCI_DEVFN(dev, 0), buf, true);
> + i21154_init(pci_bus, PCI_DEVFN(dev, 0), buf, true);
> }
>
> /* PCIe root port b0:d1:f0 in GMCH.
> @@ -128,8 +106,8 @@ static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
> */
> sec_bus = 32;
> snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
> - s = ioh3420_init(host_bus, PCI_DEVFN(GMCH_PCIE_DEV, GMCH_PCIE_FUNC), true,
> - buf, pci_swizzle_map_irq_fn, port, chassis, slot);
> + ioh3420_init(host_bus, PCI_DEVFN(GMCH_PCIE_DEV, GMCH_PCIE_FUNC), true,
> + buf, pci_swizzle_map_irq_fn, port, chassis, slot);
>
>
> /* more slots. ICH9 doesn't have those, but many slots are wanted. */
> @@ -153,8 +131,8 @@ static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
> slot++;
>
> snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
> - s = ioh3420_init(host_bus, PCI_DEVFN(23, fn), true,
> - buf, pci_swizzle_map_irq_fn, port, chassis, slot);
> + ioh3420_init(host_bus, PCI_DEVFN(23, fn), true,
> + buf, pci_swizzle_map_irq_fn, port, chassis, slot);
> }
>
> /* PCIe root port b0:d24:f0 */
> @@ -219,27 +197,38 @@ static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
> slot++;
>
> snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
> - s = ioh3420_init(host_bus, PCI_DEVFN(ICH9_PCIE_DEV, fn), true,
> - buf, pci_swizzle_map_irq_fn,
> - port, chassis, slot);
> + ioh3420_init(host_bus, PCI_DEVFN(ICH9_PCIE_DEV, fn), true,
> + buf, pci_swizzle_map_irq_fn,
> + port, chassis, slot);
> }
> }
>
> -static void pc_q35_init_early(qemu_irq *isa_irq, IsaIrqState *isa_irq_state,
> +static void pc_q35_init_early(qemu_irq *gsi, GSIState *gsi_state,
> DeviceState **gmch_host_p,
> PCIBus **host_bus_p, PCIBus **pci_bus_p,
> - PCIDevice **lpc_p)
> + PCIDevice **lpc_p, ISABus **isa_bus,
> + MemoryRegion *system_memory,
> + MemoryRegion *pci_address_space,
> + MemoryRegion *address_space_io,
> + MemoryRegion *ram_memory,
> + ram_addr_t below_4g_mem_size,
> + ram_addr_t above_4g_mem_size)
> {
> + target_phys_addr_t pci_hole64_size;
> DeviceState *gmch_host;
> PCIBus *host_bus;
> PCIBus *pci_bus;
>
> PCIDevice *gmch_state;
> PCIDevice *lpc;
> + GMCH_PCIState *gmps;
> + ICH9_LPCState *ich9_lpc;
>
> /* create pci host bus */
> - host_bus = gmch_host_init(&gmch_host, isa_irq, isa_irq_state->ioapic);
> + host_bus = gmch_host_init(&gmch_host, gsi, gsi_state->ioapic_irq,
> + pci_address_space, address_space_io);
> gmch_state = gmch_init(gmch_host, host_bus);
> + gmps = GMCH_PCI_DEVICE(gmch_state);
>
> /* create conventional pci bus: pcie2pci bridge */
> pci_bus = ich9_d2pbr_init(host_bus, PCI_DEVFN(ICH9_D2P_BRIDGE_DEV,
> @@ -252,10 +241,53 @@ static void pc_q35_init_early(qemu_irq *isa_irq, IsaIrqState *isa_irq_state,
> /* create ISA bus */
> lpc = gmch_lpc_init(gmch_host, host_bus);
>
> + gmps->ram_memory = ram_memory;
> + gmps->pci_address_space = pci_address_space;
> + gmps->system_memory = system_memory;
> + /* pci */
> + memory_region_init_alias(&gmps->pci_hole, "pci-hole",
> + gmps->pci_address_space,
> + below_4g_mem_size,
> + 0x100000000ULL - below_4g_mem_size);
> + memory_region_add_subregion(gmps->system_memory, below_4g_mem_size,
> + &gmps->pci_hole);
> + pci_hole64_size = (sizeof(target_phys_addr_t) == 4 ? 0 :
> + ((uint64_t)1 << 62));
> + memory_region_init_alias(&gmps->pci_hole_64bit, "pci-hole64",
> + gmps->pci_address_space,
> + 0x100000000ULL + above_4g_mem_size,
> + pci_hole64_size);
> + if (pci_hole64_size) {
> + memory_region_add_subregion(gmps->system_memory,
> + 0x100000000ULL + above_4g_mem_size,
> + &gmps->pci_hole_64bit);
> + }
> +
> + /* smram */
> + memory_region_init_alias(&gmps->smram_region, "smram-region",
> + pci_address_space, 0xa0000, 0x20000);
> + memory_region_add_subregion_overlap(system_memory, 0xa0000,
> + &gmps->smram_region, 1);
> + memory_region_set_enabled(&gmps->smram_region, false);
> +
> *gmch_host_p = gmch_host;
> *host_bus_p = host_bus;
> *pci_bus_p = pci_bus;
> *lpc_p = lpc;
> + ich9_lpc = ICH9_LPC_DEVICE(lpc);
> + *isa_bus = ich9_lpc->isa_bus;
> +}
> +
> +
> +/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
> + * BIOS will read it and start S3 resume at POST Entry */
> +static void pc_cmos_set_s3_resume(void *opaque, int irq, int level)
> +{
> + ISADevice *s = opaque;
> +
> + if (level) {
> + rtc_set_memory(s, 0xF, 0xFE);
> + }
> }
>
> static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,
> @@ -309,18 +341,22 @@ static void pc_q35_init(ram_addr_t ram_size,
> PCIBus *host_bus;
> PCIBus *pci_bus;
> PCIDevice *lpc;
> - qemu_irq *isa_irq;
> - IsaIrqState *isa_irq_state;
> BusState *idebus[MAX_SATA_PORTS];
> ISADevice *rtc_state;
> + ISADevice *floppy;
> MemoryRegion *pci_memory;
> MemoryRegion *rom_memory;
> MemoryRegion *ram_memory;
> + GSIState *gsi_state;
> + ISABus *isa_bus;
> + int pci_enabled = 1;
> + qemu_irq *cpu_irq;
> + qemu_irq *gsi;
> + qemu_irq *i8259;
> + int i;
>
> pc_cpus_init(cpu_model);
>
> - /* FIXME: add kvm clock ? */
> -
> if (ram_size >= 0xe0000000) {
> above_4g_mem_size = ram_size - 0xe0000000;
> below_4g_mem_size = 0xe0000000;
> @@ -330,37 +366,70 @@ static void pc_q35_init(ram_addr_t ram_size,
> }
>
> /* pci enabled */
> - pci_memory = g_new(MemoryRegion, 1);
> - memory_region_init(pci_memory, "pci", INT64_MAX);
> - rom_memory = pci_memory;
> + if (pci_enabled) {
> + pci_memory = g_new(MemoryRegion, 1);
> + memory_region_init(pci_memory, "pci", INT64_MAX);
> + rom_memory = pci_memory;
> + } else {
> + pci_memory = NULL;
> + rom_memory = get_system_memory();
> + }
>
> /* allocate ram and load rom/bios */
> - pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
> - initrd_filename, below_4g_mem_size, above_4g_mem_size,
> - rom_memory, &ram_memory);
> + if (!xen_enabled()) {
> + pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
> + initrd_filename, below_4g_mem_size, above_4g_mem_size,
> + rom_memory, &ram_memory);
> + }
>
> /* irq lines */
> - isa_irq = pc_isa_irq(&isa_irq_state);
> - ioapic_init(isa_irq_state);
> + gsi_state = g_malloc0(sizeof(*gsi_state));
> + if (kvm_irqchip_in_kernel()) {
> + kvm_piix3_setup_irq_routing(pci_enabled);
> + gsi = qemu_allocate_irqs(kvm_piix3_gsi_handler, gsi_state,
> + GSI_NUM_PINS);
> + } else {
> + gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
> + }
> +
> + pc_q35_init_early(gsi, gsi_state,
> + &gmch_host, &host_bus, &pci_bus, &lpc, &isa_bus,
> + get_system_memory(), pci_memory, get_system_io(),
> + ram_memory, below_4g_mem_size, above_4g_mem_size);
> + isa_bus_irqs(isa_bus, gsi);
> +
> + if (kvm_irqchip_in_kernel()) {
> + i8259 = kvm_i8259_init(isa_bus);
> + } else if (xen_enabled()) {
> + i8259 = xen_interrupt_controller_init();
> + } else {
> + cpu_irq = pc_allocate_cpu_irq();
> + i8259 = i8259_init(isa_bus, cpu_irq[0]);
> + }
> +
> + for (i = 0; i < ISA_NUM_IRQS; i++) {
> + gsi_state->i8259_irq[i] = i8259[i];
> + }
> + if (pci_enabled) {
> + ioapic_init_gsi(gsi_state, NULL);
> + }
>
> - pc_q35_init_early(isa_irq, isa_irq_state,
> - &gmch_host, &host_bus, &pci_bus, &lpc);
> - isa_bus_irqs(isa_irq);
> - pc_register_ferr_irq(isa_get_irq(13));
> + pc_register_ferr_irq(gsi[13]);
>
> /* init basic PC hardware */
> - pc_basic_device_init(isa_irq, &rtc_state, false);
> + pc_basic_device_init(isa_bus, gsi, &rtc_state, &floppy, false);
>
> pc_q35_init_late(idebus, rtc_state, gmch_host, host_bus, pci_bus, lpc);
>
> pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
> - idebus[0], idebus[1], rtc_state);
> + floppy, idebus[0], idebus[1], rtc_state);
>
> /* the rest devices to which pci devfn is automatically assigned */
> - pc_vga_init(host_bus);
> - audio_init(isa_irq, pci_bus);
> - pc_nic_init(pci_bus);
> - pc_pci_device_init(pci_bus);
> + pc_vga_init(isa_bus, host_bus);
> + audio_init(isa_bus, pci_bus);
> + pc_nic_init(isa_bus, pci_bus);
> + if (pci_enabled)
> + pc_pci_device_init(pci_bus);
Missing braces, please read CODING_STYLE.
> }
>
> static QEMUMachine pc_q35_machine = {
> diff --git a/hw/q35.c b/hw/q35.c
> index 1776ac3..09e8bd7 100644
> --- a/hw/q35.c
> +++ b/hw/q35.c
> @@ -25,6 +25,7 @@
> * Copyright (c) 2009, 2010, 2011
> * Isaku Yamahata <yamahata at valinux co jp>
> * VA Linux Systems Japan K.K.
> + * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> *
> * This is based on piix_pci.c, but heavily modified.
> *
> @@ -52,62 +53,16 @@
> #include "pci.h"
> #include "pcie_host.h"
> #include "pci_bridge.h"
> -#include "pci_p2pbr.h"
> #include "q35.h"
> #include "acpi.h"
> #include "acpi_ich9.h"
> #include "pam.h"
> +#include "pci_internals.h"
> +#include "exec-memory.h"
> +#include "isa.h"
> +#include "qemu-common.h"
>
>
> -struct ICH9_LPCState;
> -
> -typedef struct ICH9_LPCIrqState {
> - struct ICH9_LPCState *lpc;
> - qemu_irq *pic;
> - qemu_irq *ioapic;
> -} ICH9_LPCIrqState;
> -
> -typedef struct GMCH_PCIHost {
> - PCIExpressHost host;
> -
> - PCIDevice *dev;
> - ICH9_LPCIrqState irq_state;
> -} GMCH_PCIHost;
> -
> -typedef struct GMCH_PCIState {
> - PCIDevice d;
> - /*
> - * GMCH_PCIHost *gmch_host;
> - * In order to get GMCH_PCIHost
> - * PCIDevice -> qdev -> parent_bus -> qdev -upcast-> GMCH_PCIHost
> - */
> -
> - PAM pam;
> -} GMCH_PCIState;
> -
> -typedef struct ICH9_LPCState {
> - /* ICH9 LPC PCI to ISA bridge */
> - PCIDevice d;
> -
> - /* (pci device, intx) -> pirq
> - * In real chipset case, the unused slots are never used
> - * as ICH9 supports only D25-D32 irq routing.
> - * On the other hand in qemu case, any slot/function can be populated
> - * via command line option.
> - * So fallback interrupt routing for any devices in any slots is necessary.
> - */
> - uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
> -
> - APMState apm;
> - ICH9_LPCPmRegs pm;
> - uint32_t sci_level; /* track sci level */
> -
> - /* 10.1 Chipset Configuration registers(Memory Space)
> - which is pointed by RCBA */
> - uint8_t chip_config[ICH9_CC_SIZE];
> - int rbca_index;
> -} ICH9_LPCState;
> -
>
> /****************************************************************************
> * GMCH PCI host
> @@ -117,20 +72,20 @@ static int ich9_lpc_map_irq(void *opaque, PCIDevice *pci_dev, int intx);
> static void ich9_lpc_set_irq(void *opaque, int irq_num, int level);
> static int ich9_lpc_sci_irq(ICH9_LPCState *lpc);
>
> -static GMCH_PCIHost *gmch_pcihost_from_qdev(DeviceState *gmch_host_qdev)
> -{
> - SysBusDevice *sysdev = sysbus_from_qdev(gmch_host_qdev);
> - PCIHostState *pci = FROM_SYSBUS(PCIHostState, sysdev);
> - PCIExpressHost *pcie = DO_UPCAST(PCIExpressHost, pci, pci);
> - return DO_UPCAST(GMCH_PCIHost, host, pcie);
> -}
> -
> static int gmch_pcihost_initfn(SysBusDevice *dev)
> {
> - GMCH_PCIHost *s = gmch_pcihost_from_qdev(&dev->qdev);
> + PCIHostState *pci = FROM_SYSBUS(PCIHostState, dev);
> + GMCH_PCIHost *s = GMCH_HOST_DEVICE(&dev->qdev);
>
> - pci_host_conf_register_ioport(GMCH_HOST_BRIDGE_CONFIG_ADDR, &s->host.pci);
> - pci_host_data_register_ioport(GMCH_HOST_BRIDGE_CONFIG_DATA, &s->host.pci);
> + memory_region_init_io(&pci->conf_mem, &pci_host_conf_le_ops, pci,
> + "pci-conf-idx", 4);
> + sysbus_add_io(dev, GMCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem);
> + sysbus_init_ioports(&pci->busdev, GMCH_HOST_BRIDGE_CONFIG_ADDR, 4);
> +
> + memory_region_init_io(&pci->data_mem, &pci_host_data_le_ops, pci,
> + "pci-conf-data", 4);
> + sysbus_add_io(dev, GMCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem);
> + sysbus_init_ioports(&pci->busdev, GMCH_HOST_BRIDGE_CONFIG_DATA, 4);
>
> if (pcie_host_init(&s->host) < 0) {
> abort();
> @@ -139,36 +94,46 @@ static int gmch_pcihost_initfn(SysBusDevice *dev)
> return 0;
> }
>
> -static SysBusDeviceInfo gmch_pcihost_info = {
> - .init = gmch_pcihost_initfn,
> - .qdev.name = "gmch-pcihost",
> - .qdev.size = sizeof(GMCH_PCIHost),
> - .qdev.no_user = 1,
> - .qdev.props = (Property[]) {
> - {
> - .name = "MCFG",
> - .info = &qdev_prop_uint64,
> - .offset = offsetof(GMCH_PCIHost, host.base_addr),
> - .defval = (uint64_t[]){ GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT },
> - },
> - DEFINE_PROP_END_OF_LIST(),
> - },
> +static Property gmch_props[] = {
> + DEFINE_PROP_UINT64("MCFG", GMCH_PCIHost, host.base_addr,
> + GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void gmch_pcihost_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
> +
> + k->init = gmch_pcihost_initfn;
> + dc->props = gmch_props;
> + dc->no_user = 1;
> +}
> +
> +static TypeInfo gmch_pcihost_info = {
> + .name = TYPE_GMCH_HOST_DEVICE,
> + .parent = TYPE_PCIE_HOST_BRIDGE,
> + .instance_size = sizeof(GMCH_PCIHost),
> + .class_init = gmch_pcihost_class_init,
> };
>
> /* host bridge */
> PCIBus *gmch_host_init(DeviceState **gmch_hostp,
> - qemu_irq *pic, qemu_irq *ioapic)
> + qemu_irq *pic, qemu_irq *ioapic,
> + MemoryRegion *pci_address_space,
> + MemoryRegion *address_space_io)
> {
> DeviceState *dev;
> GMCH_PCIHost *s;
> PCIBus *b;
>
> - dev = qdev_create(NULL, "gmch-pcihost");
> - s = gmch_pcihost_from_qdev(dev);
> + dev = qdev_create(NULL, TYPE_GMCH_HOST_DEVICE);
> + s = GMCH_HOST_DEVICE(dev);
> s->irq_state.pic = pic;
> s->irq_state.ioapic = ioapic;
>
> - b = pci_bus_new(dev, "pcie.0", 0);
> + b = pci_bus_new(&s->host.pci.busdev.qdev, "pcie.0", pci_address_space,
> + address_space_io, 0);
> pci_bus_irqs(b, ich9_lpc_set_irq, ich9_lpc_map_irq, &s->irq_state,
> ICH9_LPC_NB_PIRQS);
> s->host.pci.bus = b;
> @@ -180,12 +145,8 @@ PCIBus *gmch_host_init(DeviceState **gmch_hostp,
>
>
> /****************************************************************************
> - * GMCH
> + * GMCH D0:F0
> */
> -static GMCH_PCIState *gmch_from_pci(PCIDevice *gmch_pci)
> -{
> - return DO_UPCAST(GMCH_PCIState, d, gmch_pci);
> -}
>
> /* PCIE MMCFG */
> static void gmch_update_pciexbar(GMCH_PCIState *gs)
> @@ -193,7 +154,7 @@ static void gmch_update_pciexbar(GMCH_PCIState *gs)
> PCIDevice *pci_dev = &gs->d;
> BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
> DeviceState *qdev = bus->parent;
> - GMCH_PCIHost *s = gmch_pcihost_from_qdev(qdev);
> + GMCH_PCIHost *s = GMCH_HOST_DEVICE(qdev);
>
> uint64_t pciexbar;
> int enable;
> @@ -234,27 +195,39 @@ static void gmch_update_pciexbar(GMCH_PCIState *gs)
> static void gmch_update_pam(GMCH_PCIState *gs)
> {
> int i;
> +
> + memory_region_transaction_begin();
> for (i = 0; i <= PAM_IDX_MAX; i++) {
> - pam_update(&gs->pam, i, gs->d.config[GMCH_HOST_BRIDGE_PAM0 + i]);
> + pam_update(&gs->pam_regions[0], i,
> + gs->d.config[GMCH_HOST_BRIDGE_PAM0 + i],
> + gs->ram_memory, gs->pci_address_space, gs->system_memory);
> }
> + memory_region_transaction_commit();
> }
>
> /* SMRAM */
> static void gmch_update_smram(GMCH_PCIState *gs)
> {
> - smram_update(&gs->pam, gs->d.config[GMCH_HOST_BRDIGE_SMRAM]);
> + memory_region_transaction_begin();
> + smram_update(&gs->smram_region, gs->d.config[GMCH_HOST_BRDIGE_SMRAM],
> + gs->smm_enabled);
> + memory_region_transaction_commit();
> }
>
> static void gmch_set_smm(int smm, void *arg)
> {
> GMCH_PCIState *gs = arg;
> - smram_set_smm(&gs->pam, smm, gs->d.config[GMCH_HOST_BRDIGE_SMRAM]);
> +
> + memory_region_transaction_begin();
> + smram_set_smm(&gs->smm_enabled, smm, gs->d.config[GMCH_HOST_BRDIGE_SMRAM],
> + &gs->smram_region);
> + memory_region_transaction_commit();
> }
>
> static void gmch_write_config(PCIDevice *d,
> uint32_t address, uint32_t val, int len)
> {
> - GMCH_PCIState *gs = gmch_from_pci(d);
> + GMCH_PCIState *gs = GMCH_PCI_DEVICE(d);
>
> /* XXX: implement SMRAM.D_LOCK */
> pci_default_write_config(d, address, val, len);
> @@ -297,15 +270,15 @@ static const VMStateDescription vmstate_gmch = {
> .post_load = gmch_post_load,
> .fields = (VMStateField []) {
> VMSTATE_PCI_DEVICE(d, GMCH_PCIState),
> - VMSTATE_UINT8(pam.smm_enabled, GMCH_PCIState),
> + VMSTATE_UINT8(smm_enabled, GMCH_PCIState),
> VMSTATE_END_OF_LIST()
> }
> };
>
> static void gmch_reset(DeviceState *qdev)
> {
> - PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
> - GMCH_PCIState *gs = gmch_from_pci(d);
> + PCIDevice *d = PCI_DEVICE(qdev);
> + GMCH_PCIState *gs = GMCH_PCI_DEVICE(d);
>
> pci_set_quad(d->config + GMCH_HOST_BRIDGE_PCIEXBAR,
> GMCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
> @@ -315,39 +288,46 @@ static void gmch_reset(DeviceState *qdev)
> gmch_update(gs);
> }
>
> -static int gmch_initfn(PCIDevice *d)
> +static int pci_gmch_initfn(PCIDevice *d)
> {
> - GMCH_PCIState *gs = gmch_from_pci(d);
> -
> - pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
> - pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_Q35_MCH);
> - pci_config_set_revision(d->config, GMCH_HOST_BRIDGE_REVISION_DEFUALT);
> - pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST);
> + GMCH_PCIState *gs = GMCH_PCI_DEVICE(d);
>
> cpu_smm_register(&gmch_set_smm, gs);
> - pam_init_memory_mappings(&gs->pam);
>
> return 0;
> }
>
> -static PCIDeviceInfo gmch_info = {
> - .qdev.name = "gmch",
> - .qdev.desc = "Host bridge",
> - .qdev.size = sizeof(GMCH_PCIState),
> - .qdev.vmsd = &vmstate_gmch,
> - .qdev.no_user = 1,
> - .init = gmch_initfn,
> - .config_write = gmch_write_config,
> - .qdev.reset = gmch_reset,
> +static void pci_gmch_class_init(ObjectClass *klass, void *data)
> +{
> + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + k->init = pci_gmch_initfn;
> + k->config_write = gmch_write_config;
> + dc->reset = gmch_reset;
> + dc->desc = "Host bridge";
> + dc->vmsd = &vmstate_gmch;
> + dc->no_user = 1;
> + k->vendor_id = PCI_VENDOR_ID_INTEL;
> + k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH;
> + k->revision = GMCH_HOST_BRIDGE_REVISION_DEFUALT;
> + k->class_id = PCI_CLASS_BRIDGE_HOST;
> +}
> +
> +struct TypeInfo pci_gmch_info = {
'static const'
> + .name = TYPE_GMCH_PCI_DEVICE,
> + .parent = TYPE_PCI_DEVICE,
> + .instance_size = sizeof(GMCH_PCIState),
> + .class_init = pci_gmch_class_init,
> };
>
> /* host bridge */
> PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b)
> {
> - GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
> + GMCH_PCIHost *s = GMCH_HOST_DEVICE(gmch_host);
> PCIDevice *d;
>
> - d = pci_create_simple_multifunction(b, 0, false, "gmch");
> + d = pci_create_simple_multifunction(b, 0, false, TYPE_GMCH_PCI_DEVICE);
> s->dev = d;
>
> return d;
> @@ -359,54 +339,135 @@ PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b)
> #define I82801ba_SSVID_SVID 0
> #define I82801ba_SSVID_SSID 0
>
> -static PCIBridge *i82801ba11_init(PCIBus *bus, int devfn, const char *bus_name,
> - bool multifunction)
> +struct i82801b11_bridge {
> + PCIBridge br;
> +};
> +
> +static int i82801b11_bridge_initfn(PCIDevice *d)
> {
> - const PCIP2PBridgeInit init = {
> - .bus = bus,
> - .devfn = devfn,
> - .multifunction = multifunction,
> + int rc;
> +
> + rc = pci_bridge_initfn(d);
> + if (rc < 0) {
> + return rc;
> + }
> +
> + rc = pci_bridge_ssvid_init(d, I82801ba_SSVID_OFFSET,
> + I82801ba_SSVID_SVID, I82801ba_SSVID_SSID);
> + if (rc < 0) {
> + goto err_bridge;
> + }
> + return 0;
>
> - .bus_name = bus_name,
> - .map_irq = pci_swizzle_map_irq_fn,
> - };
> - const PCIP2PBridgeProp prop = {
> - .vendor_id = PCI_VENDOR_ID_INTEL,
> - .device_id = PCI_DEVICE_ID_INTEL_82801BA_11,
> - .revision_id = ICH9_D2P_A2_REVISION,
> - .prog_interface = PCI_CLASS_BRDIGE_PCI_INF_SUB,
> +err_bridge:
> + pci_bridge_exitfn(d);
>
> - .ssvid_cap = I82801ba_SSVID_OFFSET,
> - .svid = I82801ba_SSVID_SVID,
> - .ssid = I82801ba_SSVID_SSID,
> - };
> - return pci_p2pbr_create_simple(&init, &prop);
> + return rc;
> }
>
> +static void i82801b11_bridge_class_init(ObjectClass *klass, void *data)
> +{
> + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> +
> + k->is_bridge = 1;
> + k->vendor_id = PCI_VENDOR_ID_INTEL;
> + k->device_id = PCI_DEVICE_ID_INTEL_82801BA_11;
> + k->revision = ICH9_D2P_A2_REVISION;
> + k->init = i82801b11_bridge_initfn;
> +}
> +
> +static TypeInfo i82801b11_bridge_info = {
'const'
> + .name = "i82801b11-bridge",
> + .parent = TYPE_PCI_DEVICE,
> + .instance_size = sizeof(struct i82801b11_bridge),
> + .class_init = i82801b11_bridge_class_init,
> +};
> +
> PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus)
> {
> + PCIDevice *d;
> PCIBridge *br;
> char buf[16];
> + DeviceState *qdev;
>
> - snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
> - br = i82801ba11_init(bus, devfn, buf, true);
> - if (br == NULL) {
> + d = pci_create_multifunction(bus, devfn, true, "i82801b11-bridge");
> + if (!d) {
> return NULL;
> }
> + br = DO_UPCAST(PCIBridge, dev, d);
> + qdev = &br->dev.qdev;
> +
> + snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
> + pci_bridge_map_irq(br, buf, pci_swizzle_map_irq_fn);
> + qdev_init_nofail(qdev);
> +
> return pci_bridge_get_sec_bus(br);
> }
> +/*****************************************************************************/
> +/* i21154 pci bridge*/
>
> +struct i21154_bridge {
I21154Bridge. If the device has a non-numeric name too that would be better.
> + PCIBridge br;
> +};
>
> -/*****************************************************************************/
> -/* ICH9 LPC PCI to ISA bridge */
> +static int i21154_bridge_initfn(PCIDevice *d)
> +{
> + int rc;
>
> -static void ich9_lpc_reset(DeviceState *qdev);
> + rc = pci_bridge_initfn(d);
> + if (rc < 0) {
> + return rc;
> + }
> +
> + return 0;
> +}
> +
> +#define I21154_REV 0x05
> +#define I21154_PI 0x00
> +
> +static void i21154_bridge_class_init(ObjectClass *klass, void *data)
> +{
> + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> +
> + k->is_bridge = 1;
> + k->vendor_id = PCI_VENDOR_ID_DEC;
> + k->device_id = PCI_DEVICE_ID_DEC_21154;
> + k->revision = I21154_REV;
> + k->init = i21154_bridge_initfn;
> +}
> +
> +static TypeInfo i21154_bridge_info = {
'const'
> + .name = "i21154-bridge",
> + .parent = TYPE_PCI_DEVICE,
> + .instance_size = sizeof(struct i21154_bridge),
> + .class_init = i21154_bridge_class_init,
> +};
>
> -static ICH9_LPCState *ich9_lpc_from_pci(PCIDevice *lpc_pci)
> +PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
> + bool multifunction)
> {
> - return DO_UPCAST(ICH9_LPCState, d, lpc_pci);
> + PCIDevice *d;
> + PCIBridge *br;
> + DeviceState *qdev;
> +
> + d = pci_create_multifunction(bus, devfn, multifunction, "i21154-bridge");
> + if (!d) {
> + return NULL;
> + }
> + br = DO_UPCAST(PCIBridge, dev, d);
> + qdev = &br->dev.qdev;
> +
> + pci_bridge_map_irq(br, bus_name, pci_swizzle_map_irq_fn);
> + qdev_init_nofail(qdev);
> +
> + return br;
> }
>
> +/*****************************************************************************/
> +/* ICH9 LPC PCI to ISA bridge */
> +
> +static void ich9_lpc_reset(DeviceState *qdev);
> +
> /* chipset configuration register
> * to access chipset configuration registers, pci_[sg]et_{byte, word, long}
> * are used.
> @@ -485,7 +546,7 @@ static void ich9_cc_reset(ICH9_LPCState *lpc)
> ich9_cc_update(lpc);
> }
>
> -static void ich9_cc_addr_len(uint32_t *addr, int *len)
> +static void ich9_cc_addr_len(uint64_t *addr, unsigned *len)
> {
> *addr &= ICH9_CC_ADDR_MASK;
> if (*addr + *len >= ICH9_CC_SIZE) {
> @@ -494,56 +555,27 @@ static void ich9_cc_addr_len(uint32_t *addr, int *len)
> }
>
> /* val: little endian */
> -static void ich9_cc_write(ICH9_LPCState *lpc, uint32_t addr,
> - uint32_t val, int len)
> +static void ich9_cc_write(void *opaque, target_phys_addr_t addr,
> + uint64_t val, unsigned len)
> {
> + ICH9_LPCState *lpc = (ICH9_LPCState *)opaque;
> +
> ich9_cc_addr_len(&addr, &len);
> memcpy(lpc->chip_config + addr, &val, len);
> }
>
> /* return value: little endian */
> -static uint32_t ich9_cc_read(ICH9_LPCState *lpc, uint32_t addr, int len)
> +static uint64_t ich9_cc_read(void *opaque, target_phys_addr_t addr,
> + unsigned len)
> {
> + ICH9_LPCState *lpc = (ICH9_LPCState *)opaque;
> +
> uint32_t val = 0;
> ich9_cc_addr_len(&addr, &len);
> memcpy(&val, lpc->chip_config + addr, len);
> return val;
> }
>
> -#define ICH9_CC_MMIO_WRITE(type, len) \
> - static void ich9_cc_mmio_write ## type \
> - (void *opaque, target_phys_addr_t addr, uint32_t val) \
> - { \
> - ich9_cc_write(opaque, addr, val, len); \
> - }
> -
> -#define ICH9_CC_MMIO_READ(type, len) \
> - static uint32_t ich9_cc_mmio_read ## type \
> - (void *opaque, target_phys_addr_t addr) \
> - { \
> - return ich9_cc_read(opaque, addr, len); \
> - }
> -
> -ICH9_CC_MMIO_WRITE(b, 1)
> -ICH9_CC_MMIO_WRITE(w, 2)
> -ICH9_CC_MMIO_WRITE(l, 4)
> -
> -ICH9_CC_MMIO_READ(b, 1)
> -ICH9_CC_MMIO_READ(w, 2)
> -ICH9_CC_MMIO_READ(l, 4)
> -
> -static CPUWriteMemoryFunc * const ich9_cc_mmio_write[] = {
> - ich9_cc_mmio_writeb,
> - ich9_cc_mmio_writew,
> - ich9_cc_mmio_writel,
> -};
> -
> -static CPUReadMemoryFunc * const ich9_cc_mmio_read[] = {
> - ich9_cc_mmio_readb,
> - ich9_cc_mmio_readw,
> - ich9_cc_mmio_readl,
> -};
> -
> /* IRQ routing */
> /* */
> static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis)
> @@ -702,8 +734,8 @@ static void ich9_set_sci(void *opaque, int irq_num, int level)
> void ich9_lpc_pm_init(DeviceState *gmch_host, PCIDevice *lpc_pci,
> qemu_irq cmos_s3)
> {
> - GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
> - ICH9_LPCState *lpc = ich9_lpc_from_pci(lpc_pci);
> + GMCH_PCIHost *s = GMCH_HOST_DEVICE(gmch_host);
> + ICH9_LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
> qemu_irq *sci_irq;
>
> sci_irq = qemu_allocate_irqs(ich9_set_sci, &s->irq_state, 1);
> @@ -713,12 +745,14 @@ void ich9_lpc_pm_init(DeviceState *gmch_host, PCIDevice *lpc_pci,
> }
>
> /* APM */
> +
> +
> static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
> {
> ICH9_LPCState *lpc = arg;
>
> /* ACPI specs 3.0, 4.7.2.5 */
> - acpi_pm1_cnt_update(&lpc->pm.pm1_cnt,
> + acpi_pm1_cnt_update(&lpc->pm.acpi_regs,
> val == ICH9_APM_ACPI_ENABLE,
> val == ICH9_APM_ACPI_DISABLE);
>
> @@ -744,12 +778,12 @@ static void ich9_lpc_rcba_update(ICH9_LPCState *lpc, uint32_t rbca_old)
> uint32_t rbca = pci_get_long(lpc->d.config + ICH9_LPC_RCBA);
>
> if (rbca_old & ICH9_LPC_RCBA_EN) {
> - cpu_register_physical_memory(rbca_old & ICH9_LPC_RCBA_BA_MASK,
> - ICH9_CC_SIZE, IO_MEM_UNASSIGNED);
> + memory_region_del_subregion(get_system_memory(), &lpc->rbca_mem);
> }
> if (rbca & ICH9_LPC_RCBA_EN) {
> - cpu_register_physical_memory(rbca & ICH9_LPC_RCBA_BA_MASK,
> - ICH9_CC_SIZE, lpc->rbca_index);
> + memory_region_add_subregion_overlap(get_system_memory(),
> + rbca & ICH9_LPC_RCBA_BA_MASK,
> + &lpc->rbca_mem, 1);
> }
> }
>
> @@ -765,7 +799,7 @@ static int ich9_lpc_post_load(void *opaque, int version_id)
> static void ich9_lpc_config_write(PCIDevice *d,
> uint32_t addr, uint32_t val, int len)
> {
> - ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
> + ICH9_LPCState *lpc = ICH9_LPC_DEVICE(d);
> uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA);
>
> pci_default_write_config(d, addr, val, len);
> @@ -779,8 +813,8 @@ static void ich9_lpc_config_write(PCIDevice *d,
>
> static void ich9_lpc_reset(DeviceState *qdev)
> {
> - PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
> - ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
> + PCIDevice *d = PCI_DEVICE(qdev);
> + ICH9_LPCState *lpc = ICH9_LPC_DEVICE(d);
> uint32_t rbca_old = pci_get_long(d->config + ICH9_LPC_RCBA);
> int i;
>
> @@ -805,22 +839,26 @@ static void ich9_lpc_reset(DeviceState *qdev)
> lpc->sci_level = 0;
> }
>
> +static const MemoryRegionOps rbca_mmio_ops = {
> + .read = ich9_cc_read,
> + .write = ich9_cc_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> +};
> +
> static int ich9_lpc_initfn(PCIDevice *d)
> {
> - ICH9_LPCState *lpc = ich9_lpc_from_pci(d);
> + ICH9_LPCState *lpc = ICH9_LPC_DEVICE(d);
> + ISABus *isa_bus;
>
> - isa_bus_new(&d->qdev);
> - pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
> - pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_ICH9_8); /* ICH9 LPC */
> - pci_config_set_revision(d->config, ICH9_A2_LPC_REVISION);
> - pci_config_set_class(d->config, PCI_CLASS_BRIDGE_ISA);
> + isa_bus = isa_bus_new(&d->qdev, get_system_io());
>
> pci_set_long(d->wmask + ICH9_LPC_PMBASE,
> ICH9_LPC_PMBASE_BASE_ADDRESS_MASK);
>
> - lpc->rbca_index = cpu_register_io_memory(ich9_cc_mmio_read,
> - ich9_cc_mmio_write,
> - lpc, DEVICE_LITTLE_ENDIAN);
> + memory_region_init_io(&lpc->rbca_mem, &rbca_mmio_ops, lpc,
> + "lpc-rbca-mmio", ICH9_CC_SIZE);
> +
> + lpc->isa_bus = isa_bus;
>
> ich9_cc_init(lpc);
> apm_init(&lpc->apm, ich9_apm_ctrl_changed, lpc);
> @@ -845,33 +883,50 @@ static const VMStateDescription vmstate_ich9_lpc = {
>
> PCIDevice *gmch_lpc_init(DeviceState *gmch_host, PCIBus *bus)
> {
> - GMCH_PCIHost *s = gmch_pcihost_from_qdev(gmch_host);
> + GMCH_PCIHost *s = GMCH_HOST_DEVICE(gmch_host);
> PCIDevice *d;
> ICH9_LPCState *lpc;
>
> d = pci_create_simple_multifunction(bus, PCI_DEVFN(ICH9_LPC_DEV,
> ICH9_LPC_FUNC),
> - true, "ICH9 LPC");
> - lpc = ich9_lpc_from_pci(d);
> + true, TYPE_ICH9_LPC_DEVICE);
> + lpc = ICH9_LPC_DEVICE(d);
> s->irq_state.lpc = lpc;
> return &lpc->d;
> }
>
> -static PCIDeviceInfo ich9_lpc_info = {
> - .qdev.name = "ICH9 LPC",
> - .qdev.desc = "ICH9 LPC bridge",
> - .qdev.size = sizeof(ICH9_LPCState),
> - .qdev.vmsd = &vmstate_ich9_lpc,
> - .qdev.no_user = 1,
> - .init = ich9_lpc_initfn,
> - .config_write = ich9_lpc_config_write,
> - .qdev.reset = ich9_lpc_reset,
> +static void ich9_lpc_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> +
> + dc->reset = ich9_lpc_reset;
> + k->init = ich9_lpc_initfn;
> + dc->vmsd = &vmstate_ich9_lpc;
> + dc->no_user = 1;
> + k->config_write = ich9_lpc_config_write;
> + dc->desc = "ICH9 LPC bridge";
> + k->vendor_id = PCI_VENDOR_ID_INTEL;
> + k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8;
> + k->revision = ICH9_A2_LPC_REVISION;
> + k->class_id = PCI_CLASS_BRIDGE_ISA;
> +
> +}
> +
> +static TypeInfo ich9_lpc_info = {
'const'
> + .name = TYPE_ICH9_LPC_DEVICE,
> + .parent = TYPE_PCI_DEVICE,
> + .instance_size = sizeof(struct ICH9_LPCState),
> + .class_init = ich9_lpc_class_init,
> };
>
> static void q35_register(void)
> {
> - sysbus_register_withprop(&gmch_pcihost_info);
> - pci_qdev_register(&gmch_info);
> - pci_qdev_register(&ich9_lpc_info);
> + type_register_static(&pci_gmch_info);
> + type_register_static(&gmch_pcihost_info);
> + type_register_static(&i82801b11_bridge_info);
> + type_register_static(&i21154_bridge_info);
> + type_register_static(&ich9_lpc_info);
> }
> -device_init(q35_register);
> +
> +type_init(q35_register);
> diff --git a/hw/q35.h b/hw/q35.h
> index be2e96b..030386e 100644
> --- a/hw/q35.h
> +++ b/hw/q35.h
> @@ -21,19 +21,109 @@
> #ifndef HW_Q35_H
> #define HW_Q35_H
>
> +#include "hw.h"
> +#include "range.h"
> +#include "isa.h"
> #include "sysbus.h"
> +#include "pc.h"
> +#include "apm.h"
> +#include "apic.h"
> +#include "pci.h"
> +#include "pcie_host.h"
> +#include "pci_bridge.h"
> +#include "q35.h"
> +#include "acpi.h"
> #include "acpi_ich9.h"
> +#include "pam.h"
> +#include "pci_internals.h"
> +
> +
> +#define ICH9_CC_SIZE (16 * 1024) /* 16KB */
> +
> +#define TYPE_GMCH_HOST_DEVICE "gmch-pcihost"
> +#define GMCH_HOST_DEVICE(obj) \
> + OBJECT_CHECK(GMCH_PCIHost, (obj), TYPE_GMCH_HOST_DEVICE)
> +
> +#define TYPE_GMCH_PCI_DEVICE "gmch"
> +#define GMCH_PCI_DEVICE(obj) \
> + OBJECT_CHECK(GMCH_PCIState, (obj), TYPE_GMCH_PCI_DEVICE)
> +
> +#define TYPE_ICH9_LPC_DEVICE "ICH9 LPC"
> +#define ICH9_LPC_DEVICE(obj) \
> + OBJECT_CHECK(ICH9_LPCState, (obj), TYPE_ICH9_LPC_DEVICE)
> +
> +struct ICH9_LPCState;
ICH9LPCState, typedef missing.
> +
> +typedef struct ICH9_LPCIrqState {
ICH9LPCIRQState
> + struct ICH9_LPCState *lpc;
> + qemu_irq *pic;
> + qemu_irq *ioapic;
> +} ICH9_LPCIrqState;
> +
> +typedef struct GMCH_PCIHost {
GMCHPCIHost, or does GMCH stand for something that is more suitable
for CamelCasing?
> + PCIExpressHost host;
> +
> + PCIDevice *dev;
> + ICH9_LPCIrqState irq_state;
> +} GMCH_PCIHost;
> +
> +typedef struct GMCH_PCIState {
> + PCIDevice d;
> + /*
> + * GMCH_PCIHost *gmch_host;
> + * In order to get GMCH_PCIHost
> + * PCIDevice -> qdev -> parent_bus -> qdev -upcast-> GMCH_PCIHost
> + */
> + MemoryRegion *ram_memory;
> + MemoryRegion *pci_address_space;
> + MemoryRegion *system_memory;
> + PAMMemoryRegion pam_regions[13];
> + MemoryRegion smram_region;
> + MemoryRegion pci_hole;
> + MemoryRegion pci_hole_64bit;
> + uint8_t smm_enabled;
> +} GMCH_PCIState;
> +
> +typedef struct ICH9_LPCState {
The typedef part should be declared earlier so that other structures
can use the typedef.
> + /* ICH9 LPC PCI to ISA bridge */
> + PCIDevice d;
> +
> + /* (pci device, intx) -> pirq
> + * In real chipset case, the unused slots are never used
> + * as ICH9 supports only D25-D32 irq routing.
> + * On the other hand in qemu case, any slot/function can be populated
> + * via command line option.
> + * So fallback interrupt routing for any devices in any slots is necessary.
> + */
> + uint8_t irr[PCI_SLOT_MAX][PCI_NUM_PINS];
> +
> + APMState apm;
> + ICH9_LPCPmRegs pm;
> + uint32_t sci_level; /* track sci level */
> +
> + /* 10.1 Chipset Configuration registers(Memory Space)
> + which is pointed by RCBA */
> + uint8_t chip_config[ICH9_CC_SIZE];
> + /* isa bus */
> + ISABus *isa_bus;
> + MemoryRegion rbca_mem;
> +} ICH9_LPCState;
>
> -PCIBus *gmch_host_init(DeviceState **gmch_hostp,
> - qemu_irq *pic, qemu_irq *ioapic);
>
> +
> +
> +PCIBus *gmch_host_init(DeviceState **gmch_hostp,
> + qemu_irq *pic, qemu_irq *ioapic,
> + MemoryRegion *pci_address_space,
> + MemoryRegion *address_space_io);
> PCIDevice *gmch_init(DeviceState *gmch_host, PCIBus *b);
> PCIBus *ich9_d2pbr_init(PCIBus *bus, int devfn, int sec_bus);
> PCIDevice *gmch_lpc_init(DeviceState *gmch_host, PCIBus *bus);
> void ich9_lpc_pm_init(DeviceState *gmch_host, PCIDevice *pci_lpc,
> qemu_irq cmos_s3);
> -
> i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
> +PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
> + bool multifunction);
>
> #define Q35_MASK(bit, ms_bit, ls_bit) \
> ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
> @@ -124,7 +214,6 @@ i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
> */
>
> /* ICH9: Chipset Configuration Registers */
> -#define ICH9_CC_SIZE (16 * 1024) /* 16KB */
> #define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
>
> #define ICH9_CC
> diff --git a/hw/q35_smbus.c b/hw/q35_smbus.c
> index fe445ac..0ee404e 100644
> --- a/hw/q35_smbus.c
> +++ b/hw/q35_smbus.c
> @@ -18,6 +18,7 @@
> /*
> * Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
> * VA Linux Systems Japan K.K.
> + * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
> *
> * This is based on acpi.c, but heavily rewritten.
> */
> @@ -35,6 +36,7 @@ typedef struct ICH9_SMBState {
> PCIDevice dev;
>
> PMSMBus smb;
> + MemoryRegion mem_bar;
> } ICH9_SMBState;
>
> static ICH9_SMBState *ich9_pci_to_smb(PCIDevice* pci_dev)
> @@ -53,7 +55,8 @@ static const VMStateDescription vmstate_ich9_smbus = {
> }
> };
>
> -static void ich9_smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
> +static void ich9_smb_ioport_writeb(void *opaque, target_phys_addr_t addr,
> + uint64_t val, unsigned size)
> {
> ICH9_SMBState *s = opaque;
> uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
> @@ -64,7 +67,8 @@ static void ich9_smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
> }
> }
>
> -static uint32_t ich9_smb_ioport_readb(void *opaque, uint32_t addr)
> +static uint64_t ich9_smb_ioport_readb(void *opaque, target_phys_addr_t addr,
> + unsigned size)
> {
> ICH9_SMBState *s = opaque;
> uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
> @@ -77,32 +81,22 @@ static uint32_t ich9_smb_ioport_readb(void *opaque, uint32_t addr)
> return 0xff;
> }
>
> -static void ich9_smb_map_ioport(PCIDevice *dev, int region_num,
> - uint64_t addr, uint64_t size, int type)
> -{
> - ICH9_SMBState *s = ich9_pci_to_smb(dev);
> -
> - assert(size == ICH9_SMB_SMB_BASE_SIZE);
> - assert(type == PCI_BASE_ADDRESS_SPACE_IO);
> -
> - register_ioport_write(addr, 64, 1, ich9_smb_ioport_writeb, s);
> - register_ioport_read(addr, 64, 1, ich9_smb_ioport_readb, s);
> -}
> +static const MemoryRegionOps lpc_smb_mmio_ops = {
> + .read = ich9_smb_ioport_readb,
> + .write = ich9_smb_ioport_writeb,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .impl = {
> + .min_access_size = 1,
> + .max_access_size = 1,
> + },
> +};
>
> -static int ich9_smb_initfn(PCIDevice *d)
> +static int ich9_smbus_initfn(PCIDevice *d)
> {
> ICH9_SMBState *s = ich9_pci_to_smb(d);
>
> - pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_INTEL);
> - pci_config_set_device_id(d->config, PCI_DEVICE_ID_INTEL_ICH9_6);
> -
> pci_set_word(d->wmask + PCI_STATUS,
> - PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
> -
> - pci_config_set_revision(d->config, ICH9_A2_SMB_REVISION);
> - pci_config_set_prog_interface(d->config, ICH9_SMB_PI);
> - pci_config_set_class(d->config, PCI_CLASS_SERIAL_SMBUS);
> -
> + PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
> /* TODO? D31IP.SMIP in chipset configuration space */
> pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
>
> @@ -121,14 +115,30 @@ static int ich9_smb_initfn(PCIDevice *d)
> /* TODO smb_io_base */
> pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
> /* TODO bar0, bar1: 64bit BAR support*/
> - pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR,
> - ICH9_SMB_SMB_BASE_SIZE, PCI_BASE_ADDRESS_SPACE_IO,
> - &ich9_smb_map_ioport);
>
> + memory_region_init_io(&s->mem_bar, &lpc_smb_mmio_ops, s, "ich9-smbus-bar",
> + ICH9_SMB_SMB_BASE_SIZE);
> + pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
> + &s->mem_bar);
> pm_smbus_init(&d->qdev, &s->smb);
> return 0;
> }
>
> +static void ich9_smb_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
> +
> + k->vendor_id = PCI_VENDOR_ID_INTEL;
> + k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6;
> + k->revision = ICH9_A2_SMB_REVISION;
> + k->class_id = PCI_CLASS_SERIAL_SMBUS;
> + dc->no_user = 1;
> + dc->vmsd = &vmstate_ich9_smbus;
> + dc->desc = "ICH9 SMBUS Bridge";
> + k->init = ich9_smbus_initfn;
> +}
> +
> i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
> {
> PCIDevice *d =
> @@ -137,18 +147,16 @@ i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
> return s->smb.smbus;
> }
>
> -static PCIDeviceInfo ich9_smb_info = {
> - .qdev.name = "ICH9 SMB",
> - .qdev.desc = "ICH9 SMBUS Bridge",
> - .qdev.size = sizeof(ICH9_SMBState),
> - .qdev.vmsd = &vmstate_ich9_smbus,
> - .qdev.no_user = 1,
> - .init = ich9_smb_initfn,
> +static TypeInfo ich9_smb_info = {
'const'
> + .name = "ICH9 SMB",
> + .parent = TYPE_PCI_DEVICE,
> + .instance_size = sizeof(ICH9_SMBState),
> + .class_init = ich9_smb_class_init,
> };
>
> static void ich9_smb_register(void)
> {
> - pci_qdev_register(&ich9_smb_info);
> + type_register_static(&ich9_smb_info);
> }
>
> -device_init(ich9_smb_register);
> +type_init(ich9_smb_register);
> --
> 1.7.1
>
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 24/25] Add a fallback bios file search, if -L fails.
2012-09-13 20:12 ` [Qemu-devel] [PATCH 24/25] Add a fallback bios file search, if -L fails Jason Baron
2012-09-14 7:09 ` Paolo Bonzini
2012-09-14 10:54 ` Peter Maydell
@ 2012-09-14 19:15 ` Blue Swirl
2 siblings, 0 replies; 74+ messages in thread
From: Blue Swirl @ 2012-09-14 19:15 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On Thu, Sep 13, 2012 at 8:12 PM, Jason Baron <jbaron@redhat.com> wrote:
> If -L <dir> is specified, and qemu does not find the bios file in <dir>, then
> the search fails. Add infrastructure such that the search will continue in
> the default paths, if not found in the -L path.
>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> vl.c | 28 +++++++++++++++++++++-------
> 1 files changed, 21 insertions(+), 7 deletions(-)
>
> diff --git a/vl.c b/vl.c
> index 7c577fa..656a210 100644
> --- a/vl.c
> +++ b/vl.c
> @@ -177,6 +177,7 @@ int main(int argc, char **argv)
> #define MAX_VIRTIO_CONSOLES 1
>
> static const char *data_dir;
> +static const char *data_dir_fallback;
> const char *bios_name = NULL;
> enum vga_retrace_method vga_retrace_method = VGA_RETRACE_DUMB;
> DisplayType display_type = DT_DEFAULT;
> @@ -1872,12 +1873,15 @@ static int balloon_parse(const char *arg)
> return -1;
> }
>
> -char *qemu_find_file(int type, const char *name)
> +static char *__qemu_find_file(int type, const char *name, const char *dir)
> {
> int len;
> const char *subdir;
> char *buf;
>
> + if (!dir)
> + return NULL;
Missing braces.
> +
> /* Try the name as a straight path first */
> if (access(name, R_OK) == 0) {
> return g_strdup(name);
> @@ -1892,9 +1896,9 @@ char *qemu_find_file(int type, const char *name)
> default:
> abort();
> }
> - len = strlen(data_dir) + strlen(name) + strlen(subdir) + 2;
> + len = strlen(dir) + strlen(name) + strlen(subdir) + 2;
> buf = g_malloc0(len);
> - snprintf(buf, len, "%s/%s%s", data_dir, subdir, name);
> + snprintf(buf, len, "%s/%s%s", dir, subdir, name);
> if (access(buf, R_OK)) {
> g_free(buf);
> return NULL;
> @@ -1902,6 +1906,18 @@ char *qemu_find_file(int type, const char *name)
> return buf;
> }
>
> +char *qemu_find_file(int type, const char *name)
> +{
> + char *filename;
> +
> + filename = __qemu_find_file(type, name, data_dir);
> + if (!filename) {
> + filename = __qemu_find_file(type, name, data_dir_fallback);
> + }
> +
> + return filename;
> +}
> +
> static int device_help_func(QemuOpts *opts, void *opaque)
> {
> return qdev_device_help(opts);
> @@ -3338,11 +3354,9 @@ int main(int argc, char **argv, char **envp)
>
> /* If no data_dir is specified then try to find it relative to the
> executable path. */
> - if (!data_dir) {
> - data_dir = os_find_datadir(argv[0]);
> - }
> + data_dir_fallback = os_find_datadir(argv[0]);
> /* If all else fails use the install path specified when building. */
> - if (!data_dir) {
> + if (!data_dir_fallback) {
> data_dir = CONFIG_QEMU_DATADIR;
> }
>
> --
> 1.7.1
>
>
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
2012-09-14 19:01 ` Jason Baron
@ 2012-09-15 0:24 ` Isaku Yamahata
2012-09-15 11:33 ` Paolo Bonzini
2012-09-15 18:05 ` Michael S. Tsirkin
2012-09-15 17:40 ` Michael S. Tsirkin
1 sibling, 2 replies; 74+ messages in thread
From: Isaku Yamahata @ 2012-09-15 0:24 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On Fri, Sep 14, 2012 at 03:01:55PM -0400, Jason Baron wrote:
> On Sat, Sep 15, 2012 at 02:34:18AM +0900, Isaku Yamahata wrote:
> > On Fri, Sep 14, 2012 at 11:23:29AM -0400, Jason Baron wrote:
> > > On Sat, Sep 15, 2012 at 12:14:01AM +0900, Isaku Yamahata wrote:
> > > > On Thu, Sep 13, 2012 at 04:12:34PM -0400, Jason Baron wrote:
> > > > > 2) hotplug
> > > > > I've added piix acpi style hotplug to ich9.
> > > >
> > > > What's the point of this?
> > > > Its design is ad-hoc and shpc/pcie hotplug are available.
> > >
> > > The point was to get to feature parity with piix. I'm not sure how hard
> > > pcie hotplug is to implement really. I was thinking that we could
> > > replace the piix hotplug style with pcie hotplug, once that was
> > > implemented...
> >
> > shpc/pcie hotplug emulators are already available in qemu.
> > hw/shpc.c, hw/pcie.c and hw/xio3130_downstream.c.
> >
> > thanks,
> > --
> > yamahata
> >
>
> ok, yes pcie hotplug seems to work :) I guess I got confused b/c I
> thought devices would show up on the host bus. So the host bus in q35
> simply doesn't support hotplug?
No, it doesn't.
> Also, the way I'm doing hotplug is by specifying a 'bus=pcie.n' param.
> Without the 'bus=pcie.n' param, i get:
>
> Bus 'pcie.0' does not support hotplugging
>
> We probably then need to enhance 'device_add' to find a reasonable
> default bus for the device on hotplug?
Yes.
--
yamahata
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
2012-09-15 0:24 ` Isaku Yamahata
@ 2012-09-15 11:33 ` Paolo Bonzini
2012-09-15 17:35 ` Michael S. Tsirkin
2012-09-15 18:05 ` Michael S. Tsirkin
1 sibling, 1 reply; 74+ messages in thread
From: Paolo Bonzini @ 2012-09-15 11:33 UTC (permalink / raw)
To: Isaku Yamahata
Cc: aliguori, alex.williamson, mst, jan.kiszka, Jason Baron,
qemu-devel, agraf, juzhang, kevin, avi, mkletzan, lcapitulino,
afaerber, armbru
Il 15/09/2012 02:24, Isaku Yamahata ha scritto:
>> > ok, yes pcie hotplug seems to work :) I guess I got confused b/c I
>> > thought devices would show up on the host bus. So the host bus in q35
>> > simply doesn't support hotplug?
> No, it doesn't.
I think it makes sense then to keep ACPI hotplug on the host bus, for
backwards compatibility with PIIX4 guests, especially if the code is
written.
Paolo
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 10/25] pcie: Convert PCIExpressHost to use the QOM.
2012-09-13 20:12 ` [Qemu-devel] [PATCH 10/25] pcie: Convert PCIExpressHost to use the QOM Jason Baron
@ 2012-09-15 15:16 ` Andreas Färber
0 siblings, 0 replies; 74+ messages in thread
From: Andreas Färber @ 2012-09-15 15:16 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, armbru
Am 13.09.2012 22:12, schrieb Jason Baron:
> Let's use PCIExpressHost with QOM.
>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
Acked-by: Andreas Färber <afaerber@suse.de>
Andreas
--
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
2012-09-15 11:33 ` Paolo Bonzini
@ 2012-09-15 17:35 ` Michael S. Tsirkin
0 siblings, 0 replies; 74+ messages in thread
From: Michael S. Tsirkin @ 2012-09-15 17:35 UTC (permalink / raw)
To: Paolo Bonzini
Cc: aliguori, alex.williamson, jan.kiszka, Jason Baron, qemu-devel,
agraf, Isaku Yamahata, juzhang, kevin, avi, mkletzan, lcapitulino,
afaerber, armbru
On Sat, Sep 15, 2012 at 01:33:04PM +0200, Paolo Bonzini wrote:
> Il 15/09/2012 02:24, Isaku Yamahata ha scritto:
> >> > ok, yes pcie hotplug seems to work :) I guess I got confused b/c I
> >> > thought devices would show up on the host bus. So the host bus in q35
> >> > simply doesn't support hotplug?
> > No, it doesn't.
>
> I think it makes sense then to keep ACPI hotplug on the host bus, for
> backwards compatibility with PIIX4 guests, especially if the code is
> written.
>
> Paolo
I agree. I think ACPI hotplug support is a spec requirement anyway: if
you look at ACPI spec you will see that native hotplug support for guest
is optional.
--
MST
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
2012-09-14 19:01 ` Jason Baron
2012-09-15 0:24 ` Isaku Yamahata
@ 2012-09-15 17:40 ` Michael S. Tsirkin
1 sibling, 0 replies; 74+ messages in thread
From: Michael S. Tsirkin @ 2012-09-15 17:40 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, jan.kiszka, qemu-devel, agraf, Isaku Yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On Fri, Sep 14, 2012 at 03:01:55PM -0400, Jason Baron wrote:
> On Sat, Sep 15, 2012 at 02:34:18AM +0900, Isaku Yamahata wrote:
> > On Fri, Sep 14, 2012 at 11:23:29AM -0400, Jason Baron wrote:
> > > On Sat, Sep 15, 2012 at 12:14:01AM +0900, Isaku Yamahata wrote:
> > > > On Thu, Sep 13, 2012 at 04:12:34PM -0400, Jason Baron wrote:
> > > > > 2) hotplug
> > > > > I've added piix acpi style hotplug to ich9.
> > > >
> > > > What's the point of this?
> > > > Its design is ad-hoc and shpc/pcie hotplug are available.
> > >
> > > The point was to get to feature parity with piix. I'm not sure how hard
> > > pcie hotplug is to implement really. I was thinking that we could
> > > replace the piix hotplug style with pcie hotplug, once that was
> > > implemented...
> >
> > shpc/pcie hotplug emulators are already available in qemu.
> > hw/shpc.c, hw/pcie.c and hw/xio3130_downstream.c.
> >
> > thanks,
> > --
> > yamahata
> >
>
> ok, yes pcie hotplug seems to work :) I guess I got confused b/c I
> thought devices would show up on the host bus. So the host bus in q35
> simply doesn't support hotplug?
>
> Also, the way I'm doing hotplug is by specifying a 'bus=pcie.n' param.
> Without the 'bus=pcie.n' param, i get:
>
> Bus 'pcie.0' does not support hotplugging
>
> We probably then need to enhance 'device_add' to find a reasonable
> default bus for the device on hotplug?
>
> Thanks,
>
> -Jason
Maybe though I am not too worried: hotplug is an advanced enough
feature.
We will also still need a PCI bus in the system so that legacy PCI
devices such as virtio can be added. And that bus needs ACPI for
hotplug.
--
MST
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
2012-09-14 15:14 ` Isaku Yamahata
2012-09-14 15:23 ` Jason Baron
@ 2012-09-15 18:02 ` Michael S. Tsirkin
1 sibling, 0 replies; 74+ messages in thread
From: Michael S. Tsirkin @ 2012-09-15 18:02 UTC (permalink / raw)
To: Isaku Yamahata
Cc: aliguori, alex.williamson, jan.kiszka, Jason Baron, qemu-devel,
agraf, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On Sat, Sep 15, 2012 at 12:14:01AM +0900, Isaku Yamahata wrote:
> On Thu, Sep 13, 2012 at 04:12:34PM -0400, Jason Baron wrote:
> > 2) hotplug
> > I've added piix acpi style hotplug to ich9.
>
> What's the point of this?
> Its design is ad-hoc and shpc/pcie hotplug are available.
We have a pci bridge with shpc support, but not host support. In any
case, windows guests do not support shpc for PCI, and we need ability to
mix in PCI buses with hotplug support so we can use PCI devices.
> --
> yamahata
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 00/25] q35 series take #1
2012-09-15 0:24 ` Isaku Yamahata
2012-09-15 11:33 ` Paolo Bonzini
@ 2012-09-15 18:05 ` Michael S. Tsirkin
1 sibling, 0 replies; 74+ messages in thread
From: Michael S. Tsirkin @ 2012-09-15 18:05 UTC (permalink / raw)
To: Isaku Yamahata
Cc: aliguori, juzhang, jan.kiszka, Jason Baron, agraf, qemu-devel,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On Sat, Sep 15, 2012 at 09:24:51AM +0900, Isaku Yamahata wrote:
> On Fri, Sep 14, 2012 at 03:01:55PM -0400, Jason Baron wrote:
> > On Sat, Sep 15, 2012 at 02:34:18AM +0900, Isaku Yamahata wrote:
> > > On Fri, Sep 14, 2012 at 11:23:29AM -0400, Jason Baron wrote:
> > > > On Sat, Sep 15, 2012 at 12:14:01AM +0900, Isaku Yamahata wrote:
> > > > > On Thu, Sep 13, 2012 at 04:12:34PM -0400, Jason Baron wrote:
> > > > > > 2) hotplug
> > > > > > I've added piix acpi style hotplug to ich9.
> > > > >
> > > > > What's the point of this?
> > > > > Its design is ad-hoc and shpc/pcie hotplug are available.
> > > >
> > > > The point was to get to feature parity with piix. I'm not sure how hard
> > > > pcie hotplug is to implement really. I was thinking that we could
> > > > replace the piix hotplug style with pcie hotplug, once that was
> > > > implemented...
> > >
> > > shpc/pcie hotplug emulators are already available in qemu.
> > > hw/shpc.c, hw/pcie.c and hw/xio3130_downstream.c.
> > >
> > > thanks,
> > > --
> > > yamahata
> > >
> >
> > ok, yes pcie hotplug seems to work :) I guess I got confused b/c I
> > thought devices would show up on the host bus. So the host bus in q35
> > simply doesn't support hotplug?
>
> No, it doesn't.
>
>
> > Also, the way I'm doing hotplug is by specifying a 'bus=pcie.n' param.
> > Without the 'bus=pcie.n' param, i get:
> >
> > Bus 'pcie.0' does not support hotplugging
> >
> > We probably then need to enhance 'device_add' to find a reasonable
> > default bus for the device on hotplug?
>
> Yes.
By the way I would tread carefully before switching on
native hotplug support unconditionally in the BIOS.
For example, it has an
annoying two-second delay after device is added
and before it is used built into the spec that
might interfere with some uses.
As a minimum we might want to give users the ability to disable BIOS
native hotplug support.
> --
> yamahata
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator
2012-09-13 20:12 ` [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator Jason Baron
` (2 preceding siblings ...)
2012-09-14 12:26 ` Michael S. Tsirkin
@ 2012-09-15 18:14 ` Michael S. Tsirkin
2012-09-16 14:48 ` Anthony Liguori
3 siblings, 1 reply; 74+ messages in thread
From: Michael S. Tsirkin @ 2012-09-15 18:14 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, alex.williamson, jan.kiszka, qemu-devel, agraf,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On Thu, Sep 13, 2012 at 04:12:42PM -0400, Jason Baron wrote:
> diff --git a/hw/pc_q35.c b/hw/pc_q35.c
> new file mode 100644
> index 0000000..4f75d97
> --- /dev/null
> +++ b/hw/pc_q35.c
> @@ -0,0 +1,378 @@
> +/*
> + * QEMU PC System Emulator
> + *
> + * Copyright (c) 2003-2004 Fabrice Bellard
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +/*
> + * Q35 chipset based pc system emulator
> + *
> + * Copyright (c) 2009, 2010
> + * Isaku Yamahata <yamahata at valinux co jp>
> + * VA Linux Systems Japan K.K.
> + *
> + * This is based on pc.c, but heavily modified.
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>
> + */
> +#include "hw.h"
> +#include "arch_init.h"
> +#include "pc.h"
> +#include "fdc.h"
> +#include "pci.h"
> +#include "pci_bridge.h"
> +#include "pci_p2pbr.h"
> +#include "ioh3420.h"
> +#include "xio3130_upstream.h"
> +#include "xio3130_downstream.h"
> +#include "block.h"
> +#include "blockdev.h"
> +#include "sysemu.h"
> +#include "audio/audio.h"
> +#include "net.h"
> +#include "smbus.h"
> +#include "boards.h"
> +#include "monitor.h"
> +#include "fw_cfg.h"
> +#include "hpet_emul.h"
> +#include "watchdog.h"
> +#include "smbios.h"
> +#include "ide.h"
> +#include "usb-uhci.h"
> +
> +#include "q35.h"
> +
> +/* ICH9 AHCI has 6 ports */
> +#define MAX_SATA_PORTS 6
> +
> +#define I21154_REV 0x05
> +#define I21154_PI 0x00
> +
> +static PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
> + bool multifunction)
> +{
> + const PCIP2PBridgeInit init = {
> + .bus = bus,
> + .devfn = devfn,
> + .multifunction = multifunction,
> +
> + .bus_name = bus_name,
> + .map_irq = pci_swizzle_map_irq_fn,
> + };
> + const PCIP2PBridgeProp prop = {
> + .vendor_id = PCI_VENDOR_ID_DEC,
> + .device_id = PCI_DEVICE_ID_DEC_21154,
> + .revision_id = I21154_REV,
> + .prog_interface = I21154_PI,
> + };
> + return pci_p2pbr_create_simple(&init, &prop);
> +}
> +
> +static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
> +{
> + uint8_t dev;
> + uint8_t sec_bus;
> + uint8_t port = 0;
> + uint8_t chassis = 0;
> + uint16_t slot = 0;
> + uint8_t upstream_port;
> + PCIESlot *s;
> + uint8_t fn;
> + PCIESlot *root_port;
> + PCIBus *root_port_bus;
> + char buf[16];
> +
> + /* PCI to PCI bridge b6:d[29 - 31]:f0, 6:[1c - 1f].0 with subordinate bus
> + of 7 - 9 on b0:d30:f0, 0.1e.0 = bus */
> +#define Q35_P2P_BRDIGE_DEV_BASE 28
> +#define Q35_P2P_BRDIGE_DEV_MAX 32
> +#define Q35_P2P_BRDIGE_SUBBUS_BASE (ICH9_D2P_SECONDARY_DEFAULT + 1)
> + for (dev = Q35_P2P_BRDIGE_DEV_BASE; dev < Q35_P2P_BRDIGE_DEV_MAX; dev++) {
> + PCIBridge *br;
> + sec_bus = Q35_P2P_BRDIGE_SUBBUS_BASE + dev - Q35_P2P_BRDIGE_DEV_BASE;
> +
> + snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
> + br = i21154_init(pci_bus, PCI_DEVFN(dev, 0), buf, true);
> + }
> +
> + /* PCIe root port b0:d1:f0 in GMCH.
> + * Actually it's vid/did = 0x8086:0x29c1, but we substitute ioh for it.
> + */
> + sec_bus = 32;
> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
> + s = ioh3420_init(host_bus, PCI_DEVFN(GMCH_PCIE_DEV, GMCH_PCIE_FUNC), true,
> + buf, pci_swizzle_map_irq_fn, port, chassis, slot);
> +
> +
> + /* more slots. ICH9 doesn't have those, but many slots are wanted. */
> +//#define Q35_MANY_SLOTS
> +#undef Q35_MANY_SLOTS
> +
> +#ifdef Q35_MANY_SLOTS
> +#define Q35_NR_ROOTPORT 6
> +#define Q35_NR_UPSTREAM 8
> +#define Q35_NR_DOWNSTREAM 16
> +#else
> +#define Q35_NR_ROOTPORT 1
> +#define Q35_NR_UPSTREAM 1
> +#define Q35_NR_DOWNSTREAM 1
> +#endif
> +
> + /* PCIe root port b0:d23:f[0-5], 0.17.[0-5] */
> + for (fn = 0; fn < Q35_NR_ROOTPORT; fn++) {
> + sec_bus++;
> + port++;
> + slot++;
> +
> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
> + s = ioh3420_init(host_bus, PCI_DEVFN(23, fn), true,
> + buf, pci_swizzle_map_irq_fn, port, chassis, slot);
> + }
> +
> + /* PCIe root port b0:d24:f0 */
> + sec_bus++;
> + port++;
> + slot++;
> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
> + root_port = ioh3420_init(host_bus, PCI_DEVFN(24, 0), true,
> + buf, pci_swizzle_map_irq_fn, port, chassis, slot);
> + root_port_bus = pci_bridge_get_sec_bus(&root_port->port.br);
> +
> + /* 8 * 16 = 128 slots */
> + upstream_port = 0;
> + for (fn = 0; fn < Q35_NR_UPSTREAM; fn++) {
> + PCIEPort *upstream;
> + PCIBus *upstream_bus;
> + uint16_t downstream_port;
> +
> + uint8_t ds_dev_max;
> + uint8_t ds_dev;
> + uint8_t ds_fn_max;
> + uint8_t ds_fn;
> +
> + /* PCIe upstream port d0:f[0-7] */
> + sec_bus++;
> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
> + upstream = xio3130_upstream_init(root_port_bus, PCI_DEVFN(0, fn),
> + true, buf, pci_swizzle_map_irq_fn,
> + upstream_port);
> +
> + upstream_bus = pci_bridge_get_sec_bus(&upstream->br);
> + upstream_port++;
> +
> + /* PCIe downstream port */
> + downstream_port = 0;
> + ds_fn_max = MIN(Q35_NR_DOWNSTREAM / PCI_SLOT_MAX, PCI_FUNC_MAX);
> + ds_dev_max = MIN(Q35_NR_DOWNSTREAM / (ds_fn_max + 1), PCI_SLOT_MAX);
> +
> + for (ds_dev = 0; ds_dev <= ds_dev_max &&
> + downstream_port < Q35_NR_DOWNSTREAM; ds_dev++) {
> + for (ds_fn = 0; ds_fn <= ds_fn_max &&
> + downstream_port < Q35_NR_DOWNSTREAM; ds_fn++) {
> + sec_bus++;
> + slot++;
> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
> +
> + xio3130_downstream_init(upstream_bus, PCI_DEVFN(ds_dev, ds_fn),
> + true, buf, pci_swizzle_map_irq_fn,
> + downstream_port, chassis, slot);
> + downstream_port++;
> + }
> + }
> + }
> +
> + /* PCIe root port b0:d28:f[0-6] in ICH9.
> + * Actually it's vid/did = 0x8086:0x294[02468A], but we substitute ioh
> + * for them.
> + */
> + for (fn = 0; fn < ICH9_PCIE_FUNC_MAX; fn++) {
> + sec_bus++;
> + port++;
> + slot++;
> +
> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
> + s = ioh3420_init(host_bus, PCI_DEVFN(ICH9_PCIE_DEV, fn), true,
> + buf, pci_swizzle_map_irq_fn,
> + port, chassis, slot);
> + }
> +}
> +
> +static void pc_q35_init_early(qemu_irq *isa_irq, IsaIrqState *isa_irq_state,
> + DeviceState **gmch_host_p,
> + PCIBus **host_bus_p, PCIBus **pci_bus_p,
> + PCIDevice **lpc_p)
> +{
> + DeviceState *gmch_host;
> + PCIBus *host_bus;
> + PCIBus *pci_bus;
> +
> + PCIDevice *gmch_state;
> + PCIDevice *lpc;
> +
> + /* create pci host bus */
> + host_bus = gmch_host_init(&gmch_host, isa_irq, isa_irq_state->ioapic);
> + gmch_state = gmch_init(gmch_host, host_bus);
> +
> + /* create conventional pci bus: pcie2pci bridge */
> + pci_bus = ich9_d2pbr_init(host_bus, PCI_DEVFN(ICH9_D2P_BRIDGE_DEV,
> + ICH9_D2P_BRIDGE_FUNC),
> + ICH9_D2P_SECONDARY_DEFAULT);
> +
> + /* create child pci/pcie buses */
> + pc_q35_bridge_init(host_bus, pci_bus);
> +
> + /* create ISA bus */
> + lpc = gmch_lpc_init(gmch_host, host_bus);
> +
> + *gmch_host_p = gmch_host;
> + *host_bus_p = host_bus;
> + *pci_bus_p = pci_bus;
> + *lpc_p = lpc;
> +}
> +
> +static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,
> + DeviceState *gmch_host,
> + PCIBus *host_bus, PCIBus *pci_bus,
> + PCIDevice *lpc)
> +{
> + qemu_irq *cmos_s3;
> + PCIDevice *ahci;
> + DriveInfo *hd[MAX_SATA_PORTS * MAX_IDE_DEVS];
> +
> + /* connect pm stuff to lpc */
> + cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
> + ich9_lpc_pm_init(gmch_host, lpc, *cmos_s3);
> +
> + /* ahci and SATA device */
> + ide_drive_get(hd, MAX_SATA_PORTS);
> + ahci = pci_create_simple_multifunction(host_bus,
> + PCI_DEVFN(ICH9_SATA1_DEV,
> + ICH9_SATA1_FUNC),
> + true, "ich9-ahci");
> + pci_ahci_ide_create_devs(ahci, hd);
> + idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
> + idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
> +
> + if (usb_enabled) {
> + /* Should we create 6 UHCI according to ich9 spec? */
> + pci_create_simple_multifunction(
> + host_bus, PCI_DEVFN(ICH9_USB_UHCI1_DEV, ICH9_USB_UHCI1_FUNC),
> + true, "ich9-usb-uhci1");
> + /* XXX: EHCI */
> + }
> +
> + /* TODO: Populate SPD eeprom data. */
> + smbus_eeprom_init(ich9_smb_init(host_bus,
> + PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
> + 0xb100),
> + 8, NULL, 0);
> +}
> +
> +/* PC hardware initialisation */
> +static void pc_q35_init(ram_addr_t ram_size,
> + const char *boot_device,
> + const char *kernel_filename,
> + const char *kernel_cmdline,
> + const char *initrd_filename,
> + const char *cpu_model)
> +{
> + ram_addr_t below_4g_mem_size, above_4g_mem_size;
> + DeviceState *gmch_host;
> + PCIBus *host_bus;
> + PCIBus *pci_bus;
> + PCIDevice *lpc;
> + qemu_irq *isa_irq;
> + IsaIrqState *isa_irq_state;
> + BusState *idebus[MAX_SATA_PORTS];
> + ISADevice *rtc_state;
> + MemoryRegion *pci_memory;
> + MemoryRegion *rom_memory;
> + MemoryRegion *ram_memory;
> +
> + pc_cpus_init(cpu_model);
> +
> + /* FIXME: add kvm clock ? */
> +
> + if (ram_size >= 0xe0000000) {
> + above_4g_mem_size = ram_size - 0xe0000000;
> + below_4g_mem_size = 0xe0000000;
> + } else {
> + above_4g_mem_size = 0;
> + below_4g_mem_size = ram_size;
> + }
> +
> + /* pci enabled */
> + pci_memory = g_new(MemoryRegion, 1);
> + memory_region_init(pci_memory, "pci", INT64_MAX);
> + rom_memory = pci_memory;
> +
> + /* allocate ram and load rom/bios */
> + pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
> + initrd_filename, below_4g_mem_size, above_4g_mem_size,
> + rom_memory, &ram_memory);
> +
> + /* irq lines */
> + isa_irq = pc_isa_irq(&isa_irq_state);
> + ioapic_init(isa_irq_state);
> +
> + pc_q35_init_early(isa_irq, isa_irq_state,
> + &gmch_host, &host_bus, &pci_bus, &lpc);
> + isa_bus_irqs(isa_irq);
> + pc_register_ferr_irq(isa_get_irq(13));
> +
> + /* init basic PC hardware */
> + pc_basic_device_init(isa_irq, &rtc_state, false);
> +
> + pc_q35_init_late(idebus, rtc_state, gmch_host, host_bus, pci_bus, lpc);
> +
> + pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
> + idebus[0], idebus[1], rtc_state);
> +
> + /* the rest devices to which pci devfn is automatically assigned */
> + pc_vga_init(host_bus);
> + audio_init(isa_irq, pci_bus);
> + pc_nic_init(pci_bus);
> + pc_pci_device_init(pci_bus);
> +}
> +
> +static QEMUMachine pc_q35_machine = {
> + .name = "pc_q35",
> + .desc = "Q35 chipset PC",
> + .init = pc_q35_init,
> + .max_cpus = 255,
> +};
> +
> +static void pc_q35_machine_init(void)
> +{
> + qemu_register_machine(&pc_q35_machine);
> +}
> +
> +machine_init(pc_q35_machine_init);
I wonder if it's possible for q35 to have no devices
at all in the default machine and have it
fully qualified by -device switches?
I envision -M qemu-1.3 switch that does exactly that,
so that machine type only handles things like
cross version compatibility.
--
MST
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator
2012-09-15 18:14 ` Michael S. Tsirkin
@ 2012-09-16 14:48 ` Anthony Liguori
2012-09-16 15:14 ` Michael S. Tsirkin
0 siblings, 1 reply; 74+ messages in thread
From: Anthony Liguori @ 2012-09-16 14:48 UTC (permalink / raw)
To: Michael S. Tsirkin, Jason Baron
Cc: alex.williamson, jan.kiszka, qemu-devel, agraf, yamahata, juzhang,
kevin, avi, mkletzan, lcapitulino, afaerber, armbru
"Michael S. Tsirkin" <mst@redhat.com> writes:
> On Thu, Sep 13, 2012 at 04:12:42PM -0400, Jason Baron wrote:
>> diff --git a/hw/pc_q35.c b/hw/pc_q35.c
>> new file mode 100644
>> index 0000000..4f75d97
>> --- /dev/null
>> +++ b/hw/pc_q35.c
>> @@ -0,0 +1,378 @@
>> +/*
>> + * QEMU PC System Emulator
>> + *
>> + * Copyright (c) 2003-2004 Fabrice Bellard
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>> + * of this software and associated documentation files (the "Software"), to deal
>> + * in the Software without restriction, including without limitation the rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + */
>> +/*
>> + * Q35 chipset based pc system emulator
>> + *
>> + * Copyright (c) 2009, 2010
>> + * Isaku Yamahata <yamahata at valinux co jp>
>> + * VA Linux Systems Japan K.K.
>> + *
>> + * This is based on pc.c, but heavily modified.
>> + *
>> + * This library is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU Lesser General Public
>> + * License as published by the Free Software Foundation; either
>> + * version 2 of the License, or (at your option) any later version.
>> + *
>> + * This library is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
>> + * Lesser General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU Lesser General Public
>> + * License along with this library; if not, see <http://www.gnu.org/licenses/>
>> + */
>> +#include "hw.h"
>> +#include "arch_init.h"
>> +#include "pc.h"
>> +#include "fdc.h"
>> +#include "pci.h"
>> +#include "pci_bridge.h"
>> +#include "pci_p2pbr.h"
>> +#include "ioh3420.h"
>> +#include "xio3130_upstream.h"
>> +#include "xio3130_downstream.h"
>> +#include "block.h"
>> +#include "blockdev.h"
>> +#include "sysemu.h"
>> +#include "audio/audio.h"
>> +#include "net.h"
>> +#include "smbus.h"
>> +#include "boards.h"
>> +#include "monitor.h"
>> +#include "fw_cfg.h"
>> +#include "hpet_emul.h"
>> +#include "watchdog.h"
>> +#include "smbios.h"
>> +#include "ide.h"
>> +#include "usb-uhci.h"
>> +
>> +#include "q35.h"
>> +
>> +/* ICH9 AHCI has 6 ports */
>> +#define MAX_SATA_PORTS 6
>> +
>> +#define I21154_REV 0x05
>> +#define I21154_PI 0x00
>> +
>> +static PCIBridge *i21154_init(PCIBus *bus, int devfn, const char *bus_name,
>> + bool multifunction)
>> +{
>> + const PCIP2PBridgeInit init = {
>> + .bus = bus,
>> + .devfn = devfn,
>> + .multifunction = multifunction,
>> +
>> + .bus_name = bus_name,
>> + .map_irq = pci_swizzle_map_irq_fn,
>> + };
>> + const PCIP2PBridgeProp prop = {
>> + .vendor_id = PCI_VENDOR_ID_DEC,
>> + .device_id = PCI_DEVICE_ID_DEC_21154,
>> + .revision_id = I21154_REV,
>> + .prog_interface = I21154_PI,
>> + };
>> + return pci_p2pbr_create_simple(&init, &prop);
>> +}
>> +
>> +static void pc_q35_bridge_init(PCIBus *host_bus, PCIBus *pci_bus)
>> +{
>> + uint8_t dev;
>> + uint8_t sec_bus;
>> + uint8_t port = 0;
>> + uint8_t chassis = 0;
>> + uint16_t slot = 0;
>> + uint8_t upstream_port;
>> + PCIESlot *s;
>> + uint8_t fn;
>> + PCIESlot *root_port;
>> + PCIBus *root_port_bus;
>> + char buf[16];
>> +
>> + /* PCI to PCI bridge b6:d[29 - 31]:f0, 6:[1c - 1f].0 with subordinate bus
>> + of 7 - 9 on b0:d30:f0, 0.1e.0 = bus */
>> +#define Q35_P2P_BRDIGE_DEV_BASE 28
>> +#define Q35_P2P_BRDIGE_DEV_MAX 32
>> +#define Q35_P2P_BRDIGE_SUBBUS_BASE (ICH9_D2P_SECONDARY_DEFAULT + 1)
>> + for (dev = Q35_P2P_BRDIGE_DEV_BASE; dev < Q35_P2P_BRDIGE_DEV_MAX; dev++) {
>> + PCIBridge *br;
>> + sec_bus = Q35_P2P_BRDIGE_SUBBUS_BASE + dev - Q35_P2P_BRDIGE_DEV_BASE;
>> +
>> + snprintf(buf, sizeof(buf), "pci.%d", sec_bus);
>> + br = i21154_init(pci_bus, PCI_DEVFN(dev, 0), buf, true);
>> + }
>> +
>> + /* PCIe root port b0:d1:f0 in GMCH.
>> + * Actually it's vid/did = 0x8086:0x29c1, but we substitute ioh for it.
>> + */
>> + sec_bus = 32;
>> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
>> + s = ioh3420_init(host_bus, PCI_DEVFN(GMCH_PCIE_DEV, GMCH_PCIE_FUNC), true,
>> + buf, pci_swizzle_map_irq_fn, port, chassis, slot);
>> +
>> +
>> + /* more slots. ICH9 doesn't have those, but many slots are wanted. */
>> +//#define Q35_MANY_SLOTS
>> +#undef Q35_MANY_SLOTS
>> +
>> +#ifdef Q35_MANY_SLOTS
>> +#define Q35_NR_ROOTPORT 6
>> +#define Q35_NR_UPSTREAM 8
>> +#define Q35_NR_DOWNSTREAM 16
>> +#else
>> +#define Q35_NR_ROOTPORT 1
>> +#define Q35_NR_UPSTREAM 1
>> +#define Q35_NR_DOWNSTREAM 1
>> +#endif
>> +
>> + /* PCIe root port b0:d23:f[0-5], 0.17.[0-5] */
>> + for (fn = 0; fn < Q35_NR_ROOTPORT; fn++) {
>> + sec_bus++;
>> + port++;
>> + slot++;
>> +
>> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
>> + s = ioh3420_init(host_bus, PCI_DEVFN(23, fn), true,
>> + buf, pci_swizzle_map_irq_fn, port, chassis, slot);
>> + }
>> +
>> + /* PCIe root port b0:d24:f0 */
>> + sec_bus++;
>> + port++;
>> + slot++;
>> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
>> + root_port = ioh3420_init(host_bus, PCI_DEVFN(24, 0), true,
>> + buf, pci_swizzle_map_irq_fn, port, chassis, slot);
>> + root_port_bus = pci_bridge_get_sec_bus(&root_port->port.br);
>> +
>> + /* 8 * 16 = 128 slots */
>> + upstream_port = 0;
>> + for (fn = 0; fn < Q35_NR_UPSTREAM; fn++) {
>> + PCIEPort *upstream;
>> + PCIBus *upstream_bus;
>> + uint16_t downstream_port;
>> +
>> + uint8_t ds_dev_max;
>> + uint8_t ds_dev;
>> + uint8_t ds_fn_max;
>> + uint8_t ds_fn;
>> +
>> + /* PCIe upstream port d0:f[0-7] */
>> + sec_bus++;
>> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
>> + upstream = xio3130_upstream_init(root_port_bus, PCI_DEVFN(0, fn),
>> + true, buf, pci_swizzle_map_irq_fn,
>> + upstream_port);
>> +
>> + upstream_bus = pci_bridge_get_sec_bus(&upstream->br);
>> + upstream_port++;
>> +
>> + /* PCIe downstream port */
>> + downstream_port = 0;
>> + ds_fn_max = MIN(Q35_NR_DOWNSTREAM / PCI_SLOT_MAX, PCI_FUNC_MAX);
>> + ds_dev_max = MIN(Q35_NR_DOWNSTREAM / (ds_fn_max + 1), PCI_SLOT_MAX);
>> +
>> + for (ds_dev = 0; ds_dev <= ds_dev_max &&
>> + downstream_port < Q35_NR_DOWNSTREAM; ds_dev++) {
>> + for (ds_fn = 0; ds_fn <= ds_fn_max &&
>> + downstream_port < Q35_NR_DOWNSTREAM; ds_fn++) {
>> + sec_bus++;
>> + slot++;
>> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
>> +
>> + xio3130_downstream_init(upstream_bus, PCI_DEVFN(ds_dev, ds_fn),
>> + true, buf, pci_swizzle_map_irq_fn,
>> + downstream_port, chassis, slot);
>> + downstream_port++;
>> + }
>> + }
>> + }
>> +
>> + /* PCIe root port b0:d28:f[0-6] in ICH9.
>> + * Actually it's vid/did = 0x8086:0x294[02468A], but we substitute ioh
>> + * for them.
>> + */
>> + for (fn = 0; fn < ICH9_PCIE_FUNC_MAX; fn++) {
>> + sec_bus++;
>> + port++;
>> + slot++;
>> +
>> + snprintf(buf, sizeof(buf), "pcie.%d", sec_bus);
>> + s = ioh3420_init(host_bus, PCI_DEVFN(ICH9_PCIE_DEV, fn), true,
>> + buf, pci_swizzle_map_irq_fn,
>> + port, chassis, slot);
>> + }
>> +}
>> +
>> +static void pc_q35_init_early(qemu_irq *isa_irq, IsaIrqState *isa_irq_state,
>> + DeviceState **gmch_host_p,
>> + PCIBus **host_bus_p, PCIBus **pci_bus_p,
>> + PCIDevice **lpc_p)
>> +{
>> + DeviceState *gmch_host;
>> + PCIBus *host_bus;
>> + PCIBus *pci_bus;
>> +
>> + PCIDevice *gmch_state;
>> + PCIDevice *lpc;
>> +
>> + /* create pci host bus */
>> + host_bus = gmch_host_init(&gmch_host, isa_irq, isa_irq_state->ioapic);
>> + gmch_state = gmch_init(gmch_host, host_bus);
>> +
>> + /* create conventional pci bus: pcie2pci bridge */
>> + pci_bus = ich9_d2pbr_init(host_bus, PCI_DEVFN(ICH9_D2P_BRIDGE_DEV,
>> + ICH9_D2P_BRIDGE_FUNC),
>> + ICH9_D2P_SECONDARY_DEFAULT);
>> +
>> + /* create child pci/pcie buses */
>> + pc_q35_bridge_init(host_bus, pci_bus);
>> +
>> + /* create ISA bus */
>> + lpc = gmch_lpc_init(gmch_host, host_bus);
>> +
>> + *gmch_host_p = gmch_host;
>> + *host_bus_p = host_bus;
>> + *pci_bus_p = pci_bus;
>> + *lpc_p = lpc;
>> +}
>> +
>> +static void pc_q35_init_late(BusState **idebus, ISADevice *rtc_state,
>> + DeviceState *gmch_host,
>> + PCIBus *host_bus, PCIBus *pci_bus,
>> + PCIDevice *lpc)
>> +{
>> + qemu_irq *cmos_s3;
>> + PCIDevice *ahci;
>> + DriveInfo *hd[MAX_SATA_PORTS * MAX_IDE_DEVS];
>> +
>> + /* connect pm stuff to lpc */
>> + cmos_s3 = qemu_allocate_irqs(pc_cmos_set_s3_resume, rtc_state, 1);
>> + ich9_lpc_pm_init(gmch_host, lpc, *cmos_s3);
>> +
>> + /* ahci and SATA device */
>> + ide_drive_get(hd, MAX_SATA_PORTS);
>> + ahci = pci_create_simple_multifunction(host_bus,
>> + PCI_DEVFN(ICH9_SATA1_DEV,
>> + ICH9_SATA1_FUNC),
>> + true, "ich9-ahci");
>> + pci_ahci_ide_create_devs(ahci, hd);
>> + idebus[0] = qdev_get_child_bus(&ahci->qdev, "ide.0");
>> + idebus[1] = qdev_get_child_bus(&ahci->qdev, "ide.1");
>> +
>> + if (usb_enabled) {
>> + /* Should we create 6 UHCI according to ich9 spec? */
>> + pci_create_simple_multifunction(
>> + host_bus, PCI_DEVFN(ICH9_USB_UHCI1_DEV, ICH9_USB_UHCI1_FUNC),
>> + true, "ich9-usb-uhci1");
>> + /* XXX: EHCI */
>> + }
>> +
>> + /* TODO: Populate SPD eeprom data. */
>> + smbus_eeprom_init(ich9_smb_init(host_bus,
>> + PCI_DEVFN(ICH9_SMB_DEV, ICH9_SMB_FUNC),
>> + 0xb100),
>> + 8, NULL, 0);
>> +}
>> +
>> +/* PC hardware initialisation */
>> +static void pc_q35_init(ram_addr_t ram_size,
>> + const char *boot_device,
>> + const char *kernel_filename,
>> + const char *kernel_cmdline,
>> + const char *initrd_filename,
>> + const char *cpu_model)
>> +{
>> + ram_addr_t below_4g_mem_size, above_4g_mem_size;
>> + DeviceState *gmch_host;
>> + PCIBus *host_bus;
>> + PCIBus *pci_bus;
>> + PCIDevice *lpc;
>> + qemu_irq *isa_irq;
>> + IsaIrqState *isa_irq_state;
>> + BusState *idebus[MAX_SATA_PORTS];
>> + ISADevice *rtc_state;
>> + MemoryRegion *pci_memory;
>> + MemoryRegion *rom_memory;
>> + MemoryRegion *ram_memory;
>> +
>> + pc_cpus_init(cpu_model);
>> +
>> + /* FIXME: add kvm clock ? */
>> +
>> + if (ram_size >= 0xe0000000) {
>> + above_4g_mem_size = ram_size - 0xe0000000;
>> + below_4g_mem_size = 0xe0000000;
>> + } else {
>> + above_4g_mem_size = 0;
>> + below_4g_mem_size = ram_size;
>> + }
>> +
>> + /* pci enabled */
>> + pci_memory = g_new(MemoryRegion, 1);
>> + memory_region_init(pci_memory, "pci", INT64_MAX);
>> + rom_memory = pci_memory;
>> +
>> + /* allocate ram and load rom/bios */
>> + pc_memory_init(get_system_memory(), kernel_filename, kernel_cmdline,
>> + initrd_filename, below_4g_mem_size, above_4g_mem_size,
>> + rom_memory, &ram_memory);
>> +
>> + /* irq lines */
>> + isa_irq = pc_isa_irq(&isa_irq_state);
>> + ioapic_init(isa_irq_state);
>> +
>> + pc_q35_init_early(isa_irq, isa_irq_state,
>> + &gmch_host, &host_bus, &pci_bus, &lpc);
>> + isa_bus_irqs(isa_irq);
>> + pc_register_ferr_irq(isa_get_irq(13));
>> +
>> + /* init basic PC hardware */
>> + pc_basic_device_init(isa_irq, &rtc_state, false);
>> +
>> + pc_q35_init_late(idebus, rtc_state, gmch_host, host_bus, pci_bus, lpc);
>> +
>> + pc_cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device,
>> + idebus[0], idebus[1], rtc_state);
>> +
>> + /* the rest devices to which pci devfn is automatically assigned */
>> + pc_vga_init(host_bus);
>> + audio_init(isa_irq, pci_bus);
>> + pc_nic_init(pci_bus);
>> + pc_pci_device_init(pci_bus);
>> +}
>> +
>> +static QEMUMachine pc_q35_machine = {
>> + .name = "pc_q35",
>> + .desc = "Q35 chipset PC",
>> + .init = pc_q35_init,
>> + .max_cpus = 255,
>> +};
>> +
>> +static void pc_q35_machine_init(void)
>> +{
>> + qemu_register_machine(&pc_q35_machine);
>> +}
>> +
>> +machine_init(pc_q35_machine_init);
>
> I wonder if it's possible for q35 to have no devices
> at all in the default machine and have it
> fully qualified by -device switches?
>
> I envision -M qemu-1.3 switch that does exactly that,
> so that machine type only handles things like
> cross version compatibility.
It's more than just "no devices". It's a matter of proper modeling of
the chipset, the super I/O chip, and peripherals.
Regards,
Anthony Liguori
>
> --
> MST
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator
2012-09-16 14:48 ` Anthony Liguori
@ 2012-09-16 15:14 ` Michael S. Tsirkin
0 siblings, 0 replies; 74+ messages in thread
From: Michael S. Tsirkin @ 2012-09-16 15:14 UTC (permalink / raw)
To: Anthony Liguori
Cc: alex.williamson, jan.kiszka, Jason Baron, qemu-devel, agraf,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On Sun, Sep 16, 2012 at 09:48:25AM -0500, Anthony Liguori wrote:
> > I wonder if it's possible for q35 to have no devices
> > at all in the default machine and have it
> > fully qualified by -device switches?
> >
> > I envision -M qemu-1.3 switch that does exactly that,
> > so that machine type only handles things like
> > cross version compatibility.
>
> It's more than just "no devices". It's a matter of proper modeling of
> the chipset, the super I/O chip, and peripherals.
OK I guess the answer us no then.
However, if you look at hw/pc_piix.c you see a bunch of version
compatiblity code. Other systems do not have this I guess
mostly because they worry less about compatibility ATM.
Looks like if we start bothering about compatibility
for both q35 and piix we'll have a lot of
code duplication between the two.
This problem is not limited to pc though,
I expect it with time we'll have it for power and arm.
I wonder what the solution is. Move compat
code out of pc_piix, making it non pc specific?
--
MST
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator
2012-09-14 7:37 ` Gerd Hoffmann
2012-09-14 14:11 ` Jason Baron
@ 2012-09-18 21:28 ` Alex Williamson
1 sibling, 0 replies; 74+ messages in thread
From: Alex Williamson @ 2012-09-18 21:28 UTC (permalink / raw)
To: Gerd Hoffmann
Cc: aliguori, mst, jan.kiszka, Jason Baron, qemu-devel, agraf,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber,
armbru
On Fri, 2012-09-14 at 09:37 +0200, Gerd Hoffmann wrote:
> On 09/13/12 22:12, Jason Baron wrote:
> > + if (ram_size >= 0xe0000000) {
> > + above_4g_mem_size = ram_size - 0xe0000000;
> > + below_4g_mem_size = 0xe0000000;
>
> We should make the hole larger to get more pci i/o address space below
> 4G, especially as q35 needs a good chunk of it for mmconfig.
>
> I think at least 0xc0000000, maybe even 0xb0000000. The later would
> allow to place mmconfig @ 0xb0000000, one big 512MB pci bar @ 0xc0000000
> (think gfx card pass-through) and all the remaining little stuff above
> 0xe0000000.
We also seem to be missing logic in seabios to avoid assigning pci bars
to the mmconfig area. I just tried to assign a graphics card and put it
right over it. Thanks,
Alex
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 04/25] ahci: add ide device initialization helper
2012-09-13 20:12 ` [Qemu-devel] [PATCH 04/25] ahci: add ide device initialization helper Jason Baron
@ 2012-09-21 14:05 ` Markus Armbruster
2012-09-21 19:37 ` Jason Baron
0 siblings, 1 reply; 74+ messages in thread
From: Markus Armbruster @ 2012-09-21 14:05 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber
Jason Baron <jbaron@redhat.com> writes:
> From: Isaku Yamahata <yamahata@valinux.co.jp>
>
> Introduce a helper function which initializes the ahci port with ide devices.
> It will be used by q35 support.
>
> Cc: Alexander Graf <agraf@suse.de>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jason Baron <jbaron@redhat.com>
> ---
> hw/ide.h | 3 +++
> hw/ide/ahci.c | 16 ++++++++++++++++
> 2 files changed, 19 insertions(+), 0 deletions(-)
>
> diff --git a/hw/ide.h b/hw/ide.h
> index 2db4079..8df872e 100644
> --- a/hw/ide.h
> +++ b/hw/ide.h
> @@ -36,4 +36,7 @@ int ide_get_bios_chs_trans(BusState *bus, int unit);
> /* ide/core.c */
> void ide_drive_get(DriveInfo **hd, int max_bus);
>
> +/* ide/ahci.c */
> +void pci_ahci_ide_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table);
> +
> #endif /* HW_IDE_H */
> diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
> index 5ea3cad..9561210 100644
> --- a/hw/ide/ahci.c
> +++ b/hw/ide/ahci.c
> @@ -1260,3 +1260,19 @@ static void sysbus_ahci_register_types(void)
> }
>
> type_init(sysbus_ahci_register_types)
> +
> +void pci_ahci_ide_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)
> +{
> + struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card, pci_dev);
> + int i;
> +
> + for (i = 0; i < dev->ahci.ports; i++) {
> + /* master device only, ignore slaves */
> + if (hd_table[i * MAX_IDE_DEVS] == NULL) {
> + continue;
> + }
> + ide_create_drive(&dev->ahci.dev[i].port, 0,
> + hd_table[i * MAX_IDE_DEVS]);
> + }
> +}
> +
Ignores odd entries in hd_table[] (MAX_IDE_DEVS is 2). Here's my
attempt at explaining why.
-drive has parameters bus, unit, and index. index and (bus, unit) are
related in a well-known way that depends on parameter if. For if=ide,
index = bus * 2 + unit. This relationship is ABI, i.e. it cannot be
changed.
"bus * 2 + unit" makes sense for IDE, because each IDE bus can connect
two IDE devices, "master" and "slave".
Boards implementing IDE reject drives with (bus, unit) that make no
sense for the board's IDE controller(s). A typical board has a single
controller with two buses, which means bus > 1 get rejected.
q35 implements AHCI instead of IDE. It connects if=ide drives to AHCI,
because that's felt to be convenient.
An AHCI port can connect a single AHCI device, unlike an IDE bus. This
patch identifies maps -drive's bus to AHCI port number.
PATCH 11/25 sets up argument hd_table[] as follows:
ide_drive_get(hd, MAX_SATA_PORTS);
This rejects bus > MAX_SATA_PORTS. It doesn't reject unit == 1. I
believe these get silently ignored. Bug or feature?
Should we reject unit == 1 instead?
Should we map -drive's index to AHCI port number instead?
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 04/25] ahci: add ide device initialization helper
2012-09-21 14:05 ` Markus Armbruster
@ 2012-09-21 19:37 ` Jason Baron
2012-09-24 16:52 ` Markus Armbruster
0 siblings, 1 reply; 74+ messages in thread
From: Jason Baron @ 2012-09-21 19:37 UTC (permalink / raw)
To: Markus Armbruster
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber
On Fri, Sep 21, 2012 at 04:05:14PM +0200, Markus Armbruster wrote:
> Jason Baron <jbaron@redhat.com> writes:
>
> > From: Isaku Yamahata <yamahata@valinux.co.jp>
> >
> > Introduce a helper function which initializes the ahci port with ide devices.
> > It will be used by q35 support.
> >
> > Cc: Alexander Graf <agraf@suse.de>
> > Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> > Signed-off-by: Jason Baron <jbaron@redhat.com>
> > ---
> > hw/ide.h | 3 +++
> > hw/ide/ahci.c | 16 ++++++++++++++++
> > 2 files changed, 19 insertions(+), 0 deletions(-)
> >
> > diff --git a/hw/ide.h b/hw/ide.h
> > index 2db4079..8df872e 100644
> > --- a/hw/ide.h
> > +++ b/hw/ide.h
> > @@ -36,4 +36,7 @@ int ide_get_bios_chs_trans(BusState *bus, int unit);
> > /* ide/core.c */
> > void ide_drive_get(DriveInfo **hd, int max_bus);
> >
> > +/* ide/ahci.c */
> > +void pci_ahci_ide_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table);
> > +
> > #endif /* HW_IDE_H */
> > diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
> > index 5ea3cad..9561210 100644
> > --- a/hw/ide/ahci.c
> > +++ b/hw/ide/ahci.c
> > @@ -1260,3 +1260,19 @@ static void sysbus_ahci_register_types(void)
> > }
> >
> > type_init(sysbus_ahci_register_types)
> > +
> > +void pci_ahci_ide_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)
> > +{
> > + struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card, pci_dev);
> > + int i;
> > +
> > + for (i = 0; i < dev->ahci.ports; i++) {
> > + /* master device only, ignore slaves */
> > + if (hd_table[i * MAX_IDE_DEVS] == NULL) {
> > + continue;
> > + }
> > + ide_create_drive(&dev->ahci.dev[i].port, 0,
> > + hd_table[i * MAX_IDE_DEVS]);
> > + }
> > +}
> > +
>
> Ignores odd entries in hd_table[] (MAX_IDE_DEVS is 2). Here's my
> attempt at explaining why.
>
> -drive has parameters bus, unit, and index. index and (bus, unit) are
> related in a well-known way that depends on parameter if. For if=ide,
> index = bus * 2 + unit. This relationship is ABI, i.e. it cannot be
> changed.
>
> "bus * 2 + unit" makes sense for IDE, because each IDE bus can connect
> two IDE devices, "master" and "slave".
>
> Boards implementing IDE reject drives with (bus, unit) that make no
> sense for the board's IDE controller(s). A typical board has a single
> controller with two buses, which means bus > 1 get rejected.
>
> q35 implements AHCI instead of IDE. It connects if=ide drives to AHCI,
> because that's felt to be convenient.
>
> An AHCI port can connect a single AHCI device, unlike an IDE bus. This
> patch identifies maps -drive's bus to AHCI port number.
>
> PATCH 11/25 sets up argument hd_table[] as follows:
>
> ide_drive_get(hd, MAX_SATA_PORTS);
>
> This rejects bus > MAX_SATA_PORTS. It doesn't reject unit == 1. I
> believe these get silently ignored. Bug or feature?
>
> Should we reject unit == 1 instead?
>
> Should we map -drive's index to AHCI port number instead?
Right, so now that we have ide disks that can be attached to either the
legacy ide controller or to ahci, I think we need to differentiate which
controller we mean. That is, as proposed q35 is treating -drive if=ide
as an ide attached to the ahci controller. I think that is broken
behavior b/c we need a way to differentiate between the controllers.
As Alexander Graf has proposed before, I think we need a -drive if=ahci
introduced. In that case, I think we reject unit > 0, as you've
suggested.
In terms of the current q35 patch series, I think the first step would
be to introduce the ahci interface type, and have hda-hdd be added with
the default type for q35 of ahci. Then, we can simply fetch ahci drives
of index 0-3, and populate the controller, without any of this skipping
odd numbers stuff.
The next step would then to add if=ahci interface to -drive.
Thanks,
-Jason
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 04/25] ahci: add ide device initialization helper
2012-09-21 19:37 ` Jason Baron
@ 2012-09-24 16:52 ` Markus Armbruster
2012-09-24 17:23 ` Jason Baron
0 siblings, 1 reply; 74+ messages in thread
From: Markus Armbruster @ 2012-09-24 16:52 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, alex.williamson, mst, jan.kiszka, qemu-devel, agraf,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
Jason Baron <jbaron@redhat.com> writes:
> On Fri, Sep 21, 2012 at 04:05:14PM +0200, Markus Armbruster wrote:
>> Jason Baron <jbaron@redhat.com> writes:
>>
>> > From: Isaku Yamahata <yamahata@valinux.co.jp>
>> >
>> > Introduce a helper function which initializes the ahci port with
>> > ide devices.
>> > It will be used by q35 support.
>> >
>> > Cc: Alexander Graf <agraf@suse.de>
>> > Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
>> > Signed-off-by: Jason Baron <jbaron@redhat.com>
>> > ---
>> > hw/ide.h | 3 +++
>> > hw/ide/ahci.c | 16 ++++++++++++++++
>> > 2 files changed, 19 insertions(+), 0 deletions(-)
>> >
>> > diff --git a/hw/ide.h b/hw/ide.h
>> > index 2db4079..8df872e 100644
>> > --- a/hw/ide.h
>> > +++ b/hw/ide.h
>> > @@ -36,4 +36,7 @@ int ide_get_bios_chs_trans(BusState *bus, int unit);
>> > /* ide/core.c */
>> > void ide_drive_get(DriveInfo **hd, int max_bus);
>> >
>> > +/* ide/ahci.c */
>> > +void pci_ahci_ide_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table);
>> > +
>> > #endif /* HW_IDE_H */
>> > diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
>> > index 5ea3cad..9561210 100644
>> > --- a/hw/ide/ahci.c
>> > +++ b/hw/ide/ahci.c
>> > @@ -1260,3 +1260,19 @@ static void sysbus_ahci_register_types(void)
>> > }
>> >
>> > type_init(sysbus_ahci_register_types)
>> > +
>> > +void pci_ahci_ide_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)
>> > +{
>> > + struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card,
>> > pci_dev);
>> > + int i;
>> > +
>> > + for (i = 0; i < dev->ahci.ports; i++) {
>> > + /* master device only, ignore slaves */
>> > + if (hd_table[i * MAX_IDE_DEVS] == NULL) {
>> > + continue;
>> > + }
>> > + ide_create_drive(&dev->ahci.dev[i].port, 0,
>> > + hd_table[i * MAX_IDE_DEVS]);
>> > + }
>> > +}
>> > +
>>
>> Ignores odd entries in hd_table[] (MAX_IDE_DEVS is 2). Here's my
>> attempt at explaining why.
>>
>> -drive has parameters bus, unit, and index. index and (bus, unit) are
>> related in a well-known way that depends on parameter if. For if=ide,
>> index = bus * 2 + unit. This relationship is ABI, i.e. it cannot be
>> changed.
>>
>> "bus * 2 + unit" makes sense for IDE, because each IDE bus can connect
>> two IDE devices, "master" and "slave".
>>
>> Boards implementing IDE reject drives with (bus, unit) that make no
>> sense for the board's IDE controller(s). A typical board has a single
>> controller with two buses, which means bus > 1 get rejected.
>>
>> q35 implements AHCI instead of IDE. It connects if=ide drives to AHCI,
>> because that's felt to be convenient.
>>
>> An AHCI port can connect a single AHCI device, unlike an IDE bus. This
>> patch identifies maps -drive's bus to AHCI port number.
>>
>> PATCH 11/25 sets up argument hd_table[] as follows:
>>
>> ide_drive_get(hd, MAX_SATA_PORTS);
>>
>> This rejects bus > MAX_SATA_PORTS. It doesn't reject unit == 1. I
>> believe these get silently ignored. Bug or feature?
>>
>> Should we reject unit == 1 instead?
>>
>> Should we map -drive's index to AHCI port number instead?
>
> Right, so now that we have ide disks that can be attached to either the
> legacy ide controller or to ahci, I think we need to differentiate which
> controller we mean. That is, as proposed q35 is treating -drive if=ide
> as an ide attached to the ahci controller. I think that is broken
> behavior b/c we need a way to differentiate between the controllers.
What exactly is broken?
> As Alexander Graf has proposed before, I think we need a -drive if=ahci
> introduced. In that case, I think we reject unit > 0, as you've
> suggested.
Achieved by setting if_max_devs[IF_AHCI] to one. bus becomes an alias
for index, and unit must be zero.
Alternatively, keep if_max_devs[IF_AHCI] zero. Swaps role of bus and
unit.
Alex had if_max_devs[IF_AHCI] = 6.
> In terms of the current q35 patch series, I think the first step would
> be to introduce the ahci interface type, and have hda-hdd be added with
> the default type for q35 of ahci. Then, we can simply fetch ahci drives
> of index 0-3, and populate the controller, without any of this skipping
> odd numbers stuff.
>
> The next step would then to add if=ahci interface to -drive.
We discussed if=ahci at length before, without reaching consensus. I'd
rather not rehash the old arguments again. Instead, let's examine how
the command line should behave, and only then figure out how to get
that.
1. Drives created with -hd[a-d], -cdrom, or the non-option image
argument should connect to well-known connectors of the board's
preferred controller.
For current pc, the preferred controller is piix3-ide. -hda connects
to its primary bus as master, -hdb as slave. -hdc connects to its
secondary bus as master, -hdd as slave.
For pseries, the preferred controller is spapr-vscsi. -hda connects
as SCSI ID 0, -hdb as 1, and so forth.
For s390-virtio, the preferred controller is virtio-blk-s390. -hda
and -hdb connect to their own virtio-blk-s390 controller, -hdc and
-hdd get silently ignored. Yes, that's wacky. Your current q35
patch is similarly wacky, as far as I can tell: -hdb and -hdd get
silently ignored.
For q35, the preferred controller is ich9-ahci. I'd expect -hda to
connect to port 0, -hdb to port 1, and so forth.
Below the hood, -hda is currently like -drive index=0,media=disk,
-hd[b-d] same with index=1..3, and -cdrom is like -drive
index=2,media=cdrom, independent of the board.
It follows that -cdrom connects to the same connector as -hdc for all
boards. Fine for pc, but may not be as fine for some other boards.
You can't use both -hdc and -cdrom at the same time.
The non-option image argument is equivalent to -hda. You can't use
both at the same time.
2. Drives created with -drive without if, index, bus, and unit connect
to the next unused connector of the board's preferred controller.
If all connectors are in use, behavior currently depends on the
board, I think.
3. -drive parameters (if, index) provide more control over the connector
to use.
Which controller you get for which if depends on the board. So does
the meaning of index. The details can get messy.
For instance, drives with (if, index) the board doesn't support
sometimes get ignored silently, and sometimes get flagged as error.
Currently, -drive without parameter if is equivalent to either if=ide
or if=scsi. Could be changed for new machine types.
For q35, -drive index=0..5 should connect to ports 0..5 of the
board's ich9-ahci.
4. -drive parameters (bus, unit) are an alternate way to specify
parameter index. The mapping between index and (bus, unit) depends
on the board.
Actually, it depends only on parameter if right now. For if=ide,
index = bus * 2 + unit, unit<2. For if=scsi, index = bus * 7 + unit,
unit < 7. For everything else, index = unit, bus = 0. We might want
to make it depend on the board, see commit 27d6bf40.
For q35, we want index = bus * 6 + unit, unit<5.
An easy way to get that is new if=ahci. Backfires when an AHCI
controller with a different number of ports shows up.
We really should make the mapping between index and (bus, unit)
depend on the board. And then we can just as well use if=ide to
refer to q35's one and only IDE-like controller ich9-ahci.
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 04/25] ahci: add ide device initialization helper
2012-09-24 16:52 ` Markus Armbruster
@ 2012-09-24 17:23 ` Jason Baron
2012-09-26 8:15 ` Markus Armbruster
0 siblings, 1 reply; 74+ messages in thread
From: Jason Baron @ 2012-09-24 17:23 UTC (permalink / raw)
To: Markus Armbruster
Cc: aliguori, alex.williamson, mst, jan.kiszka, qemu-devel, agraf,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
On Mon, Sep 24, 2012 at 06:52:29PM +0200, Markus Armbruster wrote:
> Jason Baron <jbaron@redhat.com> writes:
>
> > On Fri, Sep 21, 2012 at 04:05:14PM +0200, Markus Armbruster wrote:
> >> Jason Baron <jbaron@redhat.com> writes:
> >>
> >> > From: Isaku Yamahata <yamahata@valinux.co.jp>
> >> >
> >> > Introduce a helper function which initializes the ahci port with
> >> > ide devices.
> >> > It will be used by q35 support.
> >> >
> >> > Cc: Alexander Graf <agraf@suse.de>
> >> > Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> >> > Signed-off-by: Jason Baron <jbaron@redhat.com>
> >> > ---
> >> > hw/ide.h | 3 +++
> >> > hw/ide/ahci.c | 16 ++++++++++++++++
> >> > 2 files changed, 19 insertions(+), 0 deletions(-)
> >> >
> >> > diff --git a/hw/ide.h b/hw/ide.h
> >> > index 2db4079..8df872e 100644
> >> > --- a/hw/ide.h
> >> > +++ b/hw/ide.h
> >> > @@ -36,4 +36,7 @@ int ide_get_bios_chs_trans(BusState *bus, int unit);
> >> > /* ide/core.c */
> >> > void ide_drive_get(DriveInfo **hd, int max_bus);
> >> >
> >> > +/* ide/ahci.c */
> >> > +void pci_ahci_ide_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table);
> >> > +
> >> > #endif /* HW_IDE_H */
> >> > diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
> >> > index 5ea3cad..9561210 100644
> >> > --- a/hw/ide/ahci.c
> >> > +++ b/hw/ide/ahci.c
> >> > @@ -1260,3 +1260,19 @@ static void sysbus_ahci_register_types(void)
> >> > }
> >> >
> >> > type_init(sysbus_ahci_register_types)
> >> > +
> >> > +void pci_ahci_ide_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)
> >> > +{
> >> > + struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card,
> >> > pci_dev);
> >> > + int i;
> >> > +
> >> > + for (i = 0; i < dev->ahci.ports; i++) {
> >> > + /* master device only, ignore slaves */
> >> > + if (hd_table[i * MAX_IDE_DEVS] == NULL) {
> >> > + continue;
> >> > + }
> >> > + ide_create_drive(&dev->ahci.dev[i].port, 0,
> >> > + hd_table[i * MAX_IDE_DEVS]);
> >> > + }
> >> > +}
> >> > +
> >>
> >> Ignores odd entries in hd_table[] (MAX_IDE_DEVS is 2). Here's my
> >> attempt at explaining why.
> >>
> >> -drive has parameters bus, unit, and index. index and (bus, unit) are
> >> related in a well-known way that depends on parameter if. For if=ide,
> >> index = bus * 2 + unit. This relationship is ABI, i.e. it cannot be
> >> changed.
> >>
> >> "bus * 2 + unit" makes sense for IDE, because each IDE bus can connect
> >> two IDE devices, "master" and "slave".
> >>
> >> Boards implementing IDE reject drives with (bus, unit) that make no
> >> sense for the board's IDE controller(s). A typical board has a single
> >> controller with two buses, which means bus > 1 get rejected.
> >>
> >> q35 implements AHCI instead of IDE. It connects if=ide drives to AHCI,
> >> because that's felt to be convenient.
> >>
> >> An AHCI port can connect a single AHCI device, unlike an IDE bus. This
> >> patch identifies maps -drive's bus to AHCI port number.
> >>
> >> PATCH 11/25 sets up argument hd_table[] as follows:
> >>
> >> ide_drive_get(hd, MAX_SATA_PORTS);
> >>
> >> This rejects bus > MAX_SATA_PORTS. It doesn't reject unit == 1. I
> >> believe these get silently ignored. Bug or feature?
> >>
> >> Should we reject unit == 1 instead?
> >>
> >> Should we map -drive's index to AHCI port number instead?
> >
> > Right, so now that we have ide disks that can be attached to either the
> > legacy ide controller or to ahci, I think we need to differentiate which
> > controller we mean. That is, as proposed q35 is treating -drive if=ide
> > as an ide attached to the ahci controller. I think that is broken
> > behavior b/c we need a way to differentiate between the controllers.
>
> What exactly is broken?
>
I think that -drive if=ide should result in a disk attached piix3-ide.
Not in an ide disk attached to the ahci controller (which is current q35
bahavior, and is 'broken' b/c we don't want that to change after q35 is
introdued). The reason being is that I think there should be an easy way
to create an ide drive on piix3-ide, and an ide drive on the ahci
controller. But it sounds like you don't agree with this point.
> > As Alexander Graf has proposed before, I think we need a -drive if=ahci
> > introduced. In that case, I think we reject unit > 0, as you've
> > suggested.
>
> Achieved by setting if_max_devs[IF_AHCI] to one. bus becomes an alias
> for index, and unit must be zero.
>
> Alternatively, keep if_max_devs[IF_AHCI] zero. Swaps role of bus and
> unit.
>
> Alex had if_max_devs[IF_AHCI] = 6.
>
> > In terms of the current q35 patch series, I think the first step would
> > be to introduce the ahci interface type, and have hda-hdd be added with
> > the default type for q35 of ahci. Then, we can simply fetch ahci drives
> > of index 0-3, and populate the controller, without any of this skipping
> > odd numbers stuff.
> >
> > The next step would then to add if=ahci interface to -drive.
>
> We discussed if=ahci at length before, without reaching consensus. I'd
> rather not rehash the old arguments again. Instead, let's examine how
> the command line should behave, and only then figure out how to get
> that.
>
> 1. Drives created with -hd[a-d], -cdrom, or the non-option image
> argument should connect to well-known connectors of the board's
> preferred controller.
>
> For current pc, the preferred controller is piix3-ide. -hda connects
> to its primary bus as master, -hdb as slave. -hdc connects to its
> secondary bus as master, -hdd as slave.
>
> For pseries, the preferred controller is spapr-vscsi. -hda connects
> as SCSI ID 0, -hdb as 1, and so forth.
>
> For s390-virtio, the preferred controller is virtio-blk-s390. -hda
> and -hdb connect to their own virtio-blk-s390 controller, -hdc and
> -hdd get silently ignored. Yes, that's wacky. Your current q35
> patch is similarly wacky, as far as I can tell: -hdb and -hdd get
> silently ignored.
>
> For q35, the preferred controller is ich9-ahci. I'd expect -hda to
> connect to port 0, -hdb to port 1, and so forth.
>
> Below the hood, -hda is currently like -drive index=0,media=disk,
> -hd[b-d] same with index=1..3, and -cdrom is like -drive
> index=2,media=cdrom, independent of the board.
>
> It follows that -cdrom connects to the same connector as -hdc for all
> boards. Fine for pc, but may not be as fine for some other boards.
> You can't use both -hdc and -cdrom at the same time.
>
> The non-option image argument is equivalent to -hda. You can't use
> both at the same time.
>
> 2. Drives created with -drive without if, index, bus, and unit connect
> to the next unused connector of the board's preferred controller.
>
> If all connectors are in use, behavior currently depends on the
> board, I think.
>
> 3. -drive parameters (if, index) provide more control over the connector
> to use.
>
> Which controller you get for which if depends on the board. So does
> the meaning of index. The details can get messy.
>
> For instance, drives with (if, index) the board doesn't support
> sometimes get ignored silently, and sometimes get flagged as error.
>
> Currently, -drive without parameter if is equivalent to either if=ide
> or if=scsi. Could be changed for new machine types.
>
> For q35, -drive index=0..5 should connect to ports 0..5 of the
> board's ich9-ahci.
>
> 4. -drive parameters (bus, unit) are an alternate way to specify
> parameter index. The mapping between index and (bus, unit) depends
> on the board.
>
> Actually, it depends only on parameter if right now. For if=ide,
> index = bus * 2 + unit, unit<2. For if=scsi, index = bus * 7 + unit,
> unit < 7. For everything else, index = unit, bus = 0. We might want
> to make it depend on the board, see commit 27d6bf40.
>
> For q35, we want index = bus * 6 + unit, unit<5.
>
> An easy way to get that is new if=ahci. Backfires when an AHCI
> controller with a different number of ports shows up.
>
I agree with points 1-4.
> We really should make the mapping between index and (bus, unit)
> depend on the board. And then we can just as well use if=ide to
> refer to q35's one and only IDE-like controller ich9-ahci.
I agree mapping should depend on the board.
But I'm not sure about using if=ide to use ich9-ahci. I'm suggesting
that if=ide should continue to refer to piix3-ide.
Thanks,
-Jason
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 04/25] ahci: add ide device initialization helper
2012-09-24 17:23 ` Jason Baron
@ 2012-09-26 8:15 ` Markus Armbruster
2012-09-26 10:43 ` Kevin Wolf
2012-09-27 17:59 ` Jason Baron
0 siblings, 2 replies; 74+ messages in thread
From: Markus Armbruster @ 2012-09-26 8:15 UTC (permalink / raw)
To: Jason Baron
Cc: aliguori, juzhang, mst, jan.kiszka, qemu-devel, agraf, yamahata,
alex.williamson, kevin, avi, mkletzan, lcapitulino, afaerber
Jason Baron <jbaron@redhat.com> writes:
> On Mon, Sep 24, 2012 at 06:52:29PM +0200, Markus Armbruster wrote:
>> Jason Baron <jbaron@redhat.com> writes:
>>
>> > On Fri, Sep 21, 2012 at 04:05:14PM +0200, Markus Armbruster wrote:
>> >> Jason Baron <jbaron@redhat.com> writes:
>> >>
>> >> > From: Isaku Yamahata <yamahata@valinux.co.jp>
>> >> >
>> >> > Introduce a helper function which initializes the ahci port with
>> >> > ide devices.
>> >> > It will be used by q35 support.
>> >> >
>> >> > Cc: Alexander Graf <agraf@suse.de>
>> >> > Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
>> >> > Signed-off-by: Jason Baron <jbaron@redhat.com>
>> >> > ---
>> >> > hw/ide.h | 3 +++
>> >> > hw/ide/ahci.c | 16 ++++++++++++++++
>> >> > 2 files changed, 19 insertions(+), 0 deletions(-)
>> >> >
>> >> > diff --git a/hw/ide.h b/hw/ide.h
>> >> > index 2db4079..8df872e 100644
>> >> > --- a/hw/ide.h
>> >> > +++ b/hw/ide.h
>> >> > @@ -36,4 +36,7 @@ int ide_get_bios_chs_trans(BusState *bus, int unit);
>> >> > /* ide/core.c */
>> >> > void ide_drive_get(DriveInfo **hd, int max_bus);
>> >> >
>> >> > +/* ide/ahci.c */
>> >> > +void pci_ahci_ide_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table);
>> >> > +
>> >> > #endif /* HW_IDE_H */
>> >> > diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
>> >> > index 5ea3cad..9561210 100644
>> >> > --- a/hw/ide/ahci.c
>> >> > +++ b/hw/ide/ahci.c
>> >> > @@ -1260,3 +1260,19 @@ static void sysbus_ahci_register_types(void)
>> >> > }
>> >> >
>> >> > type_init(sysbus_ahci_register_types)
>> >> > +
>> >> > +void pci_ahci_ide_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)
>> >> > +{
>> >> > + struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card,
>> >> > pci_dev);
>> >> > + int i;
>> >> > +
>> >> > + for (i = 0; i < dev->ahci.ports; i++) {
>> >> > + /* master device only, ignore slaves */
>> >> > + if (hd_table[i * MAX_IDE_DEVS] == NULL) {
>> >> > + continue;
>> >> > + }
>> >> > + ide_create_drive(&dev->ahci.dev[i].port, 0,
>> >> > + hd_table[i * MAX_IDE_DEVS]);
>> >> > + }
>> >> > +}
>> >> > +
>> >>
>> >> Ignores odd entries in hd_table[] (MAX_IDE_DEVS is 2). Here's my
>> >> attempt at explaining why.
>> >>
>> >> -drive has parameters bus, unit, and index. index and (bus, unit) are
>> >> related in a well-known way that depends on parameter if. For if=ide,
>> >> index = bus * 2 + unit. This relationship is ABI, i.e. it cannot be
>> >> changed.
>> >>
>> >> "bus * 2 + unit" makes sense for IDE, because each IDE bus can connect
>> >> two IDE devices, "master" and "slave".
>> >>
>> >> Boards implementing IDE reject drives with (bus, unit) that make no
>> >> sense for the board's IDE controller(s). A typical board has a single
>> >> controller with two buses, which means bus > 1 get rejected.
>> >>
>> >> q35 implements AHCI instead of IDE. It connects if=ide drives to AHCI,
>> >> because that's felt to be convenient.
>> >>
>> >> An AHCI port can connect a single AHCI device, unlike an IDE bus. This
>> >> patch identifies maps -drive's bus to AHCI port number.
>> >>
>> >> PATCH 11/25 sets up argument hd_table[] as follows:
>> >>
>> >> ide_drive_get(hd, MAX_SATA_PORTS);
>> >>
>> >> This rejects bus > MAX_SATA_PORTS. It doesn't reject unit == 1. I
>> >> believe these get silently ignored. Bug or feature?
>> >>
>> >> Should we reject unit == 1 instead?
>> >>
>> >> Should we map -drive's index to AHCI port number instead?
>> >
>> > Right, so now that we have ide disks that can be attached to either the
>> > legacy ide controller or to ahci, I think we need to differentiate which
>> > controller we mean. That is, as proposed q35 is treating -drive if=ide
>> > as an ide attached to the ahci controller. I think that is broken
>> > behavior b/c we need a way to differentiate between the controllers.
>>
>> What exactly is broken?
>>
>
> I think that -drive if=ide should result in a disk attached piix3-ide.
> Not in an ide disk attached to the ahci controller (which is current q35
> bahavior, and is 'broken' b/c we don't want that to change after q35 is
> introdued). The reason being is that I think there should be an easy way
> to create an ide drive on piix3-ide, and an ide drive on the ahci
> controller. But it sounds like you don't agree with this point.
Two issues with that:
1. Why should q35 have a piix3-ide? The ICH9 southbridge provides only
SATA, so the board needs additional circuitry to provide PATA. As far
as I can tell, intel's Q35 doesn't. ICH9-based boards that do certainly
won't use a piix3-ide, because that's a *function* of the PIIX
southbridge device. It doesn't exist separately.
2. Why should we connect -drive if=ide to a slow PATA controller instead
of a perfectly servicable SATA controller?
>> > As Alexander Graf has proposed before, I think we need a -drive if=ahci
>> > introduced. In that case, I think we reject unit > 0, as you've
>> > suggested.
>>
>> Achieved by setting if_max_devs[IF_AHCI] to one. bus becomes an alias
>> for index, and unit must be zero.
>>
>> Alternatively, keep if_max_devs[IF_AHCI] zero. Swaps role of bus and
>> unit.
>>
>> Alex had if_max_devs[IF_AHCI] = 6.
>>
>> > In terms of the current q35 patch series, I think the first step would
>> > be to introduce the ahci interface type, and have hda-hdd be added with
>> > the default type for q35 of ahci. Then, we can simply fetch ahci drives
>> > of index 0-3, and populate the controller, without any of this skipping
>> > odd numbers stuff.
>> >
>> > The next step would then to add if=ahci interface to -drive.
>>
>> We discussed if=ahci at length before, without reaching consensus. I'd
>> rather not rehash the old arguments again. Instead, let's examine how
>> the command line should behave, and only then figure out how to get
>> that.
>>
>> 1. Drives created with -hd[a-d], -cdrom, or the non-option image
>> argument should connect to well-known connectors of the board's
>> preferred controller.
>>
>> For current pc, the preferred controller is piix3-ide. -hda connects
>> to its primary bus as master, -hdb as slave. -hdc connects to its
>> secondary bus as master, -hdd as slave.
>>
>> For pseries, the preferred controller is spapr-vscsi. -hda connects
>> as SCSI ID 0, -hdb as 1, and so forth.
>>
>> For s390-virtio, the preferred controller is virtio-blk-s390. -hda
>> and -hdb connect to their own virtio-blk-s390 controller, -hdc and
>> -hdd get silently ignored. Yes, that's wacky. Your current q35
>> patch is similarly wacky, as far as I can tell: -hdb and -hdd get
>> silently ignored.
>>
>> For q35, the preferred controller is ich9-ahci. I'd expect -hda to
>> connect to port 0, -hdb to port 1, and so forth.
>>
>> Below the hood, -hda is currently like -drive index=0,media=disk,
>> -hd[b-d] same with index=1..3, and -cdrom is like -drive
>> index=2,media=cdrom, independent of the board.
>>
>> It follows that -cdrom connects to the same connector as -hdc for all
>> boards. Fine for pc, but may not be as fine for some other boards.
>> You can't use both -hdc and -cdrom at the same time.
>>
>> The non-option image argument is equivalent to -hda. You can't use
>> both at the same time.
>>
>> 2. Drives created with -drive without if, index, bus, and unit connect
>> to the next unused connector of the board's preferred controller.
>>
>> If all connectors are in use, behavior currently depends on the
>> board, I think.
>>
>> 3. -drive parameters (if, index) provide more control over the connector
>> to use.
>>
>> Which controller you get for which if depends on the board. So does
>> the meaning of index. The details can get messy.
>>
>> For instance, drives with (if, index) the board doesn't support
>> sometimes get ignored silently, and sometimes get flagged as error.
>>
>> Currently, -drive without parameter if is equivalent to either if=ide
>> or if=scsi. Could be changed for new machine types.
>>
>> For q35, -drive index=0..5 should connect to ports 0..5 of the
>> board's ich9-ahci.
>>
>> 4. -drive parameters (bus, unit) are an alternate way to specify
>> parameter index. The mapping between index and (bus, unit) depends
>> on the board.
>>
>> Actually, it depends only on parameter if right now. For if=ide,
>> index = bus * 2 + unit, unit<2. For if=scsi, index = bus * 7 + unit,
>> unit < 7. For everything else, index = unit, bus = 0. We might want
>> to make it depend on the board, see commit 27d6bf40.
>>
>> For q35, we want index = bus * 6 + unit, unit<5.
>>
>> An easy way to get that is new if=ahci. Backfires when an AHCI
>> controller with a different number of ports shows up.
>>
>
> I agree with points 1-4.
>
>> We really should make the mapping between index and (bus, unit)
>> depend on the board. And then we can just as well use if=ide to
>> refer to q35's one and only IDE-like controller ich9-ahci.
>
> I agree mapping should depend on the board.
We agree on the important things then.
> But I'm not sure about using if=ide to use ich9-ahci. I'm suggesting
> that if=ide should continue to refer to piix3-ide.
Perhaps it should mean "the board's preferred ATA controller", perhaps
it should mean "the board's preferred PATA controller". Certainly
debatable.
If the latter, not necessarily piix3-ide.
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 04/25] ahci: add ide device initialization helper
2012-09-26 8:15 ` Markus Armbruster
@ 2012-09-26 10:43 ` Kevin Wolf
2012-09-27 17:59 ` Jason Baron
1 sibling, 0 replies; 74+ messages in thread
From: Kevin Wolf @ 2012-09-26 10:43 UTC (permalink / raw)
To: Markus Armbruster
Cc: aliguori, alex.williamson, mst, jan.kiszka, Jason Baron,
qemu-devel, agraf, yamahata, juzhang, kevin, avi, mkletzan,
lcapitulino, afaerber
Am 26.09.2012 10:15, schrieb Markus Armbruster:
> Jason Baron <jbaron@redhat.com> writes:
>> I think that -drive if=ide should result in a disk attached piix3-ide.
>> Not in an ide disk attached to the ahci controller (which is current q35
>> bahavior, and is 'broken' b/c we don't want that to change after q35 is
>> introdued). The reason being is that I think there should be an easy way
>> to create an ide drive on piix3-ide, and an ide drive on the ahci
>> controller. But it sounds like you don't agree with this point.
>
> Two issues with that:
>
> 1. Why should q35 have a piix3-ide? The ICH9 southbridge provides only
> SATA, so the board needs additional circuitry to provide PATA. As far
> as I can tell, intel's Q35 doesn't. ICH9-based boards that do certainly
> won't use a piix3-ide, because that's a *function* of the PIIX
> southbridge device. It doesn't exist separately.
>
> 2. Why should we connect -drive if=ide to a slow PATA controller instead
> of a perfectly servicable SATA controller?
Because the guest OS doesn't have an AHCI driver.
But I don't think that connecting to a slow PATA controller describes
exactly what we would ideally want to emulate. We'll probably want to
emulate a SATA controller that is in IDE emulation mode (or whatever it
is called). But as long as we don't have it, the PATA controller is
probably the right thing to provide.
>> But I'm not sure about using if=ide to use ich9-ahci. I'm suggesting
>> that if=ide should continue to refer to piix3-ide.
>
> Perhaps it should mean "the board's preferred ATA controller", perhaps
> it should mean "the board's preferred PATA controller". Certainly
> debatable.
>
> If the latter, not necessarily piix3-ide.
I'd rephrase as "the board's preferred way to provide an IDE interface",
but yes, I think that's the real question.
If we ever want to make Q35 the default, if=ide must implement this
semantics. If we want to stay with PIIX forever, we have a choice. I'm
leaning towards implementing it anyway and just making if=ahci the
default for Q35 if no if is specified at all.
Kevin
^ permalink raw reply [flat|nested] 74+ messages in thread
* Re: [Qemu-devel] [PATCH 04/25] ahci: add ide device initialization helper
2012-09-26 8:15 ` Markus Armbruster
2012-09-26 10:43 ` Kevin Wolf
@ 2012-09-27 17:59 ` Jason Baron
1 sibling, 0 replies; 74+ messages in thread
From: Jason Baron @ 2012-09-27 17:59 UTC (permalink / raw)
To: Markus Armbruster
Cc: aliguori, alex.williamson, mst, jan.kiszka, qemu-devel, agraf,
yamahata, juzhang, kevin, avi, mkletzan, lcapitulino, afaerber
On Wed, Sep 26, 2012 at 10:15:39AM +0200, Markus Armbruster wrote:
> Jason Baron <jbaron@redhat.com> writes:
>
> > On Mon, Sep 24, 2012 at 06:52:29PM +0200, Markus Armbruster wrote:
> >> Jason Baron <jbaron@redhat.com> writes:
> >>
> >> > On Fri, Sep 21, 2012 at 04:05:14PM +0200, Markus Armbruster wrote:
> >> >> Jason Baron <jbaron@redhat.com> writes:
> >> >>
> >> >> > From: Isaku Yamahata <yamahata@valinux.co.jp>
> >> >> >
> >> >> > Introduce a helper function which initializes the ahci port with
> >> >> > ide devices.
> >> >> > It will be used by q35 support.
> >> >> >
> >> >> > Cc: Alexander Graf <agraf@suse.de>
> >> >> > Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> >> >> > Signed-off-by: Jason Baron <jbaron@redhat.com>
> >> >> > ---
> >> >> > hw/ide.h | 3 +++
> >> >> > hw/ide/ahci.c | 16 ++++++++++++++++
> >> >> > 2 files changed, 19 insertions(+), 0 deletions(-)
> >> >> >
> >> >> > diff --git a/hw/ide.h b/hw/ide.h
> >> >> > index 2db4079..8df872e 100644
> >> >> > --- a/hw/ide.h
> >> >> > +++ b/hw/ide.h
> >> >> > @@ -36,4 +36,7 @@ int ide_get_bios_chs_trans(BusState *bus, int unit);
> >> >> > /* ide/core.c */
> >> >> > void ide_drive_get(DriveInfo **hd, int max_bus);
> >> >> >
> >> >> > +/* ide/ahci.c */
> >> >> > +void pci_ahci_ide_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table);
> >> >> > +
> >> >> > #endif /* HW_IDE_H */
> >> >> > diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c
> >> >> > index 5ea3cad..9561210 100644
> >> >> > --- a/hw/ide/ahci.c
> >> >> > +++ b/hw/ide/ahci.c
> >> >> > @@ -1260,3 +1260,19 @@ static void sysbus_ahci_register_types(void)
> >> >> > }
> >> >> >
> >> >> > type_init(sysbus_ahci_register_types)
> >> >> > +
> >> >> > +void pci_ahci_ide_create_devs(PCIDevice *pci_dev, DriveInfo **hd_table)
> >> >> > +{
> >> >> > + struct AHCIPCIState *dev = DO_UPCAST(struct AHCIPCIState, card,
> >> >> > pci_dev);
> >> >> > + int i;
> >> >> > +
> >> >> > + for (i = 0; i < dev->ahci.ports; i++) {
> >> >> > + /* master device only, ignore slaves */
> >> >> > + if (hd_table[i * MAX_IDE_DEVS] == NULL) {
> >> >> > + continue;
> >> >> > + }
> >> >> > + ide_create_drive(&dev->ahci.dev[i].port, 0,
> >> >> > + hd_table[i * MAX_IDE_DEVS]);
> >> >> > + }
> >> >> > +}
> >> >> > +
> >> >>
> >> >> Ignores odd entries in hd_table[] (MAX_IDE_DEVS is 2). Here's my
> >> >> attempt at explaining why.
> >> >>
> >> >> -drive has parameters bus, unit, and index. index and (bus, unit) are
> >> >> related in a well-known way that depends on parameter if. For if=ide,
> >> >> index = bus * 2 + unit. This relationship is ABI, i.e. it cannot be
> >> >> changed.
> >> >>
> >> >> "bus * 2 + unit" makes sense for IDE, because each IDE bus can connect
> >> >> two IDE devices, "master" and "slave".
> >> >>
> >> >> Boards implementing IDE reject drives with (bus, unit) that make no
> >> >> sense for the board's IDE controller(s). A typical board has a single
> >> >> controller with two buses, which means bus > 1 get rejected.
> >> >>
> >> >> q35 implements AHCI instead of IDE. It connects if=ide drives to AHCI,
> >> >> because that's felt to be convenient.
> >> >>
> >> >> An AHCI port can connect a single AHCI device, unlike an IDE bus. This
> >> >> patch identifies maps -drive's bus to AHCI port number.
> >> >>
> >> >> PATCH 11/25 sets up argument hd_table[] as follows:
> >> >>
> >> >> ide_drive_get(hd, MAX_SATA_PORTS);
> >> >>
> >> >> This rejects bus > MAX_SATA_PORTS. It doesn't reject unit == 1. I
> >> >> believe these get silently ignored. Bug or feature?
> >> >>
> >> >> Should we reject unit == 1 instead?
> >> >>
> >> >> Should we map -drive's index to AHCI port number instead?
> >> >
> >> > Right, so now that we have ide disks that can be attached to either the
> >> > legacy ide controller or to ahci, I think we need to differentiate which
> >> > controller we mean. That is, as proposed q35 is treating -drive if=ide
> >> > as an ide attached to the ahci controller. I think that is broken
> >> > behavior b/c we need a way to differentiate between the controllers.
> >>
> >> What exactly is broken?
> >>
> >
> > I think that -drive if=ide should result in a disk attached piix3-ide.
> > Not in an ide disk attached to the ahci controller (which is current q35
> > bahavior, and is 'broken' b/c we don't want that to change after q35 is
> > introdued). The reason being is that I think there should be an easy way
> > to create an ide drive on piix3-ide, and an ide drive on the ahci
> > controller. But it sounds like you don't agree with this point.
>
> Two issues with that:
>
> 1. Why should q35 have a piix3-ide? The ICH9 southbridge provides only
> SATA, so the board needs additional circuitry to provide PATA. As far
> as I can tell, intel's Q35 doesn't. ICH9-based boards that do certainly
> won't use a piix3-ide, because that's a *function* of the PIIX
> southbridge device. It doesn't exist separately.
>
> 2. Why should we connect -drive if=ide to a slow PATA controller instead
> of a perfectly servicable SATA controller?
>
The only way I can install windows xp, and various bsd flavors at the
momemnt is by using the PATA controller.
> >> > As Alexander Graf has proposed before, I think we need a -drive if=ahci
> >> > introduced. In that case, I think we reject unit > 0, as you've
> >> > suggested.
> >>
> >> Achieved by setting if_max_devs[IF_AHCI] to one. bus becomes an alias
> >> for index, and unit must be zero.
> >>
> >> Alternatively, keep if_max_devs[IF_AHCI] zero. Swaps role of bus and
> >> unit.
> >>
> >> Alex had if_max_devs[IF_AHCI] = 6.
> >>
> >> > In terms of the current q35 patch series, I think the first step would
> >> > be to introduce the ahci interface type, and have hda-hdd be added with
> >> > the default type for q35 of ahci. Then, we can simply fetch ahci drives
> >> > of index 0-3, and populate the controller, without any of this skipping
> >> > odd numbers stuff.
> >> >
> >> > The next step would then to add if=ahci interface to -drive.
> >>
> >> We discussed if=ahci at length before, without reaching consensus. I'd
> >> rather not rehash the old arguments again. Instead, let's examine how
> >> the command line should behave, and only then figure out how to get
> >> that.
> >>
> >> 1. Drives created with -hd[a-d], -cdrom, or the non-option image
> >> argument should connect to well-known connectors of the board's
> >> preferred controller.
> >>
> >> For current pc, the preferred controller is piix3-ide. -hda connects
> >> to its primary bus as master, -hdb as slave. -hdc connects to its
> >> secondary bus as master, -hdd as slave.
> >>
> >> For pseries, the preferred controller is spapr-vscsi. -hda connects
> >> as SCSI ID 0, -hdb as 1, and so forth.
> >>
> >> For s390-virtio, the preferred controller is virtio-blk-s390. -hda
> >> and -hdb connect to their own virtio-blk-s390 controller, -hdc and
> >> -hdd get silently ignored. Yes, that's wacky. Your current q35
> >> patch is similarly wacky, as far as I can tell: -hdb and -hdd get
> >> silently ignored.
> >>
> >> For q35, the preferred controller is ich9-ahci. I'd expect -hda to
> >> connect to port 0, -hdb to port 1, and so forth.
> >>
> >> Below the hood, -hda is currently like -drive index=0,media=disk,
> >> -hd[b-d] same with index=1..3, and -cdrom is like -drive
> >> index=2,media=cdrom, independent of the board.
> >>
> >> It follows that -cdrom connects to the same connector as -hdc for all
> >> boards. Fine for pc, but may not be as fine for some other boards.
> >> You can't use both -hdc and -cdrom at the same time.
> >>
> >> The non-option image argument is equivalent to -hda. You can't use
> >> both at the same time.
> >>
> >> 2. Drives created with -drive without if, index, bus, and unit connect
> >> to the next unused connector of the board's preferred controller.
> >>
> >> If all connectors are in use, behavior currently depends on the
> >> board, I think.
> >>
> >> 3. -drive parameters (if, index) provide more control over the connector
> >> to use.
> >>
> >> Which controller you get for which if depends on the board. So does
> >> the meaning of index. The details can get messy.
> >>
> >> For instance, drives with (if, index) the board doesn't support
> >> sometimes get ignored silently, and sometimes get flagged as error.
> >>
> >> Currently, -drive without parameter if is equivalent to either if=ide
> >> or if=scsi. Could be changed for new machine types.
> >>
> >> For q35, -drive index=0..5 should connect to ports 0..5 of the
> >> board's ich9-ahci.
> >>
> >> 4. -drive parameters (bus, unit) are an alternate way to specify
> >> parameter index. The mapping between index and (bus, unit) depends
> >> on the board.
> >>
> >> Actually, it depends only on parameter if right now. For if=ide,
> >> index = bus * 2 + unit, unit<2. For if=scsi, index = bus * 7 + unit,
> >> unit < 7. For everything else, index = unit, bus = 0. We might want
> >> to make it depend on the board, see commit 27d6bf40.
> >>
> >> For q35, we want index = bus * 6 + unit, unit<5.
> >>
> >> An easy way to get that is new if=ahci. Backfires when an AHCI
> >> controller with a different number of ports shows up.
> >>
> >
> > I agree with points 1-4.
> >
> >> We really should make the mapping between index and (bus, unit)
> >> depend on the board. And then we can just as well use if=ide to
> >> refer to q35's one and only IDE-like controller ich9-ahci.
> >
> > I agree mapping should depend on the board.
>
> We agree on the important things then.
>
> > But I'm not sure about using if=ide to use ich9-ahci. I'm suggesting
> > that if=ide should continue to refer to piix3-ide.
>
> Perhaps it should mean "the board's preferred ATA controller", perhaps
> it should mean "the board's preferred PATA controller". Certainly
> debatable.
>
> If the latter, not necessarily piix3-ide.
>
Sure. My main point was that 'if=ide' in the q35 context doesn't specify a SATA
controller. I think it would be nice to have a short hand way of specify both
PATA and SATA on q35.
Thanks,
-Jason
^ permalink raw reply [flat|nested] 74+ messages in thread
end of thread, other threads:[~2012-09-27 18:00 UTC | newest]
Thread overview: 74+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-09-13 20:12 [Qemu-devel] [PATCH 00/25] q35 series take #1 Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 01/25] pci: pci capability must be in PCI space Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 02/25] pci: add opaque argument to pci_map_irq_fn Jason Baron
2012-09-14 16:32 ` Alex Williamson
2012-09-13 20:12 ` [Qemu-devel] [PATCH 03/25] pci: introduce pci_swizzle_map_irq_fn() for standardized interrupt pin swizzle Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 05/25] pc, pc_piix: split out pc nic initialization Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 04/25] ahci: add ide device initialization helper Jason Baron
2012-09-21 14:05 ` Markus Armbruster
2012-09-21 19:37 ` Jason Baron
2012-09-24 16:52 ` Markus Armbruster
2012-09-24 17:23 ` Jason Baron
2012-09-26 8:15 ` Markus Armbruster
2012-09-26 10:43 ` Kevin Wolf
2012-09-27 17:59 ` Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 06/25] pc: Move ioapic_init() from pc_piix.c to pc.c Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 07/25] pc/piix_pci: factor out smram/pam logic Jason Baron
2012-09-14 18:52 ` Blue Swirl
2012-09-13 20:12 ` [Qemu-devel] [PATCH 08/25] pci_ids: add intel 82801BA pci-to-pci bridge id and PCI_CLASS_SERIAL_SMBUS Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 10/25] pcie: Convert PCIExpressHost to use the QOM Jason Baron
2012-09-15 15:16 ` Andreas Färber
2012-09-13 20:12 ` [Qemu-devel] [PATCH 09/25] pcie: pass pcie window size to pcie_host_mmcfg_update() Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 11/25] q35: Introduce q35 pc based chipset emulator Jason Baron
2012-09-14 7:02 ` Paolo Bonzini
2012-09-14 7:37 ` Gerd Hoffmann
2012-09-14 14:11 ` Jason Baron
2012-09-18 21:28 ` Alex Williamson
2012-09-14 12:26 ` Michael S. Tsirkin
2012-09-14 15:20 ` Jason Baron
2012-09-15 18:14 ` Michael S. Tsirkin
2012-09-16 14:48 ` Anthony Liguori
2012-09-16 15:14 ` Michael S. Tsirkin
2012-09-13 20:12 ` [Qemu-devel] [PATCH 12/25] q35: Re-base q35 to 1.2 Jason Baron
2012-09-14 19:07 ` Blue Swirl
2012-09-13 20:12 ` [Qemu-devel] [PATCH 14/25] q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 13/25] q35: Suppress SMM BIOS initialization under KVM Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 15/25] q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and PCI_STATUS_DETECTED_PARITY from w1cmask Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 16/25] pci: Add class 0xc05 as 'SMBus' Jason Baron
2012-09-14 7:04 ` Paolo Bonzini
2012-09-14 14:24 ` Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 17/25] q35: Add kvmclock support Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 19/25] ahci: add migration support Jason Baron
2012-09-14 8:38 ` Juan Quintela
2012-09-13 20:12 ` [Qemu-devel] [PATCH 18/25] q35: Fix irr initialization for slots 25..31 Jason Baron
2012-09-14 7:05 ` Paolo Bonzini
2012-09-14 14:28 ` Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 20/25] pcie: drop version_id field for live migration Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 21/25] pcie_aer: clear cmask for Advanced Error Interrupt Message Number Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 22/25] ahci: properly reset PxCMD on HBA reset Jason Baron
2012-09-13 20:12 ` [Qemu-devel] [PATCH 23/25] q35: add acpi-based pci hotplug Jason Baron
2012-09-14 18:56 ` Blue Swirl
2012-09-13 20:12 ` [Qemu-devel] [PATCH 24/25] Add a fallback bios file search, if -L fails Jason Baron
2012-09-14 7:09 ` Paolo Bonzini
2012-09-14 10:54 ` Peter Maydell
2012-09-14 19:15 ` Blue Swirl
2012-09-13 20:12 ` [Qemu-devel] [PATCH 25/25] q35: automatically load the q35 dsdt table Jason Baron
2012-09-14 7:08 ` Paolo Bonzini
2012-09-14 7:25 ` Gerd Hoffmann
2012-09-14 7:34 ` Paolo Bonzini
2012-09-13 22:29 ` [Qemu-devel] [PATCH 00/25] q35 series take #1 Alexander Graf
2012-09-14 13:50 ` Jason Baron
2012-09-14 13:56 ` Alexander Graf
2012-09-14 14:08 ` Jason Baron
2012-09-14 14:12 ` Alexander Graf
2012-09-14 15:37 ` Kevin Wolf
2012-09-14 15:14 ` Isaku Yamahata
2012-09-14 15:23 ` Jason Baron
2012-09-14 17:34 ` Isaku Yamahata
2012-09-14 19:01 ` Jason Baron
2012-09-15 0:24 ` Isaku Yamahata
2012-09-15 11:33 ` Paolo Bonzini
2012-09-15 17:35 ` Michael S. Tsirkin
2012-09-15 18:05 ` Michael S. Tsirkin
2012-09-15 17:40 ` Michael S. Tsirkin
2012-09-15 18:02 ` Michael S. Tsirkin
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