From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:39566) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TE0nX-000644-Pm for qemu-devel@nongnu.org; Tue, 18 Sep 2012 12:37:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TE0nQ-0002jh-LB for qemu-devel@nongnu.org; Tue, 18 Sep 2012 12:37:19 -0400 Received: from hall.aurel32.net ([88.191.126.93]:44261) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TE0nQ-0002hX-8G for qemu-devel@nongnu.org; Tue, 18 Sep 2012 12:37:12 -0400 Date: Tue, 18 Sep 2012 18:36:57 +0200 From: Aurelien Jarno Message-ID: <20120918163657.GA24984@ohm.aurel32.net> References: <1347415315-2180-1-git-send-email-proljc@gmail.com> <1347415315-2180-5-git-send-email-proljc@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1347415315-2180-5-git-send-email-proljc@gmail.com> Subject: Re: [Qemu-devel] [PATCH v8 04/14] target-mips-ase-dsp: Add branch instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jia Liu Cc: qemu-devel@nongnu.org On Wed, Sep 12, 2012 at 10:01:45AM +0800, Jia Liu wrote: > Add MIPS ASE DSP Branch instructions. > > Signed-off-by: Jia Liu > --- > target-mips/translate.c | 44 ++++++++++++++++++++++++++++++++++++++++---- > 1 file changed, 40 insertions(+), 4 deletions(-) > > diff --git a/target-mips/translate.c b/target-mips/translate.c > index a983220..dcc0905 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -332,6 +332,14 @@ enum { > OPC_DSHD = (0x05 << 6) | OPC_DBSHFL, > }; > > +/* MIPS DSP REGIMM opcodes */ > +enum { > + OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM, > +#if defined(TARGET_MIPS64) > + OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM, > +#endif > +}; > + > /* Coprocessor 0 (rs field) */ > #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) > > @@ -2833,6 +2841,16 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, > } > btgt = ctx->pc + insn_bytes + offset; > break; > + case OPC_BPOSGE32: > +#if defined(TARGET_MIPS64) > + case OPC_BPOSGE64: > + tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F); > +#else > + tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F); > +#endif > + bcond_compute = 1; > + btgt = ctx->pc + insn_bytes + offset; > + break; > case OPC_J: > case OPC_JAL: > case OPC_JALX: > @@ -3021,6 +3039,16 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, > tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); > MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt); > goto likely; > + case OPC_BPOSGE32: > + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32); > + MIPS_DEBUG("bposge32 %s, " TARGET_FMT_lx, t0, btgt); > + goto not_likely; > +#if defined(TARGET_MIPS64) > + case OPC_BPOSGE64: > + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64); > + MIPS_DEBUG("bposge64 %s, " TARGET_FMT_lx, t0, btgt); > + goto not_likely; > +#endif > case OPC_BLTZALS: > case OPC_BLTZAL: > ctx->hflags |= (opc == OPC_BLTZALS > @@ -11276,10 +11304,6 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, > (ctx->opcode >> 18) & 0x7, imm << 1); > *is_branch = 1; > break; > - case BPOSGE64: > - case BPOSGE32: > - /* MIPS DSP: not implemented */ > - /* Fall through */ > default: > MIPS_INVAL("pool32i"); > generate_exception(ctx, EXCP_RI); > @@ -11468,6 +11492,10 @@ static void decode_micromips32_opc (CPUMIPSState *env, DisasContext *ctx, > do_st: > gen_st(ctx, mips32_op, rt, rs, imm); > break; > + case BPOSGE64: > + case BPOSGE32: > + /* MIPS DSP: not implemented */ > + /* Fall through */ > default: > generate_exception(ctx, EXCP_RI); > break; Why moving BPOSGE32 / BPOSGE64 ? There are still unimplemented, but this new location is not correctly decoded. > @@ -12188,6 +12216,14 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) > check_insn(env, ctx, ISA_MIPS32R2); > /* Treat as NOP. */ > break; > + case OPC_BPOSGE32: /* MIPS DSP branch */ > +#if defined(TARGET_MIPS64) > + case OPC_BPOSGE64: > +#endif > + check_dsp(ctx); > + gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2); > + *is_branch = 1; > + break; > default: /* Invalid */ > MIPS_INVAL("regimm"); > generate_exception(ctx, EXCP_RI); > -- > 1.7.9.5 > > > -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net