From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:39585) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TE0nZ-00066A-OB for qemu-devel@nongnu.org; Tue, 18 Sep 2012 12:37:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TE0nS-0002k5-NV for qemu-devel@nongnu.org; Tue, 18 Sep 2012 12:37:21 -0400 Received: from hall.aurel32.net ([88.191.126.93]:44263) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TE0nS-0002hp-FS for qemu-devel@nongnu.org; Tue, 18 Sep 2012 12:37:14 -0400 Date: Tue, 18 Sep 2012 18:37:00 +0200 From: Aurelien Jarno Message-ID: <20120918163659.GA25141@ohm.aurel32.net> References: <1347415315-2180-1-git-send-email-proljc@gmail.com> <1347415315-2180-6-git-send-email-proljc@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1347415315-2180-6-git-send-email-proljc@gmail.com> Subject: Re: [Qemu-devel] [PATCH v8 05/14] target-mips-ase-dsp: Add load instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jia Liu Cc: qemu-devel@nongnu.org On Wed, Sep 12, 2012 at 10:01:46AM +0800, Jia Liu wrote: > Add MIPS ASE DSP Load instructions. > > Signed-off-by: Jia Liu > --- > target-mips/translate.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 66 insertions(+) > > diff --git a/target-mips/translate.c b/target-mips/translate.c > index dcc0905..f7bb054 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -313,6 +313,9 @@ enum { > OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3, > OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3, > OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3, > + > + /* MIPS DSP Load */ > + OPC_LX_DSP = 0x0A | OPC_SPECIAL3, > }; > > /* BSHFL opcodes */ > @@ -340,6 +343,17 @@ enum { > #endif > }; > > +#define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) > +/* MIPS DSP Load */ > +enum { > + OPC_LBUX = (0x06 << 6) | OPC_LX_DSP, > + OPC_LHX = (0x04 << 6) | OPC_LX_DSP, > + OPC_LWX = (0x00 << 6) | OPC_LX_DSP, > +#if defined(TARGET_MIPS64) > + OPC_LDX = (0x08 << 6) | OPC_LX_DSP, > +#endif > +}; > + > /* Coprocessor 0 (rs field) */ > #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) > > @@ -12174,6 +12188,58 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) > check_insn(env, ctx, INSN_LOONGSON2E); > gen_loongson_integer(ctx, op1, rd, rs, rt); > break; > + case OPC_LX_DSP: > + check_dsp(ctx); > + op2 = MASK_LX(ctx->opcode); > + switch (op2) { > + case OPC_LBUX: > + { > + TCGv addr = tcg_temp_new(); > + > + save_cpu_state(ctx, 0); > + gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]); I don't think this is correct as rs or rt can be the zero register. > + op_ld_lbu(cpu_gpr[rd], addr, ctx); > + tcg_temp_free(addr); > + break; > + } > + case OPC_LHX: > + { > + TCGv addr = tcg_temp_new(); > + > + save_cpu_state(ctx, 0); > + gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]); > + op_ld_lh(cpu_gpr[rd], addr, ctx); > + tcg_temp_free(addr); > + break; > + } > + case OPC_LWX: > + { > + TCGv addr = tcg_temp_new(); > + > + save_cpu_state(ctx, 0); > + gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]); > + op_ld_lw(cpu_gpr[rd], addr, ctx); > + tcg_temp_free(addr); > + break; > + } > +#if defined(TARGET_MIPS64) > + case OPC_LDX: > + { > + TCGv addr = tcg_temp_new(); > + > + save_cpu_state(ctx, 0); > + gen_op_addr_add(ctx, addr, cpu_gpr[rs], cpu_gpr[rt]); > + op_ld_ld(cpu_gpr[rd], addr, ctx); > + tcg_temp_free(addr); > + break; > + } > +#endif > + default: /* Invalid */ > + MIPS_INVAL("MASK LX"); > + generate_exception(ctx, EXCP_RI); > + break; > + } Given you have 4 times the same pattern, you should create a function like gen_ld(), doing the common thing outside of the switch. > + break; > #if defined(TARGET_MIPS64) > case OPC_DEXTM ... OPC_DEXT: > case OPC_DINSM ... OPC_DINS: > -- > 1.7.9.5 > > > -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net