From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:51374) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFMWN-00037m-Qt for qemu-devel@nongnu.org; Sat, 22 Sep 2012 06:01:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TFMWM-0002K5-Fw for qemu-devel@nongnu.org; Sat, 22 Sep 2012 06:01:11 -0400 Received: from hall.aurel32.net ([88.191.126.93]:56702) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TFMWM-0002Jq-7x for qemu-devel@nongnu.org; Sat, 22 Sep 2012 06:01:10 -0400 Date: Sat, 22 Sep 2012 12:01:08 +0200 From: Aurelien Jarno Message-ID: <20120922100107.GG29951@hall.aurel32.net> References: <1348278392-3075-1-git-send-email-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1348278392-3075-1-git-send-email-rth@twiddle.net> Sender: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH] tcg-hppa: Implement movcond List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org On Fri, Sep 21, 2012 at 06:46:32PM -0700, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/hppa/tcg-target.c | 21 +++++++++++++++++++++ > tcg/hppa/tcg-target.h | 2 +- > 2 files changed, 22 insertions(+), 1 deletion(-) > > diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c > index 5385d45..793b90d 100644 > --- a/tcg/hppa/tcg-target.c > +++ b/tcg/hppa/tcg-target.c > @@ -912,6 +912,18 @@ static void tcg_out_setcond2(TCGContext *s, int cond, TCGArg ret, > tcg_out_mov(s, TCG_TYPE_I32, ret, scratch); > } > > +static void tcg_out_movcond(TCGContext *s, int cond, TCGArg ret, > + TCGArg c1, TCGArg c2, int c2const, > + TCGArg v1, int v1const) > +{ > + tcg_out_comclr(s, tcg_invert_cond(cond), TCG_REG_R0, c1, c2, c2const); > + if (v1const) { > + tcg_out_movi(s, TCG_TYPE_I32, ret, v1); > + } else { > + tcg_out_mov(s, TCG_TYPE_I32, ret, v1); > + } > +} > + > #if defined(CONFIG_SOFTMMU) > #include "../../softmmu_defs.h" > > @@ -1520,6 +1532,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, > args[3], const_args[3], args[4], const_args[4]); > break; > > + case INDEX_op_movcond_i32: > + tcg_out_movcond(s, args[5], args[0], args[1], args[2], const_args[2], > + args[3], const_args[3]); > + break; > + > case INDEX_op_add2_i32: > tcg_out_add2(s, args[0], args[1], args[2], args[3], > args[4], args[5], const_args[4]); > @@ -1628,6 +1645,10 @@ static const TCGTargetOpDef hppa_op_defs[] = { > { INDEX_op_setcond_i32, { "r", "rZ", "rI" } }, > { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rI", "rI" } }, > > + /* ??? We can actually support a signed 14-bit arg3, but we > + only have existing constraints for a signed 11-bit. */ > + { INDEX_op_movcond_i32, { "r", "rZ", "rI", "rI", "0" } }, > + What's the problem in adding a constraint for that? The lack of available letters? ;-) > { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rI", "rZ" } }, > { INDEX_op_sub2_i32, { "r", "r", "rI", "rZ", "rK", "rZ" } }, > > diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h > index 4defd28..5351353 100644 > --- a/tcg/hppa/tcg-target.h > +++ b/tcg/hppa/tcg-target.h > @@ -96,7 +96,7 @@ typedef enum { > #define TCG_TARGET_HAS_nand_i32 0 > #define TCG_TARGET_HAS_nor_i32 0 > #define TCG_TARGET_HAS_deposit_i32 1 > -#define TCG_TARGET_HAS_movcond_i32 0 > +#define TCG_TARGET_HAS_movcond_i32 1 > > /* optional instructions automatically implemented */ > #define TCG_TARGET_HAS_neg_i32 0 /* sub rd, 0, rs */ Otherwise looks fine to me. Reviewed-by: Aurelien Jarno -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net