* [Qemu-devel] [PATCH] tcg-hppa: Implement movcond
@ 2012-09-22 1:46 Richard Henderson
2012-09-22 10:01 ` Aurelien Jarno
0 siblings, 1 reply; 4+ messages in thread
From: Richard Henderson @ 2012-09-22 1:46 UTC (permalink / raw)
To: qemu-devel; +Cc: aurelien
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/hppa/tcg-target.c | 21 +++++++++++++++++++++
tcg/hppa/tcg-target.h | 2 +-
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
index 5385d45..793b90d 100644
--- a/tcg/hppa/tcg-target.c
+++ b/tcg/hppa/tcg-target.c
@@ -912,6 +912,18 @@ static void tcg_out_setcond2(TCGContext *s, int cond, TCGArg ret,
tcg_out_mov(s, TCG_TYPE_I32, ret, scratch);
}
+static void tcg_out_movcond(TCGContext *s, int cond, TCGArg ret,
+ TCGArg c1, TCGArg c2, int c2const,
+ TCGArg v1, int v1const)
+{
+ tcg_out_comclr(s, tcg_invert_cond(cond), TCG_REG_R0, c1, c2, c2const);
+ if (v1const) {
+ tcg_out_movi(s, TCG_TYPE_I32, ret, v1);
+ } else {
+ tcg_out_mov(s, TCG_TYPE_I32, ret, v1);
+ }
+}
+
#if defined(CONFIG_SOFTMMU)
#include "../../softmmu_defs.h"
@@ -1520,6 +1532,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
args[3], const_args[3], args[4], const_args[4]);
break;
+ case INDEX_op_movcond_i32:
+ tcg_out_movcond(s, args[5], args[0], args[1], args[2], const_args[2],
+ args[3], const_args[3]);
+ break;
+
case INDEX_op_add2_i32:
tcg_out_add2(s, args[0], args[1], args[2], args[3],
args[4], args[5], const_args[4]);
@@ -1628,6 +1645,10 @@ static const TCGTargetOpDef hppa_op_defs[] = {
{ INDEX_op_setcond_i32, { "r", "rZ", "rI" } },
{ INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rI", "rI" } },
+ /* ??? We can actually support a signed 14-bit arg3, but we
+ only have existing constraints for a signed 11-bit. */
+ { INDEX_op_movcond_i32, { "r", "rZ", "rI", "rI", "0" } },
+
{ INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rI", "rZ" } },
{ INDEX_op_sub2_i32, { "r", "r", "rI", "rZ", "rK", "rZ" } },
diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h
index 4defd28..5351353 100644
--- a/tcg/hppa/tcg-target.h
+++ b/tcg/hppa/tcg-target.h
@@ -96,7 +96,7 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 1
-#define TCG_TARGET_HAS_movcond_i32 0
+#define TCG_TARGET_HAS_movcond_i32 1
/* optional instructions automatically implemented */
#define TCG_TARGET_HAS_neg_i32 0 /* sub rd, 0, rs */
--
1.7.11.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH] tcg-hppa: Implement movcond
2012-09-22 1:46 [Qemu-devel] [PATCH] tcg-hppa: Implement movcond Richard Henderson
@ 2012-09-22 10:01 ` Aurelien Jarno
2012-09-22 12:43 ` Richard Henderson
0 siblings, 1 reply; 4+ messages in thread
From: Aurelien Jarno @ 2012-09-22 10:01 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Fri, Sep 21, 2012 at 06:46:32PM -0700, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> tcg/hppa/tcg-target.c | 21 +++++++++++++++++++++
> tcg/hppa/tcg-target.h | 2 +-
> 2 files changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/tcg/hppa/tcg-target.c b/tcg/hppa/tcg-target.c
> index 5385d45..793b90d 100644
> --- a/tcg/hppa/tcg-target.c
> +++ b/tcg/hppa/tcg-target.c
> @@ -912,6 +912,18 @@ static void tcg_out_setcond2(TCGContext *s, int cond, TCGArg ret,
> tcg_out_mov(s, TCG_TYPE_I32, ret, scratch);
> }
>
> +static void tcg_out_movcond(TCGContext *s, int cond, TCGArg ret,
> + TCGArg c1, TCGArg c2, int c2const,
> + TCGArg v1, int v1const)
> +{
> + tcg_out_comclr(s, tcg_invert_cond(cond), TCG_REG_R0, c1, c2, c2const);
> + if (v1const) {
> + tcg_out_movi(s, TCG_TYPE_I32, ret, v1);
> + } else {
> + tcg_out_mov(s, TCG_TYPE_I32, ret, v1);
> + }
> +}
> +
> #if defined(CONFIG_SOFTMMU)
> #include "../../softmmu_defs.h"
>
> @@ -1520,6 +1532,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
> args[3], const_args[3], args[4], const_args[4]);
> break;
>
> + case INDEX_op_movcond_i32:
> + tcg_out_movcond(s, args[5], args[0], args[1], args[2], const_args[2],
> + args[3], const_args[3]);
> + break;
> +
> case INDEX_op_add2_i32:
> tcg_out_add2(s, args[0], args[1], args[2], args[3],
> args[4], args[5], const_args[4]);
> @@ -1628,6 +1645,10 @@ static const TCGTargetOpDef hppa_op_defs[] = {
> { INDEX_op_setcond_i32, { "r", "rZ", "rI" } },
> { INDEX_op_setcond2_i32, { "r", "rZ", "rZ", "rI", "rI" } },
>
> + /* ??? We can actually support a signed 14-bit arg3, but we
> + only have existing constraints for a signed 11-bit. */
> + { INDEX_op_movcond_i32, { "r", "rZ", "rI", "rI", "0" } },
> +
What's the problem in adding a constraint for that? The lack of
available letters? ;-)
> { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rI", "rZ" } },
> { INDEX_op_sub2_i32, { "r", "r", "rI", "rZ", "rK", "rZ" } },
>
> diff --git a/tcg/hppa/tcg-target.h b/tcg/hppa/tcg-target.h
> index 4defd28..5351353 100644
> --- a/tcg/hppa/tcg-target.h
> +++ b/tcg/hppa/tcg-target.h
> @@ -96,7 +96,7 @@ typedef enum {
> #define TCG_TARGET_HAS_nand_i32 0
> #define TCG_TARGET_HAS_nor_i32 0
> #define TCG_TARGET_HAS_deposit_i32 1
> -#define TCG_TARGET_HAS_movcond_i32 0
> +#define TCG_TARGET_HAS_movcond_i32 1
>
> /* optional instructions automatically implemented */
> #define TCG_TARGET_HAS_neg_i32 0 /* sub rd, 0, rs */
Otherwise looks fine to me.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH] tcg-hppa: Implement movcond
2012-09-22 10:01 ` Aurelien Jarno
@ 2012-09-22 12:43 ` Richard Henderson
2012-09-22 14:55 ` Aurelien Jarno
0 siblings, 1 reply; 4+ messages in thread
From: Richard Henderson @ 2012-09-22 12:43 UTC (permalink / raw)
To: Aurelien Jarno; +Cc: qemu-devel
On 2012-09-22 03:01, Aurelien Jarno wrote:
>> > + /* ??? We can actually support a signed 14-bit arg3, but we
>> > + only have existing constraints for a signed 11-bit. */
>> > + { INDEX_op_movcond_i32, { "r", "rZ", "rI", "rI", "0" } },
>> > +
> What's the problem in adding a constraint for that? The lack of
> available letters? ;-)
>
Just a tad more involved than I had time for at the moment.
Could you go ahead and apply as-is, and I'll get back to
that some other day?
r~
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH] tcg-hppa: Implement movcond
2012-09-22 12:43 ` Richard Henderson
@ 2012-09-22 14:55 ` Aurelien Jarno
0 siblings, 0 replies; 4+ messages in thread
From: Aurelien Jarno @ 2012-09-22 14:55 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Sat, Sep 22, 2012 at 05:43:13AM -0700, Richard Henderson wrote:
> On 2012-09-22 03:01, Aurelien Jarno wrote:
> >> > + /* ??? We can actually support a signed 14-bit arg3, but we
> >> > + only have existing constraints for a signed 11-bit. */
> >> > + { INDEX_op_movcond_i32, { "r", "rZ", "rI", "rI", "0" } },
> >> > +
> > What's the problem in adding a constraint for that? The lack of
> > available letters? ;-)
> >
>
> Just a tad more involved than I had time for at the moment.
> Could you go ahead and apply as-is, and I'll get back to
> that some other day?
>
Applied.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2012-09-22 14:55 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2012-09-22 1:46 [Qemu-devel] [PATCH] tcg-hppa: Implement movcond Richard Henderson
2012-09-22 10:01 ` Aurelien Jarno
2012-09-22 12:43 ` Richard Henderson
2012-09-22 14:55 ` Aurelien Jarno
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).