[Qemu-devel] [PATCH 0/8] Misc tcg improvements

[Qemu-devel] [PATCH 0/8] Misc tcg improvements

[Richard Henderson]

The subject of the andi and assertion patches has come up on this
list earlier this week, between Max Filippov, malc and myself.

The posibility of using deposit to implement concat occurred to
me while working on the MIPS FPU conversion patch.


r~


Richard Henderson (8):
  tcg: Adjust descriptions of *cond opcodes
  tcg: Emit ANDI as EXTU for appropriate constants
  tcg: Optimize initial inputs for ori_i64
  tcg: Emit XORI as NOT for appropriate constants
  tcg: Implement concat*_i64 with deposit_i64
  tcg: Add tcg_debug_assert
  tcg: Sanity check deposit inputs
  tcg: Sanity check goto_tb input

 tcg/README   |  10 ++--
 tcg/tcg-op.h | 182 ++++++++++++++++++++++++++++++++++++++++++-----------------
 tcg/tcg.c    |   4 ++
 tcg/tcg.h    |  10 ++++
 4 files changed, 149 insertions(+), 57 deletions(-)

-- 
1.7.11.4

[Qemu-devel] [PATCH 1/8] tcg: Adjust descriptions of *cond opcodes

[Richard Henderson]

The README file documented the operand ordering of the tcg_gen_*
functions.  Since we're documenting opcodes here, use the true
operand ordering.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Cc: malc <av1474@comtv.ru>
---
 tcg/README | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/tcg/README b/tcg/README
index d03ae05..cd9d9cc 100644
--- a/tcg/README
+++ b/tcg/README
@@ -141,7 +141,7 @@ Define label 'label' at the current program point.
 
 Jump to label.
 
-* brcond_i32/i64 cond, t0, t1, label
+* brcond_i32/i64 t0, t1, cond, label
 
 Conditional jump if t0 cond t1 is true. cond can be:
     TCG_COND_EQ
@@ -301,13 +301,13 @@ This operation would be equivalent to
 
 ********* Conditional moves
 
-* setcond_i32/i64 cond, dest, t1, t2
+* setcond_i32/i64 dest, t1, t2, cond
 
 dest = (t1 cond t2)
 
 Set DEST to 1 if (T1 cond T2) is true, otherwise set to 0.
 
-* movcond_i32/i64 cond, dest, c1, c2, v1, v2
+* movcond_i32/i64 dest, c1, c2, v1, v2, cond
 
 dest = (c1 cond c2 ? v1 : v2)
 
@@ -360,7 +360,7 @@ The following opcodes are internal to TCG.  Thus they are to be implemented by
 32-bit host code generators, but are not to be emitted by guest translators.
 They are emitted as needed by inline functions within "tcg-op.h".
 
-* brcond2_i32 cond, t0_low, t0_high, t1_low, t1_high, label
+* brcond2_i32 t0_low, t0_high, t1_low, t1_high, cond, label
 
 Similar to brcond, except that the 64-bit values T0 and T1
 are formed from two 32-bit arguments.
@@ -377,7 +377,7 @@ is returned in two 32-bit outputs.
 Similar to mul, except two 32-bit (unsigned) inputs T1 and T2 yielding
 the full 64-bit product T0.  The later is returned in two 32-bit outputs.
 
-* setcond2_i32 cond, dest, t1_low, t1_high, t2_low, t2_high
+* setcond2_i32 dest, t1_low, t1_high, t2_low, t2_high, cond
 
 Similar to setcond, except that the 64-bit values T1 and T2 are
 formed from two 32-bit arguments.  The result is a 32-bit value.
-- 
1.7.11.4

[Qemu-devel] [PATCH 2/8] tcg: Emit ANDI as EXTU for appropriate constants

[Richard Henderson]

Note that andi_i64 failed to perform even the minimal
optimizations promised by the README.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg-op.h | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++----------
 1 file changed, 56 insertions(+), 11 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 6d28f82..c8633ff 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -518,18 +518,34 @@ static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
     }
 }
 
-static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
+static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
 {
-    /* some cases can be optimized here */
-    if (arg2 == 0) {
+    TCGv_i32 t0;
+    /* Some cases can be optimized here.  */
+    switch (arg2) {
+    case 0:
         tcg_gen_movi_i32(ret, 0);
-    } else if (arg2 == 0xffffffff) {
+        return;
+    case 0xffffffffu:
         tcg_gen_mov_i32(ret, arg1);
-    } else {
-        TCGv_i32 t0 = tcg_const_i32(arg2);
-        tcg_gen_and_i32(ret, arg1, t0);
-        tcg_temp_free_i32(t0);
-    }
+        return;
+    case 0xffu:
+        /* Don't recurse with tcg_gen_ext8u_i32.  */
+        if (TCG_TARGET_HAS_ext8u_i32) {
+            tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg1);
+            return;
+        }
+        break;
+    case 0xffffu:
+        if (TCG_TARGET_HAS_ext16u_i32) {
+            tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg1);
+            return;
+        }
+        break;
+    }
+    t0 = tcg_const_i32(arg2);
+    tcg_gen_and_i32(ret, arg1, t0);
+    tcg_temp_free_i32(t0);
 }
 
 static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
@@ -1120,9 +1136,38 @@ static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
     }
 }
 
-static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
+static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
 {
-    TCGv_i64 t0 = tcg_const_i64(arg2);
+    TCGv_i64 t0;
+    /* Some cases can be optimized here.  */
+    switch (arg2) {
+    case 0:
+        tcg_gen_movi_i64(ret, 0);
+        return;
+    case 0xffffffffffffffffull:
+        tcg_gen_mov_i64(ret, arg1);
+        return;
+    case 0xffull:
+        /* Don't recurse with tcg_gen_ext8u_i32.  */
+        if (TCG_TARGET_HAS_ext8u_i64) {
+            tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg1);
+            return;
+        }
+        break;
+    case 0xffffu:
+        if (TCG_TARGET_HAS_ext16u_i64) {
+            tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg1);
+            return;
+        }
+        break;
+    case 0xffffffffull:
+        if (TCG_TARGET_HAS_ext32u_i64) {
+            tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg1);
+            return;
+        }
+        break;
+    }
+    t0 = tcg_const_i64(arg2);
     tcg_gen_and_i64(ret, arg1, t0);
     tcg_temp_free_i64(t0);
 }
-- 
1.7.11.4

[Qemu-devel] [PATCH 3/8] tcg: Optimize initial inputs for ori_i64

[Richard Henderson]

Copy the same optimizations from ori_i32.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg-op.h | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index c8633ff..fd16499 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -559,9 +559,9 @@ static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 
 static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 {
-    /* some cases can be optimized here */
-    if (arg2 == 0xffffffff) {
-        tcg_gen_movi_i32(ret, 0xffffffff);
+    /* Some cases can be optimized here.  */
+    if (arg2 == -1) {
+        tcg_gen_movi_i32(ret, -1);
     } else if (arg2 == 0) {
         tcg_gen_mov_i32(ret, arg1);
     } else {
@@ -1183,9 +1183,16 @@ static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 
 static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 {
-    TCGv_i64 t0 = tcg_const_i64(arg2);
-    tcg_gen_or_i64(ret, arg1, t0);
-    tcg_temp_free_i64(t0);
+    /* Some cases can be optimized here.  */
+    if (arg2 == -1) {
+        tcg_gen_movi_i64(ret, -1);
+    } else if (arg2 == 0) {
+        tcg_gen_mov_i64(ret, arg1);
+    } else {
+        TCGv_i64 t0 = tcg_const_i64(arg2);
+        tcg_gen_or_i64(ret, arg1, t0);
+        tcg_temp_free_i64(t0);
+    }
 }
 
 static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-- 
1.7.11.4

[Qemu-devel] [PATCH 4/8] tcg: Emit XORI as NOT for appropriate constants

[Richard Henderson]

Note that xori_i64 failed to perform even the minimal
optimizations promised by the README.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg-op.h | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index fd16499..bcfb60b 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -582,9 +582,12 @@ static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 
 static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
 {
-    /* some cases can be optimized here */
+    /* Some cases can be optimized here.  */
     if (arg2 == 0) {
         tcg_gen_mov_i32(ret, arg1);
+    } else if (arg2 == -1 && TCG_TARGET_HAS_not_i32) {
+        /* Don't recurse with tcg_gen_not_i32.  */
+        tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1);
     } else {
         TCGv_i32 t0 = tcg_const_i32(arg2);
         tcg_gen_xor_i32(ret, arg1, t0);
@@ -1206,9 +1209,17 @@ static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
 
 static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
 {
-    TCGv_i64 t0 = tcg_const_i64(arg2);
-    tcg_gen_xor_i64(ret, arg1, t0);
-    tcg_temp_free_i64(t0);
+    /* Some cases can be optimized here.  */
+    if (arg2 == 0) {
+        tcg_gen_mov_i64(ret, arg1);
+    } else if (arg2 == -1 && TCG_TARGET_HAS_not_i64) {
+        /* Don't recurse with tcg_gen_not_i64.  */
+        tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1);
+    } else {
+        TCGv_i64 t0 = tcg_const_i64(arg2);
+        tcg_gen_xor_i64(ret, arg1, t0);
+        tcg_temp_free_i64(t0);
+    }
 }
 
 static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
-- 
1.7.11.4

[Qemu-devel] [PATCH 5/8] tcg: Implement concat*_i64 with deposit_i64

[Richard Henderson]

For tcg_gen_concat_i32_i64 we only use deposit if the host supports it.
For tcg_gen_concat32_i64 even if the host does not, as we get identical
code before and after.

Note that this relies on the ANDI -> EXTU patch for the identity claim.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg-op.h | 60 ++++++++++++++++++++++++++++++------------------------------
 1 file changed, 30 insertions(+), 30 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index bcfb60b..d2fb283 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -1809,36 +1809,6 @@ static inline void tcg_gen_discard_i64(TCGv_i64 arg)
 #endif
 }
 
-static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high)
-{
-#if TCG_TARGET_REG_BITS == 32
-    tcg_gen_mov_i32(TCGV_LOW(dest), low);
-    tcg_gen_mov_i32(TCGV_HIGH(dest), high);
-#else
-    TCGv_i64 tmp = tcg_temp_new_i64();
-    /* This extension is only needed for type correctness.
-       We may be able to do better given target specific information.  */
-    tcg_gen_extu_i32_i64(tmp, high);
-    tcg_gen_shli_i64(tmp, tmp, 32);
-    tcg_gen_extu_i32_i64(dest, low);
-    tcg_gen_or_i64(dest, dest, tmp);
-    tcg_temp_free_i64(tmp);
-#endif
-}
-
-static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high)
-{
-#if TCG_TARGET_REG_BITS == 32
-    tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high));
-#else
-    TCGv_i64 tmp = tcg_temp_new_i64();
-    tcg_gen_ext32u_i64(dest, low);
-    tcg_gen_shli_i64(tmp, high, 32);
-    tcg_gen_or_i64(dest, dest, tmp);
-    tcg_temp_free_i64(tmp);
-#endif
-}
-
 static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
 {
     if (TCG_TARGET_HAS_andc_i32) {
@@ -2181,6 +2151,36 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
     tcg_temp_free_i64(t1);
 }
 
+static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low,
+                                          TCGv_i32 high)
+{
+#if TCG_TARGET_REG_BITS == 32
+    tcg_gen_mov_i32(TCGV_LOW(dest), low);
+    tcg_gen_mov_i32(TCGV_HIGH(dest), high);
+#else
+    TCGv_i64 tmp = tcg_temp_new_i64();
+    /* These extensions are only needed for type correctness.
+       We may be able to do better given target specific information.  */
+    tcg_gen_extu_i32_i64(tmp, high);
+    tcg_gen_extu_i32_i64(dest, low);
+    /* If deposit is available, use it.  Otherwise use the extra
+       knowledge that we have of the zero-extensions above.  */
+    if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(32, 32)) {
+        tcg_gen_deposit_i64(dest, dest, tmp, 32, 32);
+    } else {
+        tcg_gen_shli_i64(tmp, tmp, 32);
+        tcg_gen_or_i64(dest, dest, tmp);
+    }
+    tcg_temp_free_i64(tmp);
+#endif
+}
+
+static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low,
+                                        TCGv_i64 high)
+{
+    tcg_gen_deposit_i64(dest, low, high, 32, 32);
+}
+
 static inline void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret,
                                        TCGv_i32 c1, TCGv_i32 c2,
                                        TCGv_i32 v1, TCGv_i32 v2)
-- 
1.7.11.4

[Qemu-devel] [PATCH 6/8] tcg: Add tcg_debug_assert

[Richard Henderson]

Like the C assert macro, except only enabled for CONFIG_DEBUG_TCG,
and without having to set _NDEBUG and disable all other asserts at
the same time.

The use of __builtin_unreachable (when available) gives the compiler
the same information, which may (or may not) help it optimize better.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg.h | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/tcg/tcg.h b/tcg/tcg.h
index 48a56f0..4501c15 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -530,6 +530,15 @@ do {\
     abort();\
 } while (0)
 
+#ifdef CONFIG_DEBUG_TCG
+# define tcg_debug_assert(X) do { assert(X); } while (0)
+#elif QEMU_GNUC_PREREQ(4, 5)
+# define tcg_debug_assert(X) \
+    do { if (!(X)) { __builtin_unreachable(); } } while (0)
+#else
+# define tcg_debug_assert(X) do { (void)(X); } while (0)
+#endif
+
 void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs);
 
 #if TCG_TARGET_REG_BITS == 32
-- 
1.7.11.4

[Qemu-devel] [PATCH 7/8] tcg: Sanity check deposit inputs

[Richard Henderson]

Given these are constants, checking once here means everything
after can assume they're correct.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/tcg-op.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index d2fb283..ecb1ac3 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -2081,6 +2081,10 @@ static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
     uint32_t mask;
     TCGv_i32 t1;
 
+    tcg_debug_assert(ofs < 32);
+    tcg_debug_assert(len <= 32);
+    tcg_debug_assert(ofs + len <= 32);
+
     if (ofs == 0 && len == 32) {
         tcg_gen_mov_i32(ret, arg2);
         return;
@@ -2112,6 +2116,10 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
     uint64_t mask;
     TCGv_i64 t1;
 
+    tcg_debug_assert(ofs < 64);
+    tcg_debug_assert(len <= 64);
+    tcg_debug_assert(ofs + len <= 64);
+
     if (ofs == 0 && len == 64) {
         tcg_gen_mov_i64(ret, arg2);
         return;
-- 
1.7.11.4

[Qemu-devel] [PATCH 8/8] tcg: Sanity check goto_tb input

[Richard Henderson]

Checking that we don't try for idx != [01] is trivial.  Checking
that we don't issue more than one of any index requires a tad
more data and some ifdefs protecting that new variable.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Cc: Max Filippov <jcmvbkbc@gmail.com>
---
 tcg/tcg-op.h | 11 +++++++++--
 tcg/tcg.c    |  4 ++++
 tcg/tcg.h    |  1 +
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index ecb1ac3..9bfed48 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -2275,8 +2275,15 @@ static inline void tcg_gen_exit_tb(tcg_target_long val)
     tcg_gen_op1i(INDEX_op_exit_tb, val);
 }
 
-static inline void tcg_gen_goto_tb(int idx)
-{
+static inline void tcg_gen_goto_tb(unsigned idx)
+{
+    /* We only support two chained exits.  */
+    tcg_debug_assert(idx <= 1);
+#ifdef CONFIG_DEBUG_TCG
+    /* Verify that we havn't seen this numbered exit before.  */
+    tcg_debug_assert((tcg_ctx.goto_tb_issue_mask & (1 << idx)) == 0);
+    tcg_ctx.goto_tb_issue_mask |= 1 << idx;
+#endif
     tcg_gen_op1i(INDEX_op_goto_tb, idx);
 }
 
diff --git a/tcg/tcg.c b/tcg/tcg.c
index bb9c995..a703e1e 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -299,6 +299,10 @@ void tcg_func_start(TCGContext *s)
     s->nb_labels = 0;
     s->current_frame_offset = s->frame_start;
 
+#ifdef CONFIG_DEBUG_TCG
+    s->goto_tb_issue_mask = 0;
+#endif
+
     gen_opc_ptr = gen_opc_buf;
     gen_opparam_ptr = gen_opparam_buf;
 }
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 4501c15..af7464a 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -390,6 +390,7 @@ struct TCGContext {
 
 #ifdef CONFIG_DEBUG_TCG
     int temps_in_use;
+    int goto_tb_issue_mask;
 #endif
 };
 
-- 
1.7.11.4

Re: [Qemu-devel] [PATCH 1/8] tcg: Adjust descriptions of *cond opcodes

[malc]

On Fri, 21 Sep 2012, Richard Henderson wrote:

> The README file documented the operand ordering of the tcg_gen_*
> functions.  Since we're documenting opcodes here, use the true
> operand ordering.

Thanks, looks good.

[..snip..]

-- 
mailto:av1474@comtv.ru

Re: [Qemu-devel] [PATCH 8/8] tcg: Sanity check goto_tb input

[Max Filippov]

On 09/22/2012 04:18 AM, Richard Henderson wrote:
> Checking that we don't try for idx != [01] is trivial.  Checking
> that we don't issue more than one of any index requires a tad
> more data and some ifdefs protecting that new variable.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> Cc: Max Filippov <jcmvbkbc@gmail.com>
> ---
>  tcg/tcg-op.h | 11 +++++++++--
>  tcg/tcg.c    |  4 ++++
>  tcg/tcg.h    |  1 +
>  3 files changed, 14 insertions(+), 2 deletions(-)

Cool.
Tested-by: Max Filippov <jcmvbkbc@gmail.com>

-- 
Thanks.
-- Max

Re: [Qemu-devel] [PATCH 1/8] tcg: Adjust descriptions of *cond opcodes

[Aurelien Jarno]

On Fri, Sep 21, 2012 at 05:18:09PM -0700, Richard Henderson wrote:
> The README file documented the operand ordering of the tcg_gen_*
> functions.  Since we're documenting opcodes here, use the true
> operand ordering.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> Cc: malc <av1474@comtv.ru>
> ---
>  tcg/README | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/tcg/README b/tcg/README
> index d03ae05..cd9d9cc 100644
> --- a/tcg/README
> +++ b/tcg/README
> @@ -141,7 +141,7 @@ Define label 'label' at the current program point.
>  
>  Jump to label.
>  
> -* brcond_i32/i64 cond, t0, t1, label
> +* brcond_i32/i64 t0, t1, cond, label
>  
>  Conditional jump if t0 cond t1 is true. cond can be:
>      TCG_COND_EQ
> @@ -301,13 +301,13 @@ This operation would be equivalent to
>  
>  ********* Conditional moves
>  
> -* setcond_i32/i64 cond, dest, t1, t2
> +* setcond_i32/i64 dest, t1, t2, cond
>  
>  dest = (t1 cond t2)
>  
>  Set DEST to 1 if (T1 cond T2) is true, otherwise set to 0.
>  
> -* movcond_i32/i64 cond, dest, c1, c2, v1, v2
> +* movcond_i32/i64 dest, c1, c2, v1, v2, cond
>  
>  dest = (c1 cond c2 ? v1 : v2)
>  
> @@ -360,7 +360,7 @@ The following opcodes are internal to TCG.  Thus they are to be implemented by
>  32-bit host code generators, but are not to be emitted by guest translators.
>  They are emitted as needed by inline functions within "tcg-op.h".
>  
> -* brcond2_i32 cond, t0_low, t0_high, t1_low, t1_high, label
> +* brcond2_i32 t0_low, t0_high, t1_low, t1_high, cond, label
>  
>  Similar to brcond, except that the 64-bit values T0 and T1
>  are formed from two 32-bit arguments.
> @@ -377,7 +377,7 @@ is returned in two 32-bit outputs.
>  Similar to mul, except two 32-bit (unsigned) inputs T1 and T2 yielding
>  the full 64-bit product T0.  The later is returned in two 32-bit outputs.
>  
> -* setcond2_i32 cond, dest, t1_low, t1_high, t2_low, t2_high
> +* setcond2_i32 dest, t1_low, t1_high, t2_low, t2_high, cond
>  
>  Similar to setcond, except that the 64-bit values T1 and T2 are
>  formed from two 32-bit arguments.  The result is a 32-bit value.

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH 2/8] tcg: Emit ANDI as EXTU for appropriate constants

[Aurelien Jarno]

On Fri, Sep 21, 2012 at 05:18:10PM -0700, Richard Henderson wrote:
> Note that andi_i64 failed to perform even the minimal
> optimizations promised by the README.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/tcg-op.h | 67 ++++++++++++++++++++++++++++++++++++++++++++++++++----------
>  1 file changed, 56 insertions(+), 11 deletions(-)
> 
> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
> index 6d28f82..c8633ff 100644
> --- a/tcg/tcg-op.h
> +++ b/tcg/tcg-op.h
> @@ -518,18 +518,34 @@ static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
>      }
>  }
>  
> -static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
> +static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2)
>  {
> -    /* some cases can be optimized here */
> -    if (arg2 == 0) {
> +    TCGv_i32 t0;
> +    /* Some cases can be optimized here.  */
> +    switch (arg2) {
> +    case 0:
>          tcg_gen_movi_i32(ret, 0);
> -    } else if (arg2 == 0xffffffff) {
> +        return;
> +    case 0xffffffffu:
>          tcg_gen_mov_i32(ret, arg1);
> -    } else {
> -        TCGv_i32 t0 = tcg_const_i32(arg2);
> -        tcg_gen_and_i32(ret, arg1, t0);
> -        tcg_temp_free_i32(t0);
> -    }
> +        return;
> +    case 0xffu:
> +        /* Don't recurse with tcg_gen_ext8u_i32.  */
> +        if (TCG_TARGET_HAS_ext8u_i32) {
> +            tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg1);
> +            return;
> +        }
> +        break;
> +    case 0xffffu:
> +        if (TCG_TARGET_HAS_ext16u_i32) {
> +            tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg1);
> +            return;
> +        }
> +        break;
> +    }
> +    t0 = tcg_const_i32(arg2);
> +    tcg_gen_and_i32(ret, arg1, t0);
> +    tcg_temp_free_i32(t0);
>  }
>  
>  static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
> @@ -1120,9 +1136,38 @@ static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
>      }
>  }
>  
> -static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
> +static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2)
>  {
> -    TCGv_i64 t0 = tcg_const_i64(arg2);
> +    TCGv_i64 t0;
> +    /* Some cases can be optimized here.  */
> +    switch (arg2) {
> +    case 0:
> +        tcg_gen_movi_i64(ret, 0);
> +        return;
> +    case 0xffffffffffffffffull:
> +        tcg_gen_mov_i64(ret, arg1);
> +        return;
> +    case 0xffull:
> +        /* Don't recurse with tcg_gen_ext8u_i32.  */
> +        if (TCG_TARGET_HAS_ext8u_i64) {
> +            tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg1);
> +            return;
> +        }
> +        break;
> +    case 0xffffu:
> +        if (TCG_TARGET_HAS_ext16u_i64) {
> +            tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg1);
> +            return;
> +        }
> +        break;
> +    case 0xffffffffull:
> +        if (TCG_TARGET_HAS_ext32u_i64) {
> +            tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg1);
> +            return;
> +        }
> +        break;
> +    }
> +    t0 = tcg_const_i64(arg2);
>      tcg_gen_and_i64(ret, arg1, t0);
>      tcg_temp_free_i64(t0);
>  }
> -- 
> 1.7.11.4
> 
> 

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH 3/8] tcg: Optimize initial inputs for ori_i64

[Aurelien Jarno]

On Fri, Sep 21, 2012 at 05:18:11PM -0700, Richard Henderson wrote:
> Copy the same optimizations from ori_i32.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/tcg-op.h | 19 +++++++++++++------
>  1 file changed, 13 insertions(+), 6 deletions(-)
> 
> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
> index c8633ff..fd16499 100644
> --- a/tcg/tcg-op.h
> +++ b/tcg/tcg-op.h
> @@ -559,9 +559,9 @@ static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
>  
>  static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
>  {
> -    /* some cases can be optimized here */
> -    if (arg2 == 0xffffffff) {
> -        tcg_gen_movi_i32(ret, 0xffffffff);
> +    /* Some cases can be optimized here.  */
> +    if (arg2 == -1) {
> +        tcg_gen_movi_i32(ret, -1);
>      } else if (arg2 == 0) {
>          tcg_gen_mov_i32(ret, arg1);
>      } else {
> @@ -1183,9 +1183,16 @@ static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
>  
>  static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
>  {
> -    TCGv_i64 t0 = tcg_const_i64(arg2);
> -    tcg_gen_or_i64(ret, arg1, t0);
> -    tcg_temp_free_i64(t0);
> +    /* Some cases can be optimized here.  */
> +    if (arg2 == -1) {
> +        tcg_gen_movi_i64(ret, -1);
> +    } else if (arg2 == 0) {
> +        tcg_gen_mov_i64(ret, arg1);
> +    } else {
> +        TCGv_i64 t0 = tcg_const_i64(arg2);
> +        tcg_gen_or_i64(ret, arg1, t0);
> +        tcg_temp_free_i64(t0);
> +    }
>  }
>  
>  static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
> -- 
> 1.7.11.4
> 

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH 4/8] tcg: Emit XORI as NOT for appropriate constants

[Aurelien Jarno]

On Fri, Sep 21, 2012 at 05:18:12PM -0700, Richard Henderson wrote:
> Note that xori_i64 failed to perform even the minimal
> optimizations promised by the README.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/tcg-op.h | 19 +++++++++++++++----
>  1 file changed, 15 insertions(+), 4 deletions(-)
> 
> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
> index fd16499..bcfb60b 100644
> --- a/tcg/tcg-op.h
> +++ b/tcg/tcg-op.h
> @@ -582,9 +582,12 @@ static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
>  
>  static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
>  {
> -    /* some cases can be optimized here */
> +    /* Some cases can be optimized here.  */
>      if (arg2 == 0) {
>          tcg_gen_mov_i32(ret, arg1);
> +    } else if (arg2 == -1 && TCG_TARGET_HAS_not_i32) {
> +        /* Don't recurse with tcg_gen_not_i32.  */
> +        tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1);
>      } else {
>          TCGv_i32 t0 = tcg_const_i32(arg2);
>          tcg_gen_xor_i32(ret, arg1, t0);
> @@ -1206,9 +1209,17 @@ static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
>  
>  static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
>  {
> -    TCGv_i64 t0 = tcg_const_i64(arg2);
> -    tcg_gen_xor_i64(ret, arg1, t0);
> -    tcg_temp_free_i64(t0);
> +    /* Some cases can be optimized here.  */
> +    if (arg2 == 0) {
> +        tcg_gen_mov_i64(ret, arg1);
> +    } else if (arg2 == -1 && TCG_TARGET_HAS_not_i64) {
> +        /* Don't recurse with tcg_gen_not_i64.  */
> +        tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1);
> +    } else {
> +        TCGv_i64 t0 = tcg_const_i64(arg2);
> +        tcg_gen_xor_i64(ret, arg1, t0);
> +        tcg_temp_free_i64(t0);
> +    }
>  }
>  
>  static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
> -- 
> 1.7.11.4
> 

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH 5/8] tcg: Implement concat*_i64 with deposit_i64

[Aurelien Jarno]

On Fri, Sep 21, 2012 at 05:18:13PM -0700, Richard Henderson wrote:
> For tcg_gen_concat_i32_i64 we only use deposit if the host supports it.
> For tcg_gen_concat32_i64 even if the host does not, as we get identical
> code before and after.
> 
> Note that this relies on the ANDI -> EXTU patch for the identity claim.

I don't really get why, andi is not used in this patch.
 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/tcg-op.h | 60 ++++++++++++++++++++++++++++++------------------------------
>  1 file changed, 30 insertions(+), 30 deletions(-)
> 
> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
> index bcfb60b..d2fb283 100644
> --- a/tcg/tcg-op.h
> +++ b/tcg/tcg-op.h
> @@ -1809,36 +1809,6 @@ static inline void tcg_gen_discard_i64(TCGv_i64 arg)
>  #endif
>  }
>  
> -static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high)
> -{
> -#if TCG_TARGET_REG_BITS == 32
> -    tcg_gen_mov_i32(TCGV_LOW(dest), low);
> -    tcg_gen_mov_i32(TCGV_HIGH(dest), high);
> -#else
> -    TCGv_i64 tmp = tcg_temp_new_i64();
> -    /* This extension is only needed for type correctness.
> -       We may be able to do better given target specific information.  */
> -    tcg_gen_extu_i32_i64(tmp, high);
> -    tcg_gen_shli_i64(tmp, tmp, 32);
> -    tcg_gen_extu_i32_i64(dest, low);
> -    tcg_gen_or_i64(dest, dest, tmp);
> -    tcg_temp_free_i64(tmp);
> -#endif
> -}
> -
> -static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high)
> -{
> -#if TCG_TARGET_REG_BITS == 32
> -    tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high));
> -#else
> -    TCGv_i64 tmp = tcg_temp_new_i64();
> -    tcg_gen_ext32u_i64(dest, low);
> -    tcg_gen_shli_i64(tmp, high, 32);
> -    tcg_gen_or_i64(dest, dest, tmp);
> -    tcg_temp_free_i64(tmp);
> -#endif
> -}
> -
>  static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
>  {
>      if (TCG_TARGET_HAS_andc_i32) {
> @@ -2181,6 +2151,36 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
>      tcg_temp_free_i64(t1);
>  }
>  
> +static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low,
> +                                          TCGv_i32 high)
> +{
> +#if TCG_TARGET_REG_BITS == 32
> +    tcg_gen_mov_i32(TCGV_LOW(dest), low);
> +    tcg_gen_mov_i32(TCGV_HIGH(dest), high);
> +#else
> +    TCGv_i64 tmp = tcg_temp_new_i64();
> +    /* These extensions are only needed for type correctness.
> +       We may be able to do better given target specific information.  */
> +    tcg_gen_extu_i32_i64(tmp, high);
> +    tcg_gen_extu_i32_i64(dest, low);
> +    /* If deposit is available, use it.  Otherwise use the extra
> +       knowledge that we have of the zero-extensions above.  */
> +    if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(32, 32)) {
> +        tcg_gen_deposit_i64(dest, dest, tmp, 32, 32);
> +    } else {
> +        tcg_gen_shli_i64(tmp, tmp, 32);
> +        tcg_gen_or_i64(dest, dest, tmp);
> +    }
> +    tcg_temp_free_i64(tmp);
> +#endif
> +}
> +
> +static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low,
> +                                        TCGv_i64 high)
> +{
> +    tcg_gen_deposit_i64(dest, low, high, 32, 32);
> +}
> +
>  static inline void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret,
>                                         TCGv_i32 c1, TCGv_i32 c2,
>                                         TCGv_i32 v1, TCGv_i32 v2)
> -- 
> 1.7.11.4
> 

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH 6/8] tcg: Add tcg_debug_assert

[Aurelien Jarno]

On Fri, Sep 21, 2012 at 05:18:14PM -0700, Richard Henderson wrote:
> Like the C assert macro, except only enabled for CONFIG_DEBUG_TCG,
> and without having to set _NDEBUG and disable all other asserts at
> the same time.
> 
> The use of __builtin_unreachable (when available) gives the compiler
> the same information, which may (or may not) help it optimize better.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/tcg.h | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/tcg/tcg.h b/tcg/tcg.h
> index 48a56f0..4501c15 100644
> --- a/tcg/tcg.h
> +++ b/tcg/tcg.h
> @@ -530,6 +530,15 @@ do {\
>      abort();\
>  } while (0)
>  
> +#ifdef CONFIG_DEBUG_TCG
> +# define tcg_debug_assert(X) do { assert(X); } while (0)
> +#elif QEMU_GNUC_PREREQ(4, 5)
> +# define tcg_debug_assert(X) \
> +    do { if (!(X)) { __builtin_unreachable(); } } while (0)
> +#else
> +# define tcg_debug_assert(X) do { (void)(X); } while (0)
> +#endif
> +
>  void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs);
>  
>  #if TCG_TARGET_REG_BITS == 32
> -- 
> 1.7.11.4
> 

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH 7/8] tcg: Sanity check deposit inputs

[Aurelien Jarno]

On Fri, Sep 21, 2012 at 05:18:15PM -0700, Richard Henderson wrote:
> Given these are constants, checking once here means everything
> after can assume they're correct.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
>  tcg/tcg-op.h | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
> index d2fb283..ecb1ac3 100644
> --- a/tcg/tcg-op.h
> +++ b/tcg/tcg-op.h
> @@ -2081,6 +2081,10 @@ static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
>      uint32_t mask;
>      TCGv_i32 t1;
>  
> +    tcg_debug_assert(ofs < 32);
> +    tcg_debug_assert(len <= 32);
> +    tcg_debug_assert(ofs + len <= 32);
> +
>      if (ofs == 0 && len == 32) {
>          tcg_gen_mov_i32(ret, arg2);
>          return;
> @@ -2112,6 +2116,10 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
>      uint64_t mask;
>      TCGv_i64 t1;
>  
> +    tcg_debug_assert(ofs < 64);
> +    tcg_debug_assert(len <= 64);
> +    tcg_debug_assert(ofs + len <= 64);
> +
>      if (ofs == 0 && len == 64) {
>          tcg_gen_mov_i64(ret, arg2);
>          return;
> -- 
> 1.7.11.4
> 

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH 8/8] tcg: Sanity check goto_tb input

[Aurelien Jarno]

On Fri, Sep 21, 2012 at 05:18:16PM -0700, Richard Henderson wrote:
> Checking that we don't try for idx != [01] is trivial.  Checking
> that we don't issue more than one of any index requires a tad
> more data and some ifdefs protecting that new variable.
> 
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> Cc: Max Filippov <jcmvbkbc@gmail.com>
> ---
>  tcg/tcg-op.h | 11 +++++++++--
>  tcg/tcg.c    |  4 ++++
>  tcg/tcg.h    |  1 +
>  3 files changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
> index ecb1ac3..9bfed48 100644
> --- a/tcg/tcg-op.h
> +++ b/tcg/tcg-op.h
> @@ -2275,8 +2275,15 @@ static inline void tcg_gen_exit_tb(tcg_target_long val)
>      tcg_gen_op1i(INDEX_op_exit_tb, val);
>  }
>  
> -static inline void tcg_gen_goto_tb(int idx)
> -{
> +static inline void tcg_gen_goto_tb(unsigned idx)
> +{
> +    /* We only support two chained exits.  */
> +    tcg_debug_assert(idx <= 1);
> +#ifdef CONFIG_DEBUG_TCG
> +    /* Verify that we havn't seen this numbered exit before.  */
> +    tcg_debug_assert((tcg_ctx.goto_tb_issue_mask & (1 << idx)) == 0);
> +    tcg_ctx.goto_tb_issue_mask |= 1 << idx;
> +#endif
>      tcg_gen_op1i(INDEX_op_goto_tb, idx);
>  }
>  
> diff --git a/tcg/tcg.c b/tcg/tcg.c
> index bb9c995..a703e1e 100644
> --- a/tcg/tcg.c
> +++ b/tcg/tcg.c
> @@ -299,6 +299,10 @@ void tcg_func_start(TCGContext *s)
>      s->nb_labels = 0;
>      s->current_frame_offset = s->frame_start;
>  
> +#ifdef CONFIG_DEBUG_TCG
> +    s->goto_tb_issue_mask = 0;
> +#endif
> +
>      gen_opc_ptr = gen_opc_buf;
>      gen_opparam_ptr = gen_opparam_buf;
>  }
> diff --git a/tcg/tcg.h b/tcg/tcg.h
> index 4501c15..af7464a 100644
> --- a/tcg/tcg.h
> +++ b/tcg/tcg.h
> @@ -390,6 +390,7 @@ struct TCGContext {
>  
>  #ifdef CONFIG_DEBUG_TCG
>      int temps_in_use;
> +    int goto_tb_issue_mask;
>  #endif
>  };
>  

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

Re: [Qemu-devel] [PATCH 5/8] tcg: Implement concat*_i64 with deposit_i64

[Richard Henderson]

On 2012-09-22 12:52, Aurelien Jarno wrote:
> On Fri, Sep 21, 2012 at 05:18:13PM -0700, Richard Henderson wrote:
>> For tcg_gen_concat_i32_i64 we only use deposit if the host supports it.
>> For tcg_gen_concat32_i64 even if the host does not, as we get identical
>> code before and after.
>>
>> Note that this relies on the ANDI -> EXTU patch for the identity claim.
> 
> I don't really get why, andi is not used in this patch.

No, but tcg_gen_deposit uses andi in its fallback implementation.


r~

Re: [Qemu-devel] [PATCH 0/8] Misc tcg improvements

[Aurelien Jarno]

On Fri, Sep 21, 2012 at 05:18:08PM -0700, Richard Henderson wrote:
> The subject of the andi and assertion patches has come up on this
> list earlier this week, between Max Filippov, malc and myself.
> 
> The posibility of using deposit to implement concat occurred to
> me while working on the MIPS FPU conversion patch.
> 
> 
> r~
> 
> 
> Richard Henderson (8):
>   tcg: Adjust descriptions of *cond opcodes
>   tcg: Emit ANDI as EXTU for appropriate constants
>   tcg: Optimize initial inputs for ori_i64
>   tcg: Emit XORI as NOT for appropriate constants
>   tcg: Implement concat*_i64 with deposit_i64
>   tcg: Add tcg_debug_assert
>   tcg: Sanity check deposit inputs
>   tcg: Sanity check goto_tb input
> 
>  tcg/README   |  10 ++--
>  tcg/tcg-op.h | 182 ++++++++++++++++++++++++++++++++++++++++++-----------------
>  tcg/tcg.c    |   4 ++
>  tcg/tcg.h    |  10 ++++
>  4 files changed, 149 insertions(+), 57 deletions(-)
> 

Thanks, all applied.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net