From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47585) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TGdvD-0007DB-7Z for qemu-devel@nongnu.org; Tue, 25 Sep 2012 18:48:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TGdvC-0004Xo-0k for qemu-devel@nongnu.org; Tue, 25 Sep 2012 18:48:07 -0400 Received: from hall.aurel32.net ([88.191.126.93]:45408) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TGdvB-0004Xj-R2 for qemu-devel@nongnu.org; Tue, 25 Sep 2012 18:48:05 -0400 Date: Wed, 26 Sep 2012 00:48:02 +0200 From: Aurelien Jarno Message-ID: <20120925224802.GI23819@ohm.aurel32.net> References: <1348273096-1495-1-git-send-email-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1348273096-1495-1-git-send-email-rth@twiddle.net> Subject: Re: [Qemu-devel] [PATCH 0/8] Misc tcg improvements List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org On Fri, Sep 21, 2012 at 05:18:08PM -0700, Richard Henderson wrote: > The subject of the andi and assertion patches has come up on this > list earlier this week, between Max Filippov, malc and myself. > > The posibility of using deposit to implement concat occurred to > me while working on the MIPS FPU conversion patch. > > > r~ > > > Richard Henderson (8): > tcg: Adjust descriptions of *cond opcodes > tcg: Emit ANDI as EXTU for appropriate constants > tcg: Optimize initial inputs for ori_i64 > tcg: Emit XORI as NOT for appropriate constants > tcg: Implement concat*_i64 with deposit_i64 > tcg: Add tcg_debug_assert > tcg: Sanity check deposit inputs > tcg: Sanity check goto_tb input > > tcg/README | 10 ++-- > tcg/tcg-op.h | 182 ++++++++++++++++++++++++++++++++++++++++++----------------- > tcg/tcg.c | 4 ++ > tcg/tcg.h | 10 ++++ > 4 files changed, 149 insertions(+), 57 deletions(-) > Thanks, all applied. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net