From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:47405) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TH1xO-0006vr-BZ for qemu-devel@nongnu.org; Wed, 26 Sep 2012 20:27:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TH1xN-0005QH-7V for qemu-devel@nongnu.org; Wed, 26 Sep 2012 20:27:58 -0400 Received: from e23smtp08.au.ibm.com ([202.81.31.141]:43154) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TH1xM-0005Ov-Lz for qemu-devel@nongnu.org; Wed, 26 Sep 2012 20:27:57 -0400 Received: from /spool/local by e23smtp08.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 27 Sep 2012 10:27:05 +1000 Date: Thu, 27 Sep 2012 10:03:04 +1000 From: David Gibson Message-ID: <20120927000304.GG31993@truffula.fritz.box> References: <1348629141-8719-1-git-send-email-david@gibson.dropbear.id.au> <1348629141-8719-4-git-send-email-david@gibson.dropbear.id.au> <20120926063645.GK23819@ohm.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20120926063645.GK23819@ohm.aurel32.net> Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 3/6] target-ppc: Extend FPU state for newer POWER CPUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aurelien Jarno Cc: aliguori@us.ibm.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org On Wed, Sep 26, 2012 at 08:36:45AM +0200, Aurelien Jarno wrote: > On Wed, Sep 26, 2012 at 01:12:18PM +1000, David Gibson wrote: > > This patch adds some extra FPU state to CPUPPCState. Specifically, fpscr > > is extended to 64 bits, since some recent CPUs now have more status bits > > than fit inside 64 bits, and we add the 32 VSR registers present on CPUs > > with VSX (these extend the standard FP regs, which together with the > > Altivec/VMX registers form a 64 x 128bit register file for VSX). > > > > We don't actually support the instructions using these extra registers in > > TCG yet, but we still a place to store the state so we can sync it with > > KVM and savevm/loadvm it. This patch updates the savevm code to not > > fail on the extended state, but also does not actually save it - that's > > a project for another patch. > > > > Signed-off-by: David Gibson > > --- > > target-ppc/cpu.h | 4 +++- > > target-ppc/machine.c | 8 ++++++-- > > target-ppc/translate.c | 2 +- > > 3 files changed, 10 insertions(+), 4 deletions(-) > > > > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > > index faf4404..846778f 100644 > > --- a/target-ppc/cpu.h > > +++ b/target-ppc/cpu.h > > @@ -963,7 +963,7 @@ struct CPUPPCState { > > /* floating point registers */ > > float64 fpr[32]; > > /* floating point status and control register */ > > - uint32_t fpscr; > > + uint64_t fpscr; > > This will break the TCG code, as fpscr is mapped as an i32 in TCG. Also > if it is 64-bit only on PPC64 machines, it might be a good idea to > change it to target_ulong instead, and use _tl in the TCG code. Ah, good point, thanks for catching that. Both changes made for the next version. -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson