From: Aurelien Jarno <aurelien@aurel32.net>
To: Richard Henderson <rth@twiddle.net>
Cc: Blue Swirl <blauwirbel@gmail.com>, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 23/23] target-sparc: Optimize conditionals using SUBCC
Date: Mon, 8 Oct 2012 00:40:16 +0200 [thread overview]
Message-ID: <20121007224016.GA12391@ohm.aurel32.net> (raw)
In-Reply-To: <1349481310-9237-24-git-send-email-rth@twiddle.net>
This patch breaks the boot of a linux sparc64 kernel very early in the
boot process. The boot hangs after:
| OpenBIOS for Sparc64
| Configuration device id QEMU version 1 machine id 0
| kernel addr 404000 size 5be6b8
| kernel cmdline root=/dev/vda4 console=ttyS0
| CPUs: 1 x SUNW,UltraSPARC-IIi
| UUID: 00000000-0000-0000-0000-000000000000
| Welcome to OpenBIOS v1.0 built on Aug 19 2012 13:06
| Type 'help' for detailed information
| [sparc64] Kernel already loaded
|
| [ 0.000000] PROMLIB: Sun IEEE Boot Prom 'OBP 3.10.24 1999/01/01 01:01'
| [ 0.000000] PROMLIB: Root node compatible: sun4u
| [ 0.000000] Initializing cgroup subsys cpuset
| [ 0.000000] Initializing cgroup subsys cpu
| [ 0.000000] Linux version 3.2.0-3-sparc64 (Debian 3.2.23-1) (debian-kernel@lists.debian.org) (gcc version 4.6.3 (Debian 4.6.3-5) ) #1 Fri Aug 3 15:37:15 UTC 2012
| [ 0.000000] bootconsole [earlyprom0] enabled
| [ 0.000000] ARCH: SUN4U
| [ 0.000000] Ethernet address: 52:54:00:12:34:56
| [ 0.000000] Kernel: Using 2 locked TLB entries for main kernel image.
| [ 0.000000] Remapping the kernel... done.
| [ 0.000000] OF stdout device is: /pci@1fe,0/ebus@2/su
| [ 0.000000] PROM: Built device tree with 32122 bytes of memory.
On Fri, Oct 05, 2012 at 04:55:10PM -0700, Richard Henderson wrote:
> Aka "normal" comparisons. We now have the infrastructure to
> pass back non-boolean results from gen_compare. This will
> automatically get used by both branches and conditional moves.
>
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-sparc/translate.c | 192 ++++++++++++++++++++++++++++++++---------------
> 1 file changed, 131 insertions(+), 61 deletions(-)
>
> diff --git a/target-sparc/translate.c b/target-sparc/translate.c
> index a7f6407..472eb51 100644
> --- a/target-sparc/translate.c
> +++ b/target-sparc/translate.c
> @@ -1046,83 +1046,153 @@ static void free_compare(DisasCompare *cmp)
> }
> }
>
> -static void gen_compare(DisasCompare *cmp, unsigned int cc, unsigned int cond,
> +static void gen_compare(DisasCompare *cmp, bool xcc, unsigned int cond,
> DisasContext *dc)
> {
> + static int subcc_cond[16] = {
> + -1, /* never */
> + TCG_COND_EQ,
> + TCG_COND_LE,
> + TCG_COND_LT,
> + TCG_COND_LEU,
> + TCG_COND_LTU,
> + -1, /* neg */
> + -1, /* overflow */
> + -1, /* always */
> + TCG_COND_NE,
> + TCG_COND_GT,
> + TCG_COND_GE,
> + TCG_COND_GTU,
> + TCG_COND_GEU,
> + -1, /* pos */
> + -1, /* no overflow */
> + };
> +
> TCGv_i32 r_src;
> TCGv r_dst;
>
> - /* For now we still generate a straight boolean result. */
> - cmp->cond = TCG_COND_NE;
> - cmp->is_bool = true;
> - cmp->g1 = cmp->g2 = false;
> - cmp->c1 = r_dst = tcg_temp_new();
> - cmp->c2 = tcg_const_tl(0);
> -
> #ifdef TARGET_SPARC64
> - if (cc)
> + if (xcc) {
> r_src = cpu_xcc;
> - else
> + } else {
> r_src = cpu_psr;
> + }
> #else
> r_src = cpu_psr;
> #endif
> +
> switch (dc->cc_op) {
> - case CC_OP_FLAGS:
> + case CC_OP_SUB:
> + switch (cond) {
> + case 6: /* neg */
> + case 14: /* pos */
> + cmp->cond = (cond == 6 ? TCG_COND_LT : TCG_COND_GE);
> + cmp->is_bool = false;
> + cmp->g2 = false;
> + cmp->c2 = tcg_const_tl(0);
> +#ifdef TARGET_SPARC64
> + if (!xcc) {
> + cmp->g1 = false;
> + cmp->c1 = tcg_temp_new();
> + tcg_gen_ext32s_tl(cmp->c1, cpu_cc_dst);
> + break;
> + }
> +#endif
> + cmp->g1 = true;
> + cmp->c1 = cpu_cc_dst;
> + break;
> +
> + case 0: /* never */
> + case 8: /* always */
> + case 7: /* overflow */
> + case 15: /* !overflow */
> + goto do_dynamic;
> +
> + default:
> + cmp->cond = subcc_cond[cond];
> + cmp->is_bool = false;
> +#ifdef TARGET_SPARC64
> + if (!xcc) {
> + /* Note that sign-extension works for unsigned compares as
> + long as both operands are sign-extended. */
> + cmp->g1 = cmp->g2 = false;
> + cmp->c1 = tcg_temp_new();
> + cmp->c2 = tcg_temp_new();
> + tcg_gen_ext32s_tl(cmp->c1, cpu_cc_src);
> + tcg_gen_ext32s_tl(cmp->c2, cpu_cc_src2);
> + }
> +#endif
> + cmp->g1 = cmp->g2 = true;
> + cmp->c1 = cpu_cc_src;
> + cmp->c2 = cpu_cc_src2;
> + break;
> + }
> break;
> +
> default:
> + do_dynamic:
> gen_helper_compute_psr(cpu_env);
> dc->cc_op = CC_OP_FLAGS;
> - break;
> - }
> - switch (cond) {
> - case 0x0:
> - gen_op_eval_bn(r_dst);
> - break;
> - case 0x1:
> - gen_op_eval_be(r_dst, r_src);
> - break;
> - case 0x2:
> - gen_op_eval_ble(r_dst, r_src);
> - break;
> - case 0x3:
> - gen_op_eval_bl(r_dst, r_src);
> - break;
> - case 0x4:
> - gen_op_eval_bleu(r_dst, r_src);
> - break;
> - case 0x5:
> - gen_op_eval_bcs(r_dst, r_src);
> - break;
> - case 0x6:
> - gen_op_eval_bneg(r_dst, r_src);
> - break;
> - case 0x7:
> - gen_op_eval_bvs(r_dst, r_src);
> - break;
> - case 0x8:
> - gen_op_eval_ba(r_dst);
> - break;
> - case 0x9:
> - gen_op_eval_bne(r_dst, r_src);
> - break;
> - case 0xa:
> - gen_op_eval_bg(r_dst, r_src);
> - break;
> - case 0xb:
> - gen_op_eval_bge(r_dst, r_src);
> - break;
> - case 0xc:
> - gen_op_eval_bgu(r_dst, r_src);
> - break;
> - case 0xd:
> - gen_op_eval_bcc(r_dst, r_src);
> - break;
> - case 0xe:
> - gen_op_eval_bpos(r_dst, r_src);
> - break;
> - case 0xf:
> - gen_op_eval_bvc(r_dst, r_src);
> + /* FALLTHRU */
> +
> + case CC_OP_FLAGS:
> + /* We're going to generate a boolean result. */
> + cmp->cond = TCG_COND_NE;
> + cmp->is_bool = true;
> + cmp->g1 = cmp->g2 = false;
> + cmp->c1 = r_dst = tcg_temp_new();
> + cmp->c2 = tcg_const_tl(0);
> +
> + switch (cond) {
> + case 0x0:
> + gen_op_eval_bn(r_dst);
> + break;
> + case 0x1:
> + gen_op_eval_be(r_dst, r_src);
> + break;
> + case 0x2:
> + gen_op_eval_ble(r_dst, r_src);
> + break;
> + case 0x3:
> + gen_op_eval_bl(r_dst, r_src);
> + break;
> + case 0x4:
> + gen_op_eval_bleu(r_dst, r_src);
> + break;
> + case 0x5:
> + gen_op_eval_bcs(r_dst, r_src);
> + break;
> + case 0x6:
> + gen_op_eval_bneg(r_dst, r_src);
> + break;
> + case 0x7:
> + gen_op_eval_bvs(r_dst, r_src);
> + break;
> + case 0x8:
> + gen_op_eval_ba(r_dst);
> + break;
> + case 0x9:
> + gen_op_eval_bne(r_dst, r_src);
> + break;
> + case 0xa:
> + gen_op_eval_bg(r_dst, r_src);
> + break;
> + case 0xb:
> + gen_op_eval_bge(r_dst, r_src);
> + break;
> + case 0xc:
> + gen_op_eval_bgu(r_dst, r_src);
> + break;
> + case 0xd:
> + gen_op_eval_bcc(r_dst, r_src);
> + break;
> + case 0xe:
> + gen_op_eval_bpos(r_dst, r_src);
> + break;
> + case 0xf:
> + gen_op_eval_bvc(r_dst, r_src);
> + break;
> + }
> break;
> }
> }
> --
> 1.7.11.4
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
next prev parent reply other threads:[~2012-10-07 22:40 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-05 23:54 [Qemu-devel] [PATCH 00/23] target-sparc comparison improvements Richard Henderson
2012-10-05 23:54 ` [Qemu-devel] [PATCH 01/23] target-sparc: Tidy cpu_dump_state Richard Henderson
2012-10-05 23:54 ` [Qemu-devel] [PATCH 02/23] target-sparc: Make CPU_LOG_INT useful by default Richard Henderson
2012-10-05 23:54 ` [Qemu-devel] [PATCH 03/23] target-sparc: Tidy do_branch interfaces Richard Henderson
2012-10-05 23:54 ` [Qemu-devel] [PATCH 04/23] target-sparc: Tidy flush_cond interface Richard Henderson
2012-10-05 23:54 ` [Qemu-devel] [PATCH 05/23] target-sparc: Tidy gen_trap_ifnofpu interface Richard Henderson
2012-10-05 23:54 ` [Qemu-devel] [PATCH 06/23] target-sparc: Tidy save_state interface Richard Henderson
2012-10-05 23:54 ` [Qemu-devel] [PATCH 07/23] target-sparc: Tidy gen_mov_pc_npc interface Richard Henderson
2012-10-05 23:54 ` [Qemu-devel] [PATCH 08/23] target-sparc: Tidy save_npc interface Richard Henderson
2012-10-05 23:54 ` [Qemu-devel] [PATCH 09/23] target-sparc: Tidy gen_generic_branch interface Richard Henderson
2012-10-05 23:54 ` [Qemu-devel] [PATCH 10/23] target-sparc: Introduce DisasCompare and functions to generate it Richard Henderson
2012-10-05 23:54 ` [Qemu-devel] [PATCH 11/23] target-sparc: Use DisasCompare in Tcc Richard Henderson
2012-10-05 23:54 ` [Qemu-devel] [PATCH 12/23] target-sparc: Use DisasCompare and movcond in FMOVR, FMOVCC Richard Henderson
2012-10-05 23:55 ` [Qemu-devel] [PATCH 13/23] target-sparc: Use DisasCompare and movcond in MOVCC Richard Henderson
2012-10-05 23:55 ` [Qemu-devel] [PATCH 14/23] target-sparc: Use DisasCompare and movcond in MOVR Richard Henderson
2012-10-05 23:55 ` [Qemu-devel] [PATCH 15/23] target-sparc: Use movcond in gen_generic_branch Richard Henderson
2012-10-05 23:55 ` [Qemu-devel] [PATCH 16/23] target-sparc: Move sdivx and udivx out of line Richard Henderson
2012-10-05 23:55 ` [Qemu-devel] [PATCH 17/23] target-sparc: Tidy Tcc Richard Henderson
2012-10-05 23:55 ` [Qemu-devel] [PATCH 18/23] target-sparc: Move taddcctv and tsubcctv out of line Richard Henderson
2012-10-05 23:55 ` [Qemu-devel] [PATCH 19/23] target-sparc: Use movcond in mulscc Richard Henderson
2012-10-05 23:55 ` [Qemu-devel] [PATCH 20/23] target-sparc: Use movcond for FMOV*R Richard Henderson
2012-10-05 23:55 ` [Qemu-devel] [PATCH 21/23] target-sparc: Cleanup "global" temporary allocation Richard Henderson
2012-10-05 23:55 ` [Qemu-devel] [PATCH 22/23] target-sparc: Fall through from not-taken trap Richard Henderson
2012-10-05 23:55 ` [Qemu-devel] [PATCH 23/23] target-sparc: Optimize conditionals using SUBCC Richard Henderson
2012-10-07 18:48 ` Blue Swirl
2012-10-07 19:16 ` Richard Henderson
2012-10-07 22:40 ` Aurelien Jarno [this message]
2012-10-07 18:44 ` [Qemu-devel] [PATCH 00/23] target-sparc comparison improvements Blue Swirl
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