From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59161) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLlLy-0001y4-ON for qemu-devel@nongnu.org; Tue, 09 Oct 2012 21:44:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TLlLx-0000Qi-Mp for qemu-devel@nongnu.org; Tue, 09 Oct 2012 21:44:54 -0400 Received: from mail-ea0-f173.google.com ([209.85.215.173]:61278) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLlLx-0000Qa-Gf for qemu-devel@nongnu.org; Tue, 09 Oct 2012 21:44:53 -0400 Received: by mail-ea0-f173.google.com with SMTP id a1so849eaa.4 for ; Tue, 09 Oct 2012 18:44:52 -0700 (PDT) Date: Wed, 10 Oct 2012 03:44:48 +0200 From: "Edgar E. Iglesias" Message-ID: <20121010014447.GA12372@zapo> References: <1349830006-12124-1-git-send-email-peter.crosthwaite@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1349830006-12124-1-git-send-email-peter.crosthwaite@xilinx.com> Subject: Re: [Qemu-devel] [PULL 0/13] Ehnahced SSI bus support + M25P80 SPI flash + Xilinx SPI controller List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Crosthwaite Cc: qemu-devel@nongnu.org On Wed, Oct 10, 2012 at 10:46:33AM +1000, Peter Crosthwaite wrote: > The following changes since commit 4bb26682f70a5f626cad3e0ac82bf4b6252ea7a4: > Blue Swirl (1): > Merge branch 'master' of git.qemu.org:/pub/git/qemu > > are available in the git repository at: > > git://developer.petalogix.com/public/qemu.git for-upstream/spi-initial.9 > > Peter A. G. Crosthwaite (12): > ssi: Support for multiple attached devices > ssi: Implemented CS behaviour > ssi: Added create_slave_no_init() > qdev: allow multiple qdev_init_gpio_in() calls > stellaris: Removed SSI mux > hw: Added generic FIFO API. > m25p80: Initial implementation of SPI flash device > xilinx_spi: Initial impl. of Xilinx SPI controller > petalogix-ml605: added SPI controller with n25q128 > xilinx_spips: Xilinx Zynq SPI cntrlr device model > xilinx_zynq: Added SPI controllers + flashes > MAINTAINERS: Added maintainerships for SSI Pulled with a minor compiler fix Thanks, Ed