From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:45435) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TMKmC-0004rb-2E for qemu-devel@nongnu.org; Thu, 11 Oct 2012 11:34:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TMKm5-00049H-DG for qemu-devel@nongnu.org; Thu, 11 Oct 2012 11:34:19 -0400 Received: from mx1.redhat.com ([209.132.183.28]:43031) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TMKm5-000495-4p for qemu-devel@nongnu.org; Thu, 11 Oct 2012 11:34:13 -0400 Date: Thu, 11 Oct 2012 11:34:08 -0400 From: Jason Baron Message-ID: <20121011153408.GI3592@redhat.com> References: <20121011105705.GE5552@redhat.com> <20121011142122.GH3592@redhat.com> <20121011144656.GF8983@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20121011144656.GF8983@redhat.com> Subject: Re: [Qemu-devel] [PATCH v2 21/21] q35: add acpi-based pci hotplug. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: agraf@suse.de, aliguori@us.ibm.com, juzhang@redhat.com, jan.kiszka@siemens.com, qemu-devel@nongnu.org, armbru@redhat.com, blauwirbel@gmail.com, yamahata@valinux.co.jp, alex.williamson@redhat.com, kevin@koconnor.net, avi@redhat.com, mkletzan@redhat.com, pbonzini@redhat.com, lcapitulino@redhat.com, afaerber@suse.de, kraxel@redhat.com On Thu, Oct 11, 2012 at 04:46:56PM +0200, Michael S. Tsirkin wrote: > On Thu, Oct 11, 2012 at 10:21:22AM -0400, Jason Baron wrote: > > On Thu, Oct 11, 2012 at 12:57:06PM +0200, Michael S. Tsirkin wrote: > > > On Mon, Oct 08, 2012 at 11:30:39PM -0400, Jason Baron wrote: > > > > From: Jason Baron > > > > > > > > Add piix style acpi hotplug to q35. > > > > > > > > Signed-off-by: Jason Baron > > > > > > Something I don't understand here: this only handles hotplug > > > of devices behind the root, no? > > > Don't we need support for hotplug/hot remove of devices behind > > > bridges? > > > > > > > Yes, this only handles acpi hotplug of devices behind the root. I'm > > trying to reach minimal set of q35 patches that we can build upon. I > > think that this patch gives us at least the same functionality as piix > > does. (Plus there is pcie hotplug). > > > > As you know, I have a proof of concept patch series providing a second > > level of hotplug behind bridges. Unfortunately, it was based on the > > static acpi tables, before Paolo made the hotplug table generation > > dynamic. So it needs quite a bit of re-work. But I know that it should > > work :) > > > > Thanks, > > > > -Jason > > Yes. Reason I ask is because q35 is adding bridges by default now. > Would it be possible to only add them if requested on command line by user > instead? I realize some guests expect devices at specific slots > but this does not apply to bridges I think? > I just tried out getting rid of the bridges by default. So 'lspci' goes from: 00:00.0 Host bridge: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller 00:01.0 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02) 00:02.0 VGA compatible controller: Cirrus Logic GD 5446 00:03.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03) 00:17.0 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02) 00:18.0 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02) 00:1c.0 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02) 00:1c.1 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02) 00:1c.2 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02) 00:1c.3 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02) 00:1c.4 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02) 00:1c.5 PCI bridge: Intel Corporation 5500 Non-Legacy I/O Hub PCI Express Root Port 0 (rev 02) 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 92) 00:1f.0 ISA bridge: Intel Corporation 82801IB (ICH9) LPC Interface Controller (rev 02) 00:1f.2 SATA controller: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller (rev 02) 00:1f.3 SMBus: Intel Corporation 82801I (ICH9 Family) SMBus Controller (rev 02) 03:00.0 PCI bridge: Texas Instruments XIO3130 PCI Express Switch (Upstream) (rev 02) 04:00.0 PCI bridge: Texas Instruments XIO3130 PCI Express Switch (Downstream) (rev 01) 0c:1c.0 PCI bridge: Digital Equipment Corporation DECchip 21154 (rev 05) 0c:1d.0 PCI bridge: Digital Equipment Corporation DECchip 21154 (rev 05) 0c:1e.0 PCI bridge: Digital Equipment Corporation DECchip 21154 (rev 05) 0c:1f.0 PCI bridge: Digital Equipment Corporation DECchip 21154 (rev 05) To: 00:00.0 Host bridge: Intel Corporation 82G33/G31/P35/P31 Express DRAM Controller 00:01.0 VGA compatible controller: Cirrus Logic GD 5446 00:02.0 Ethernet controller: Intel Corporation 82540EM Gigabit Ethernet Controller (rev 03) 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev 92) 00:1f.0 ISA bridge: Intel Corporation 82801IB (ICH9) LPC Interface Controller (rev 02) 00:1f.2 SATA controller: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller (rev 02) 00:1f.3 SMBus: Intel Corporation 82801I (ICH9 Family) SMBus Controller (rev 02) Windows and Linux guests seem fine with either layout. Slots 1-2 are specific to my setup. So this is a pretty minimal set. I think that providing the minimal set of devices is good, since it allows the user to configure things as much as possible. So I am in favor of this more minimal set. My only hesitation is that we pull out, or that I have not included some important piece h/w at a specific slot that a guest might need. Thus potentially breaking existing setups. Perhaps, that might mean a new machine type in the future, if we've messed up? These devices and slots are pulled from the Intel docs on ICH9 and Q35 specs. See: http://www.intel.com/content/www/us/en/io/io-controller-hub-9-datasheet.html Perhaps, Yamahata can comment further on the specific set of bridges? > It would also be nice to add comments explaining why > specific slots were selected e.g. /* BSD XYZ fails to boot unless ahci is at alow 2 */ > etc. Right, its basically just pulled from the Intel spec as mentioned above. > > Also - will adding this code now mean that when adding bridges > we'll need to add compatibility code in bios/qemu in the future? > I don't think so, but maybe you can elaborate this concern more specifically? Thanks, -Jason