Re: [Qemu-devel] [PATCH v11 09/14] target-mips: Add ASE DSP bit/manipulation instructions

[Aurelien Jarno <aurelien@aurel32.net>]

On Wed, Oct 17, 2012 at 03:41:23PM +0800, Jia Liu wrote:
> Hi Aurelien,
> 
> On Wed, Oct 17, 2012 at 2:05 PM, Aurelien Jarno <aurelien@aurel32.net> wrote:
> > On Wed, Oct 17, 2012 at 11:44:41AM +0800, Jia Liu wrote:
> >> Hi Aurelien,
> >>
> >> >> +#ifdef TARGET_MIPS64
> >> >> +    case OPC_ABSQ_S_QH_DSP:
> >> >> +        switch (op2) {
> >> >> +        case OPC_REPL_OB:
> >> >> +            check_dsp(ctx);
> >> >> +            {
> >> >> +                target_long temp;
> >> >> +
> >> >> +                imm = (ctx->opcode >> 16) & 0xFF;
> >> >> +                temp = imm;
> >> >> +                temp = (temp << 8) | temp;
> >> >> +                temp = (temp << 16) | temp;
> >> >> +                temp = (temp << 32) | temp;
> >> >> +                tcg_gen_movi_tl(cpu_gpr[ret], temp);
> >> >> +                break;
> >> >> +            }
> >> >
> >> > This hasn't been fixed, and thus is still wrong.
> >> >
> >>
> >> Thank you for check this again.
> >> May you give me more comment about this please? I'm not sure what
> >> should do here.
> >>
> >
> > The instruction is defined as:
> >
> > | Replicate a immediate byte into all elements of an eight byte vector.
> > |
> > | Description: rd ← immediate || immediate || immediate || immediate || immediate ||
> > |                   immediate || immediate || immediate
> >
> > In your code, I only see the value replicated 4 times, not 8 times.
> >
> 
> Thank you very much, is this code OK?
> 
> case OPC_REPL_OB:
>     check_dsp(ctx);
>     {
>         target_long temp;
> 
>         imm = (ctx->opcode >> 16) & 0xFF;
>         temp = ((uint64_t)imm << 56) | ((uint64_t)imm << 48) |
>             ((uint64_t)imm << 40) | ((uint64_t)imm << 32) |
>             ((uint64_t)imm << 24) | ((uint64_t)imm << 16) |
>             ((uint64_t)imm << 8) | (uint64_t)imm;
>         tcg_gen_movi_tl(cpu_gpr[ret], temp);
>         break;
>     }
> 

Yes, this looks fine now.


-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net